Created attachment 196366 [details] Git style diff Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro
Created attachment 196367 [details] Old-style shar
Anyone able to take a look? It's been over a month.
A commit references this bug: Author: swills Date: Thu Jan 17 23:27:12 UTC 2019 New revision: 490609 URL: https://svnweb.freebsd.org/changeset/ports/490609 Log: cad/verilator: create port Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro PR: 230761 Submitted by: Kevin Zheng <kevinz5000@gmail.com> Changes: head/cad/Makefile head/cad/verilator/ head/cad/verilator/Makefile head/cad/verilator/distinfo head/cad/verilator/pkg-descr head/cad/verilator/pkg-plist
Committed, thanks for the work, sorry it took so long to get it committed.