Created attachment 245410 [details] Patch for adding the new port This port allows to perform VHDL synthesis in yosys using ghdl. Depends on a series of patches: - https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=274238 - https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=274239 - https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=274240 - https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=274241 With the above patches I tested everything in poudriere: https://poudriere.herrhotzenplotz.de/build.html?mastername=release-latest-main&build=2023-10-01_16h35m22s I also did a smoke test by synthesising a simple VHDL design.
Patch looks good, waiting for dependencies to resolve.
A commit in branch main references this bug: URL: https://cgit.FreeBSD.org/ports/commit/?id=7e4f2be406274cd8a33b558308812fe07f1cbfea commit 7e4f2be406274cd8a33b558308812fe07f1cbfea Author: Nico Sonack <nsonack@herrhotzenplotz.de> AuthorDate: 2023-10-01 17:10:29 +0000 Commit: Robert Clausecker <fuz@FreeBSD.org> CommitDate: 2023-10-19 07:07:29 +0000 cad/yosys-ghdl-plugin: Add new port This allows performing synthesis of VHDL using ghdl with yosys. Signed-off-by: Nico Sonack <nsonack@herrhotzenplotz.de> PR: 274243 cad/Makefile | 1 + cad/yosys-ghdl-plugin/Makefile (new) | 32 ++++++++++++++++++++++++++++++++ cad/yosys-ghdl-plugin/distinfo (new) | 3 +++ cad/yosys-ghdl-plugin/pkg-descr (new) | 2 ++ 4 files changed, 38 insertions(+)
Thank you for your contribution.