Attachment #249919 for bug #278311

Lines 58-63 Link Here

(-)b/sys/dev/amdsmn/amdsmn.c (+7 lines)
58	#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0	58	#define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
59	#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */	59	#define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
60	#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630	60	#define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
		61	#define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14b0
61	#define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8	62	#define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
62		63
63	struct pciid;	64	struct pciid;
Lines 102-107 static const struct pciid { Link Here
102	.amdsmn_addr_reg = F17H_SMN_ADDR_REG,	103	.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
103	.amdsmn_data_reg = F17H_SMN_DATA_REG,	104	.amdsmn_data_reg = F17H_SMN_DATA_REG,
104	},	105	},
		106	{
		107	.amdsmn_vendorid = CPU_VENDOR_AMD,
		108	.amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M10H_ROOT,
		109	.amdsmn_addr_reg = F17H_SMN_ADDR_REG,
		110	.amdsmn_data_reg = F17H_SMN_DATA_REG,
		111	},
105	{	112	{
106	.amdsmn_vendorid = CPU_VENDOR_AMD,	113	.amdsmn_vendorid = CPU_VENDOR_AMD,
107	.amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT,	114	.amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT,

Lines 69-75 typedef enum { Link Here

(-)b/sys/dev/amdtemp/amdtemp.c (-1 / +13 lines)
69	CCD6,	69	CCD6,
70	CCD7,	70	CCD7,
71	CCD8,	71	CCD8,
72	CCD_MAX = CCD8,	72	CCD9,
		73	CCD10,
		74	CCD11,
		75	CCD12,
		76	CCD_MAX = CCD12,
73	NUM_CCDS = CCD_MAX - CCD_BASE + 1,	77	NUM_CCDS = CCD_MAX - CCD_BASE + 1,
74	} amdsensor_t;	78	} amdsensor_t;
75		79
Lines 109-114 struct amdtemp_softc { Link Here
109	#define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0	113	#define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0
110	#define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */	114	#define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
111	#define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630	115	#define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630
		116	#define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14b0
112	#define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8	117	#define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8
113		118
114	static const struct amdtemp_product {	119	static const struct amdtemp_product {
Lines 134-139 static const struct amdtemp_product { Link Here
134	{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },	139	{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
135	{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },	140	{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
136	{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },	141	{ VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },
		142	{ VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false },
137	{ VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false },	143	{ VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false },
138	};	144	};
139		145
Lines 180-185 static const struct amdtemp_product { Link Here
180	#define AMDTEMP_17H_CCD_TMP_BASE 0x59954	186	#define AMDTEMP_17H_CCD_TMP_BASE 0x59954
181	#define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)	187	#define AMDTEMP_17H_CCD_TMP_VALID (1u << 11)
182		188
		189	#define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00
183	#define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08	190	#define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08
184		191
185	/*	192	/*
Lines 860-865 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) Link Here
860	maxreg = 8;	867	maxreg = 8;
861	_Static_assert((int)NUM_CCDS >= 8, "");	868	_Static_assert((int)NUM_CCDS >= 8, "");
862	break;	869	break;
		870	case 0x10 ... 0x1f:
		871	sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE;
		872	maxreg = 12;
		873	_Static_assert((int)NUM_CCDS >= 12, "");
		874	break;
863	case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */	875	case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */
864	sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE;	876	sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE;
865	maxreg = 8;	877	maxreg = 8;

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