Created attachment 161835 [details] untested patch proposed as solution +++ This bug was initially created as a clone of Bug #186811 +++ > I bought a Intel Nuc D34010WYK [0]. It has a QS77 Chipset with a Intel > Panther Point USB Controller (as far as I can say). > or even a simple usb 3 memory stick, it was always connected at highspeed > (usb2) instead of superspeed (usb3) I bought another Intel NUC for building another FreeBSD based NAS. And the same procedure again. HW: Intel NUC Barebone NUC5I3RYH with Intel i3-5010U Processor with integrated PHB-LB chipset Reference: https://en.wikipedia.org/wiki/Broadwell_%28microarchitecture%29#Design -> Broadwell-U See also the mail from Karl Pielorz on freebsd-usb on the Sep 10 this year, he has the same problem. Philipp note to the attached patch: As the PHB is integrated into the cpu, I could'nt figure out which chipset name would match - please adapt the patch accordingly. The patch is untested yet, but I hope to be able to test it in the next few days. Output of pciconf: # pciconf -lvc hostb0@pci0:0:0:0: class=0x060000 card=0x20578086 chip=0x16048086 rev=0x09 hdr=0x00 vendor = 'Intel Corporation' class = bridge subclass = HOST-PCI cap 09[e0] = vendor (length 12) Intel cap 0 version 1 vgapci0@pci0:0:2:0: class=0x030000 card=0x20578086 chip=0x16168086 rev=0x09 hdr=0x00 vendor = 'Intel Corporation' class = display subclass = VGA cap 05[90] = MSI supports 1 message cap 01[d0] = powerspec 2 supports D0 D3 current D0 cap 13[a4] = PCI Advanced Features: FLR TP hdac0@pci0:0:3:0: class=0x040300 card=0x20578086 chip=0x160c8086 rev=0x09 hdr=0x00 vendor = 'Intel Corporation' class = multimedia subclass = HDA cap 01[50] = powerspec 2 supports D0 D3 current D0 cap 05[60] = MSI supports 1 message enabled with 1 message cap 10[70] = PCI-Express 1 root endpoint max data 128(128) FLR link x0(x0) xhci0@pci0:0:20:0: class=0x0c0330 card=0x20578086 chip=0x9cb18086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = serial bus subclass = USB cap 01[70] = powerspec 2 supports D0 D3 current D0 cap 05[80] = MSI supports 8 messages, 64 bit enabled with 1 message none0@pci0:0:22:0: class=0x078000 card=0x20578086 chip=0x9cba8086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = simple comms cap 01[50] = powerspec 3 supports D0 D3 current D0 cap 05[8c] = MSI supports 1 message, 64 bit em0@pci0:0:25:0: class=0x020000 card=0x20578086 chip=0x15a38086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = network subclass = ethernet cap 01[c8] = powerspec 2 supports D0 D3 current D0 cap 05[d0] = MSI supports 1 message, 64 bit enabled with 1 message cap 13[e0] = PCI Advanced Features: FLR TP hdac1@pci0:0:27:0: class=0x040300 card=0x20578086 chip=0x9ca08086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = multimedia subclass = HDA cap 01[50] = powerspec 3 supports D0 D3 current D0 cap 05[60] = MSI supports 1 message, 64 bit enabled with 1 message pcib1@pci0:0:28:0: class=0x060400 card=0x20578086 chip=0x9c908086 rev=0xe3 hdr=0x01 vendor = 'Intel Corporation' class = bridge subclass = PCI-PCI cap 10[40] = PCI-Express 2 root port max data 128(128) link x0(x1) speed 0.0(5.0) ASPM L0s/L1(L0s/L1) cap 05[80] = MSI supports 1 message cap 0d[90] = PCI Bridge card=0x20578086 cap 01[a0] = powerspec 3 supports D0 D3 current D0 pcib2@pci0:0:28:3: class=0x060400 card=0x20578086 chip=0x9c968086 rev=0xe3 hdr=0x01 vendor = 'Intel Corporation' class = bridge subclass = PCI-PCI cap 10[40] = PCI-Express 2 root port slot max data 128(128) link x1(x1) speed 2.5(5.0) ASPM L1(L0s/L1) cap 05[80] = MSI supports 1 message cap 0d[90] = PCI Bridge card=0x20578086 cap 01[a0] = powerspec 3 supports D0 D3 current D0 ecap 0000[100] = unknown 0 ecap 001e[200] = unknown 1 ehci0@pci0:0:29:0: class=0x0c0320 card=0x20578086 chip=0x9ca68086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = serial bus subclass = USB cap 01[50] = powerspec 3 supports D0 D3 current D0 cap 0a[58] = EHCI Debug Port at offset 0xa0 in map 0x14 cap 13[98] = PCI Advanced Features: FLR TP isab0@pci0:0:31:0: class=0x060100 card=0x20578086 chip=0x9cc38086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = bridge subclass = PCI-ISA cap 09[e0] = vendor (length 12) Intel cap 1 version 0 features: AMT, 4 PCI-e x1 slots none1@pci0:0:31:3: class=0x0c0500 card=0x20578086 chip=0x9ca28086 rev=0x03 hdr=0x00 vendor = 'Intel Corporation' class = serial bus subclass = SMBus none2@pci0:2:0:0: class=0x028000 card=0x90108086 chip=0x095a8086 rev=0x59 hdr=0x00 vendor = 'Intel Corporation' class = network cap 01[c8] = powerspec 3 supports D0 D3 current D0 cap 05[d0] = MSI supports 1 message, 64 bit cap 10[40] = PCI-Express 2 endpoint max data 128(128) FLR link x1(x1) speed 2.5(2.5) ASPM L1(L1) ecap 0001[100] = AER 1 0 fatal 0 non-fatal 0 corrected ecap 0003[140] = Serial 1 3413e8ffff3e8230 ecap 0018[14c] = LTR 1 ecap 001e[154] = unknown 1
probably affects all freebsd versions.
Created attachment 161840 [details] broadwell nuc patch for freebsd 10.2 the original patch submitted is for head
Which of the two patches attached is the correct one? --HPS
Created attachment 161898 [details] 20151011_FB10.2_xhci_broadwall_rerouting.patch The other patches contained the wrong pci ids (the ehci instead of the xhci). This patch is for 10.2 release. However, boot from my Samsung 4TB usb external haddisks is still not possible; so I'm not sure, if the patch is not working like the old one was, or if there is another or additional problem: * with this broadwell chipset * those harddisks * or just the usb3 boot Sorry about the other wrong patches. Cheers, Philipp
I was able to test the patch now. It successfully makes the usb 3 drives accessible: # usbconfig ugen1.1: <EHCI root HUB Intel> at usbus1, cfg=0 md=HOST spd=HIGH (480Mbps) pwr=SAVE (0mA) ugen0.1: <XHCI root HUB 0x8086> at usbus0, cfg=0 md=HOST spd=SUPER (5.0Gbps) pwr=SAVE (0mA) ugen1.2: <product 0x8001 vendor 0x8087> at usbus1, cfg=0 md=HOST spd=HIGH (480Mbps) pwr=SAVE (0mA) ugen0.2: <product 0x0011 vendor 0x046a> at usbus0, cfg=0 md=HOST spd=LOW (1.5Mbps) pwr=ON (100mA) ugen0.3: <M3 Portable Samsung> at usbus0, cfg=0 md=HOST spd=SUPER (5.0Gbps) pwr=ON (36mA) ugen0.4: <M3 Portable Samsung> at usbus0, cfg=0 md=HOST spd=SUPER (5.0Gbps) pwr=ON (36mA) Can you please submit the patch? Should I also send in the patch for head or do you adapt it by yourself? (it's only a small difference) I will open another bug regarding the usb boot issue.
Hi, You don't need a patch for -head. I'll process the patch this week. Remind me if I forget. Thank you! --HPS
A commit references this bug: Author: hselasky Date: Mon Oct 19 07:21:58 UTC 2015 New revision: 289560 URL: https://svnweb.freebsd.org/changeset/base/289560 Log: Add quirk for USB 3.0 PCI device. Submitted by: philipp.maechler@mamo.li PR: 203650 MFC after: 1 week Changes: head/sys/dev/usb/controller/xhci_pci.c
A commit references this bug: Author: hselasky Date: Tue Nov 3 10:24:54 UTC 2015 New revision: 290331 URL: https://svnweb.freebsd.org/changeset/base/290331 Log: MFC r285914, r289029 and r289560: - Move the remainder of host controller capability registers reading from xhci_start_controller() to xhci_init(). These values don't change at run- time so there's no point of acquiring them on every USB_HW_POWER_RESUME instead of only once during initialization. In r276717, reading the first couple of registers in question already had been moved as a prerequisite for the changes in that revision. - Identify ASMedia ASM1042A controllers. - Use NULL instead of 0 for pointers. - Add quirks for USB 3.0 PCI devices. PR: 203650 Changes: _U stable/10/ stable/10/sys/dev/usb/controller/xhci.c stable/10/sys/dev/usb/controller/xhci_pci.c
A commit references this bug: Author: hselasky Date: Tue Nov 3 10:32:28 UTC 2015 New revision: 290333 URL: https://svnweb.freebsd.org/changeset/base/290333 Log: MFC r285914, r289029, r289030 and r289560: - Move the remainder of host controller capability registers reading from xhci_start_controller() to xhci_init(). These values don't change at run- time so there's no point of acquiring them on every USB_HW_POWER_RESUME instead of only once during initialization. In r276717, reading the first couple of registers in question already had been moved as a prerequisite for the changes in that revision. - Identify ASMedia ASM1042A controllers. - Use NULL instead of 0 for pointers. - Add quirks for USB 3.0 PCI devices. PR: 203650 Changes: _U stable/9/sys/ _U stable/9/sys/dev/ stable/9/sys/dev/usb/controller/xhci.c stable/9/sys/dev/usb/controller/xhci_pci.c