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Lines 112-117
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| 112 |
static void pci_resume_msi(device_t dev); |
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static void pci_resume_msi(device_t dev); |
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static void pci_resume_msix(device_t dev); |
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static void pci_resume_msix(device_t dev); |
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static void pci_fix_asus_smbus(device_t dev); |
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static device_method_t pci_methods[] = { |
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static device_method_t pci_methods[] = { |
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/* Device interface */ |
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/* Device interface */ |
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DEVMETHOD(device_probe, pci_probe), |
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DEVMETHOD(device_probe, pci_probe), |
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Lines 179-194
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int type; |
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int type; |
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#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ |
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#define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */ |
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#define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */ |
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#define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */ |
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#define PCI_QUIRK_FIXUP_ROUTINE 4 /* PCI needs a fix to continue */ |
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int arg1; |
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int arg1; |
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int arg2; |
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int arg2; |
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void (*fixup_func)(device_t dev); |
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}; |
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}; |
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struct pci_quirk pci_quirks[] = { |
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struct pci_quirk pci_quirks[] = { |
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/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ |
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/* The Intel 82371AB and 82443MX has a map register at offset 0x90. */ |
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{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 }, |
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{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL }, |
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{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 }, |
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{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL }, |
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/* As does the Serverworks OSB4 (the SMBus mapping register) */ |
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/* As does the Serverworks OSB4 (the SMBus mapping register) */ |
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{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 }, |
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{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0, NULL }, |
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/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */ |
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{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus }, |
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{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus }, |
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/* |
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/* |
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* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge |
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* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge |
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Lines 395-400
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| 395 |
cfg->hdrtype = 1; |
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cfg->hdrtype = 1; |
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} |
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} |
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/* asus p4b/p4pe hack */ |
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static void |
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pci_fix_asus_smbus(device_t dev) |
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{ |
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int pmccfg; |
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/* read subsystem vendor-id */ |
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pmccfg = pci_read_config(dev, 0xF2, 2); |
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printf(" [-] pmccfg: %.4x\n",pmccfg); |
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if( pmccfg & 0x8 ){ |
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pmccfg &= ~0x8; |
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pci_write_config(dev, 0xF2, pmccfg, 2); |
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pmccfg = pci_read_config(dev, 0xF2, 2); |
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if( pmccfg & 0x8 ) |
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printf("Could not enable Intel 801SMBus!\n"); |
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else |
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printf("Enabled Intel 801SMBus\n"); |
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} |
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} |
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/* extract header type specific config data */ |
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/* extract header type specific config data */ |
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static void |
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static void |
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Lines 2555-2564
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* Add additional, quirked resources. |
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* Add additional, quirked resources. |
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*/ |
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*/ |
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for (q = &pci_quirks[0]; q->devid; q++) { |
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for (q = &pci_quirks[0]; q->devid; q++) { |
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if (q->devid == ((cfg->device << 16) | cfg->vendor) |
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if (q->devid == ((cfg->device << 16) | cfg->vendor) ){ |
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&& q->type == PCI_QUIRK_MAP_REG) |
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if( q->type == PCI_QUIRK_MAP_REG ) |
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pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, |
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pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl, force, 0); |
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force, 0); |
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else if( q->type == PCI_QUIRK_FIXUP_ROUTINE ) |
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q->fixup_func(dev); |
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} |
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} |
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} |
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if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { |
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if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) { |