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(-)cad/iverilog/Makefile (-1 / +3 lines)
Lines 7-13 Link Here
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#
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#
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PORTNAME=	iverilog
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PORTNAME=	iverilog
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PORTVERSION=	0.9.4
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PORTVERSION=	0.9.5
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CATEGORIES=	cad
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CATEGORIES=	cad
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MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
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MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
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		ftp://ftp.geda.seul.org/pub/geda/dist/
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		ftp://ftp.geda.seul.org/pub/geda/dist/
Lines 16-21 Link Here
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MAINTAINER=	niclas.zeising@gmail.com
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MAINTAINER=	niclas.zeising@gmail.com
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COMMENT=	A Verilog simulation and synthesis tool
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COMMENT=	A Verilog simulation and synthesis tool
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LICENSE=	GPLv2
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GNU_CONFIGURE=	yes
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GNU_CONFIGURE=	yes
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USE_BISON=	build
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USE_BISON=	build
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USE_GMAKE=	yes
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USE_GMAKE=	yes
(-)cad/iverilog/distinfo (-2 / +2 lines)
Lines 1-2 Link Here
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SHA256 (verilog-0.9.4.tar.gz) = b4eac7276975cf2d7c2c94246f733dc187feb4d5944034d053c5094279511eb1
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SHA256 (verilog-0.9.5.tar.gz) = c522b8b873f0cf77003db15c3df0f4a15b738ce4b060d1ca387c88e1b2be185d
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SIZE (verilog-0.9.4.tar.gz) = 1200614
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SIZE (verilog-0.9.5.tar.gz) = 1212112
(-)cad/iverilog/pkg-descr (-1 / +1 lines)
Lines 12-15 Link Here
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year 2000. This is a fairly large and complex standard, so it will
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year 2000. This is a fairly large and complex standard, so it will
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take some time for it to get there, but that's the goal. 
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take some time for it to get there, but that's the goal. 
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WWW: http://www.icarus.com/eda/verilog/
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WWW: http://iverilog.icarus.com/

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