Attachment #144548 for bug #139743




			    uint16_t data);
static void		pci_enable_msix(device_t dev, u_int index,
			    uint64_t address, uint32_t data);
static void		pci_fix_asus_smbus(device_t dev);
static void		pci_mask_msix(device_t dev, u_int index);
static void		pci_unmask_msix(device_t dev, u_int index);
static int		pci_msi_blacklisted(void);

#define	PCI_QUIRK_ENABLE_MSI_VM	3 /* Older chipset in VM where MSI works */
#define	PCI_QUIRK_UNMAP_REG	4 /* Ignore PCI map register */
#define	PCI_QUIRK_DISABLE_MSIX	5 /* MSI-X doesn't work */
#define	PCI_QUIRK_FIXUP_ROUTINE	6 /* PCI needs a fix to continue */
	int	arg1;
	int	arg2;
	void (*fixup_func)(device_t dev);
};

static const struct pci_quirk pci_quirks[] = {
	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },
	/* As does the Serverworks OSB4 (the SMBus mapping register) */
	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0, NULL },

	/*
	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
	 * or the CMIC-SL (AKA ServerWorks GC_LE).
	 */
	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work on earlier Intel chipsets including
	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
	 */
	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },
	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
	 * bridge.
	 */
	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0, NULL },

	/*
	 * MSI-X allocation doesn't work properly for devices passed through
	 * by VMware up to at least ESXi 5.1.
	 */
	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCI/PCI-X */
	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX,	0,	0, NULL }, /* PCIe */

	/*
	 * Some virtualization environments emulate an older chipset
	 * but support MSI just fine.  QEMU uses the Intel 82440.
	 */
	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0, NULL },

	/*
	 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus

	 * For SB600 A21 and later, firmware must set the bit to hide it.
	 * For SB700 and later, it is unused and hardcoded to zero.
	 */
	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0, NULL },

	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },
	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE,	0,	0, &pci_fix_asus_smbus },

	{ 0 }
};

		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
}

/* asus p4b/p4pe hack */

static void
pci_fix_asus_smbus(device_t dev)
{
	int	pmccfg;

	/* read subsystem vendor-id */
	pmccfg = pci_read_config(dev, 0xF2, 2);
	printf(" [-] pmccfg: %.4x\n",pmccfg);
	if( pmccfg & 0x8 ){
		pmccfg &= ~0x8;
		pci_write_config(dev, 0xF2, pmccfg, 2);
		pmccfg = pci_read_config(dev, 0xF2, 2);
		if( pmccfg & 0x8 )
			printf("Could not enable Intel 801SMBus!\n");
		else
			printf("Enabled Intel 801SMBus\n");
	}
}

/* extract header type specific config data */

static void

			 * Skip quirked resources.
			 */
			for (q = &pci_quirks[0]; q->devid != 0; q++)
				if (q->devid == ((cfg->device << 16) | cfg->vendor) ){
				    if( q->type == PCI_QUIRK_MAP_REG )
					pci_add_map(bus, dev, q->arg1, rl, force, 0);
				    else if( q->type == PCI_QUIRK_FIXUP_ROUTINE )
					q->fixup_func(dev);
				}
				if (q->devid == devid &&
				    q->type == PCI_QUIRK_UNMAP_REG &&
				    q->arg1 == PCIR_BAR(i))

Return to bug 139743

Lines 112-117 Link Here

(-)sys/dev/pci/pci.c (-17 / +51 lines)
112	uint16_t data);	112	uint16_t data);
113	static void pci_enable_msix(device_t dev, u_int index,	113	static void pci_enable_msix(device_t dev, u_int index,
114	uint64_t address, uint32_t data);	114	uint64_t address, uint32_t data);
		115	static void pci_fix_asus_smbus(device_t dev);
115	static void pci_mask_msix(device_t dev, u_int index);	116	static void pci_mask_msix(device_t dev, u_int index);
116	static void pci_unmask_msix(device_t dev, u_int index);	117	static void pci_unmask_msix(device_t dev, u_int index);
117	static int pci_msi_blacklisted(void);	118	static int pci_msi_blacklisted(void);
Lines 196-249 Link Here
196	#define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */	197	#define PCI_QUIRK_ENABLE_MSI_VM 3 /* Older chipset in VM where MSI works */
197	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */	198	#define PCI_QUIRK_UNMAP_REG 4 /* Ignore PCI map register */
198	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */	199	#define PCI_QUIRK_DISABLE_MSIX 5 /* MSI-X doesn't work */
		200	#define PCI_QUIRK_FIXUP_ROUTINE 6 /* PCI needs a fix to continue */
199	int arg1;	201	int arg1;
200	int arg2;	202	int arg2;
		203	void (*fixup_func)(device_t dev);
201	};	204	};
202		205
203	static const struct pci_quirk pci_quirks[] = {	206	static const struct pci_quirk pci_quirks[] = {
204	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */	207	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
205	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },	208	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
206	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },	209	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
207	/* As does the Serverworks OSB4 (the SMBus mapping register) */	210	/* As does the Serverworks OSB4 (the SMBus mapping register) */
208	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },	211	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
209		212
210	/*	213	/*
211	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge	214	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
212	* or the CMIC-SL (AKA ServerWorks GC_LE).	215	* or the CMIC-SL (AKA ServerWorks GC_LE).
213	*/	216	*/
214	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	217	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
215	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	218	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
216		219
217	/*	220	/*
218	* MSI doesn't work on earlier Intel chipsets including	221	* MSI doesn't work on earlier Intel chipsets including
219	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.	222	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
220	*/	223	*/
221	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	224	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
222	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	225	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
223	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	226	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
224	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	227	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
225	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	228	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
226	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	229	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
227	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	230	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
228		231
229	/*	232	/*
230	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX	233	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX
231	* bridge.	234	* bridge.
232	*/	235	*/
233	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },	236	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
234		237
235	/*	238	/*
236	* MSI-X allocation doesn't work properly for devices passed through	239	* MSI-X allocation doesn't work properly for devices passed through
237	* by VMware up to at least ESXi 5.1.	240	* by VMware up to at least ESXi 5.1.
238	*/	241	*/
239	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCI/PCI-X */	242	{ 0x079015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCI/PCI-X */
240	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0 }, /* PCIe */	243	{ 0x07a015ad, PCI_QUIRK_DISABLE_MSIX, 0, 0, NULL }, /* PCIe */
241		244
242	/*	245	/*
243	* Some virtualization environments emulate an older chipset	246	* Some virtualization environments emulate an older chipset
244	* but support MSI just fine. QEMU uses the Intel 82440.	247	* but support MSI just fine. QEMU uses the Intel 82440.
245	*/	248	*/
246	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },	249	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0, NULL },
247		250
248	/*	251	/*
249	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus	252	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
Lines 253-259 Link Here
253	* For SB600 A21 and later, firmware must set the bit to hide it.	256	* For SB600 A21 and later, firmware must set the bit to hide it.
254	* For SB700 and later, it is unused and hardcoded to zero.	257	* For SB700 and later, it is unused and hardcoded to zero.
255	*/	258	*/
256	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },	259	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0, NULL },
		260
		261	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
		262	{ 0x24408086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
		263	{ 0x24C08086, PCI_QUIRK_FIXUP_ROUTINE, 0, 0, &pci_fix_asus_smbus },
257		264
258	{ 0 }	265	{ 0 }
259	};	266	};
Lines 527-532 Link Here
527	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;	534	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
528	}	535	}
529		536
		537	/* asus p4b/p4pe hack */
		538
		539	static void
		540	pci_fix_asus_smbus(device_t dev)
		541	{
		542	int pmccfg;
		543
		544	/* read subsystem vendor-id */
		545	pmccfg = pci_read_config(dev, 0xF2, 2);
		546	printf(" [-] pmccfg: %.4x\n",pmccfg);
		547	if( pmccfg & 0x8 ){
		548	pmccfg &= ~0x8;
		549	pci_write_config(dev, 0xF2, pmccfg, 2);
		550	pmccfg = pci_read_config(dev, 0xF2, 2);
		551	if( pmccfg & 0x8 )
		552	printf("Could not enable Intel 801SMBus!\n");
		553	else
		554	printf("Enabled Intel 801SMBus\n");
		555	}
		556	}
		557
530	/* extract header type specific config data */	558	/* extract header type specific config data */
531		559
532	static void	560	static void
Lines 3206-3211 Link Here
3206	* Skip quirked resources.	3234	* Skip quirked resources.
3207	*/	3235	*/
3208	for (q = &pci_quirks[0]; q->devid != 0; q++)	3236	for (q = &pci_quirks[0]; q->devid != 0; q++)
		3237	if (q->devid == ((cfg->device << 16) \| cfg->vendor) ){
		3238	if( q->type == PCI_QUIRK_MAP_REG )
		3239	pci_add_map(bus, dev, q->arg1, rl, force, 0);
		3240	else if( q->type == PCI_QUIRK_FIXUP_ROUTINE )
		3241	q->fixup_func(dev);
		3242	}
3209	if (q->devid == devid &&	3243	if (q->devid == devid &&
3210	q->type == PCI_QUIRK_UNMAP_REG &&	3244	q->type == PCI_QUIRK_UNMAP_REG &&
3211	q->arg1 == PCIR_BAR(i))	3245	q->arg1 == PCIR_BAR(i))