Attachment #150704 for bug #196081




#include <sys/watchdog.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/frame.h>
#include <machine/intr.h>

#include <dev/fdt/fdt_common.h>

static int
a10_ccm_probe(device_t dev)
{
	int result = ENXIO;
	if (!ofw_bus_status_okay(dev))
		return (ENXIO);

	if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) {
		device_set_desc(dev, "Allwinner Clock Control Module");
		result = BUS_PROBE_DEFAULT;
	}

	return (result);
}

static int

	struct a10_ccm_softc *sc = device_get_softc(dev);
	int rid = 0;

	if (a10_ccm_sc) {
		return (ENXIO);
	}

	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
	if (!sc->res) {


	a10_ccm_sc = sc;

    ccm_write_4(sc, CCM_PLL6_CFG, CCM_PLL6_DEFAULT_CONFIG);

	return (0);
}


	struct a10_ccm_softc *sc = a10_ccm_sc;
	uint32_t reg_value;

	if (sc == NULL) {
		return (ENXIO);
	}

	/* Gating AHB clock for USB */
	reg_value = ccm_read_4(sc, CCM_AHB_GATING0);

	struct a10_ccm_softc *sc = a10_ccm_sc;
	uint32_t reg_value;

	if (sc == NULL) {
		return (ENXIO);
	}

	/* Disable clock for USB */
	reg_value = ccm_read_4(sc, CCM_USB_CLK);

}

int
a10_clk_mmc_activate(uint32_t *mod_clk)
{
	struct a10_ccm_softc *sc = a10_ccm_sc;
	uint32_t reg_value;
	uint32_t pll6_clk;
	uint32_t divider;
	uint32_t n, k;

	if (sc == NULL) {
		return (ENXIO);
	}

	/* Gating AHB clock for SDMMC0 */
	reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
	reg_value |= CCM_AHB_GATING_SDMMC0 | CCM_AHB_GATING_DMA;
	ccm_write_4(sc, CCM_AHB_GATING0, reg_value);

	/* Config mod clock */
	reg_value = ccm_read_4(sc, CCM_PLL6_CFG);
	n = (reg_value >> 8) & 0x1f;
	k = ((reg_value >> 4) & 3) + 1;
	pll6_clk = 24000000 * n * k / 2;

	divider = ((pll6_clk + 99999999) / 100000000) - 1;

	ccm_write_4(sc, CCM_MMC0_SCLK_CFG,
			CCM_MMC0_GATE_PASS | CCM_MMC0_CLK_SRC_PLL6 | divider);

	*mod_clk = pll6_clk / (divider + 1);

	return (0);
}

int
a10_clk_emac_activate(void) {
	struct a10_ccm_softc *sc = a10_ccm_sc;
	uint32_t reg_value;


	return (0);
}


Lines 103-117 Link Here

(-)b/sys/arm/allwinner/a10_clk.h (-1 / +11 lines)
103	#define CCM_AHB_GATING_USB0 (1 << 0)	103	#define CCM_AHB_GATING_USB0 (1 << 0)
104	#define CCM_AHB_GATING_EHCI0 (1 << 1)	104	#define CCM_AHB_GATING_EHCI0 (1 << 1)
105	#define CCM_AHB_GATING_EHCI1 (1 << 3)	105	#define CCM_AHB_GATING_EHCI1 (1 << 3)
106	#define CCM_AHB_GATING_EMAC (1 << 17)	106	#define CCM_AHB_GATING_EMAC (1 << 17)
		107	#define CCM_AHB_GATING_DMA (1 << 6)
		108	#define CCM_AHB_GATING_SDMMC0 (1 << 8)
107		109
108	#define CCM_USB_PHY (1 << 8)	110	#define CCM_USB_PHY (1 << 8)
109	#define CCM_USB0_RESET (1 << 0)	111	#define CCM_USB0_RESET (1 << 0)
110	#define CCM_USB1_RESET (1 << 1)	112	#define CCM_USB1_RESET (1 << 1)
111	#define CCM_USB2_RESET (1 << 2)	113	#define CCM_USB2_RESET (1 << 2)
112		114
		115	#define CCM_MMC0_CLK_SRC_PLL5 (2U << 24)
		116	#define CCM_MMC0_CLK_SRC_PLL6 (0x1 << 24)
		117	#define CCM_MMC0_GATE_MASK (0 << 31)
		118	#define CCM_MMC0_GATE_PASS (1 << 31)
		119
		120	#define CCM_PLL6_DEFAULT_CONFIG 0xa1009911
		121
113	int a10_clk_usb_activate(void);	122	int a10_clk_usb_activate(void);
114	int a10_clk_usb_deactivate(void);	123	int a10_clk_usb_deactivate(void);
115	int a10_clk_emac_activate(void);	124	int a10_clk_emac_activate(void);
		125	int a10_clk_mmc_activate(uint32_t *mod_clk);
116		126
117	#endif /* _A10_CLK_H_ */	127	#endif /* _A10_CLK_H_ */




/*-
 * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
 * All rights reserved.
 *
 * Copyright (c) 2013-2014:
 * Computer Architecture Laboratory, National University of Cordoba. Cordoba, Argentina.
 * Nicolas Vidable <njvidable@gmail.com>
 * Martin Galvan <omgalvan.86@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 *
 * MMC/SD Host Controller driver for the Allwinner A10 SoC.
 */

#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");

#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bio.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/endian.h>
#include <sys/kernel.h>
#include <sys/kthread.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/queue.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/time.h>
#include <sys/timetc.h>
#include <sys/watchdog.h>

#include <sys/kdb.h>

#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/resource.h>
#include <machine/frame.h>
#include <machine/intr.h>

#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>

#include <dev/mmc/bridge.h>
#include <dev/mmc/mmcreg.h>
#include <dev/mmc/mmcbrvar.h>

#include <arm/allwinner/a10_clk.h>
#include <arm/allwinner/a10_mmc.h>

struct a10_mmc_softc {
    device_t             device;
    struct mtx           mutex;
    struct mmc_host      mmc_host;
    struct mmc_request * mmc_request;
    struct resource *    memory_resource;
    struct resource *    interrupt_resource;
    void *               interrupt_handler;
    uint32_t             read_interrupts;  /* Interrupts we've read so far. */
    uint32_t             mod_clock;
    int                  bus_busy;
};

static int a10_mmc_probe(device_t);
static int a10_mmc_attach(device_t);
static int a10_mmc_detach(device_t);
static void a10_mmc_release_resources(struct a10_mmc_softc *);
static int a10_mmc_reset_controller(struct a10_mmc_softc *);
static void a10_mmc_clear_interrupts(struct a10_mmc_softc *);
static void a10_mmc_enable_interrupts(struct a10_mmc_softc *);
static void a10_mmc_interrupt_handler(void *);
static void a10_mmc_request_ok(struct a10_mmc_softc *);
static void a10_mmc_request_error(struct a10_mmc_softc *);
static void a10_mmc_finalize_request(struct a10_mmc_softc *);
static void a10_mmc_send_manual_stop(struct a10_mmc_softc *, struct mmc_request *);
static void a10_mmc_set_bus_width(struct a10_mmc_softc *, struct mmc_ios *);
static int a10_mmc_update_ios(device_t, device_t);
static int a10_mmc_update_clock(struct a10_mmc_softc *);
static int a10_mmc_set_clock_enabled(struct a10_mmc_softc *, int);
static int a10_mmc_set_clock_rate(struct a10_mmc_softc *, struct mmc_ios *);
static int a10_mmc_request(device_t, device_t, struct mmc_request *);
static int a10_mmc_get_ro(device_t, device_t);
static int a10_mmc_acquire_host(device_t, device_t);
static int a10_mmc_release_host(device_t, device_t);
static int a10_mmc_do_programmed_io(struct a10_mmc_softc *, struct mmc_data *);
static int a10_mmc_timeout_without_command_done(struct a10_mmc_softc *);
static int a10_mmc_interrupt_error(struct a10_mmc_softc *);
static int a10_mmc_interrupt_done(uint32_t, struct mmc_data *);
static int a10_mmc_fifo_wait(struct a10_mmc_softc *, uint32_t, uint32_t);

static inline void
a10_mmc_lock(struct a10_mmc_softc *sc)
{
    mtx_lock(&sc->mutex);
}

static inline void
a10_mmc_unlock(struct a10_mmc_softc *sc)
{
    mtx_unlock(&sc->mutex);
}

static inline uint32_t
a10_mmc_read_4(struct a10_mmc_softc *sc, bus_size_t offset)
{
	return (bus_read_4(sc->memory_resource, offset));
}

static inline void
a10_mmc_write_4(struct a10_mmc_softc *sc, bus_size_t offset, uint32_t value)
{
	bus_write_4(sc->memory_resource, offset, value);
}

static int
a10_mmc_probe(device_t device)
{
    int result = ENXIO;

    if (ofw_bus_is_compatible(device, "allwinner,sun4i-mmc")) {
        device_set_desc(device, "Allwinner Integrated MMC/SD controller");
        result = BUS_PROBE_DEFAULT;
    }

    return (result);
}

static int
a10_mmc_attach(device_t device)
{
    struct a10_mmc_softc *sc;
    device_t child;
    int resource_id;
    int error;

    sc = device_get_softc(device);
    sc->device = device;
    sc->mmc_request = NULL;  /* Set the current request to NULL. */

    mtx_init(&sc->mutex, device_get_nameunit(sc->device), "a10_mmc", MTX_DEF);

    /* Allocate a memory window resource. */
    resource_id = 0;
    sc->memory_resource = bus_alloc_resource_any(device, SYS_RES_MEMORY,
                                                 &resource_id, RF_ACTIVE);

    if (sc->memory_resource == NULL) {
        device_printf(device, "Cannot allocate memory window!\n");

        return (ENXIO);
    }

    /* Allocate an interrupt resource. */
    resource_id = 0;
    sc->interrupt_resource = bus_alloc_resource_any(device, SYS_RES_IRQ, &resource_id,
                                                    RF_ACTIVE | RF_SHAREABLE);

    if (sc->interrupt_resource == NULL) {
        device_printf(device, "Cannot allocate interrupt resource!\n");
        a10_mmc_release_resources(sc);

        return (ENXIO);
    }

    /* Set the ithread interrupt handler for our interrupt resource. */
    error = bus_setup_intr(device, sc->interrupt_resource, INTR_TYPE_MISC |
                           INTR_MPSAFE, NULL, a10_mmc_interrupt_handler, sc,
                           &sc->interrupt_handler);

    if (error) {
        device_printf(device, "Cannot setup interrupt handler!\n");
        a10_mmc_release_resources(sc);

        return (ENXIO);
    }

    /* Activate the MMC clock. */
    error = a10_clk_mmc_activate(&sc->mod_clock);

    if (error) {
        device_printf(device, "Cannot activate clock!\n");
        a10_mmc_release_resources(sc);

        return (ENXIO);
    }

    /* Reset controller. */
    error = a10_mmc_reset_controller(sc);

    if (error) {
        a10_mmc_release_resources(sc);

        return (ENXIO);
    }

    /* Configure timeout register. */
    a10_mmc_write_4(sc, A10_MMC_TIMEOUT_REG, 0xFFFFFFFF);

    /* Clear interrupt flags. */
    a10_mmc_clear_interrupts(sc);

    /* Initialization black magic: there's no documentation on why these
     * values must be written here.
     */
    a10_mmc_write_4(sc, A10_MMC_DEBUG_ENABLE_REG, 0xDEB);
    a10_mmc_write_4(sc, A10_MMC_FUNCTION_SELECT_REG, A10_MMC_CE_ATA_ON);

    /* Set minimum and maximum operating frequencies (400kHz-50MHz). */
    sc->mmc_host.f_min = 400000;
    sc->mmc_host.f_max = 52000000;

    /* Set operation conditions (voltage). */
    sc->mmc_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;

    /* Set additional host controller capabilities. */
    sc->mmc_host.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_HSPEED;

    /* Set mode. */
    sc->mmc_host.mode = mode_sd;

    device_set_ivars(device, &sc->mmc_host);

    child = device_add_child(device, "mmc", 0);

    if (child == NULL) {
        device_printf(device, "Attaching MMC bus failed!\n");
        a10_mmc_release_resources(sc);

        return (ENXIO);
    }

    device_set_ivars(device, &sc->mmc_host);
    bus_generic_attach(device);

    return (0);
}

static int
a10_mmc_detach(device_t device)
{
    a10_mmc_release_resources(device_get_softc(device));

    return (EBUSY);
}

/* Releases allocated resources. */
static void
a10_mmc_release_resources(struct a10_mmc_softc *sc)
{
    if (sc->interrupt_handler != NULL) {
        bus_teardown_intr(sc->device, sc->interrupt_resource, sc->interrupt_handler);
        sc->interrupt_handler = NULL;
    }

    if (sc->memory_resource != NULL) {
        bus_release_resource(sc->device, SYS_RES_MEMORY, 0, sc->memory_resource);
        sc->memory_resource = NULL;
    }

    if (sc->interrupt_resource != NULL) {
        bus_release_resource(sc->device, SYS_RES_IRQ, 0, sc->interrupt_resource);
        sc->interrupt_resource = NULL;
    }
}

/* Writes the hardware reset bits to the global control register. */
static int
a10_mmc_reset_controller(struct a10_mmc_softc *sc)
{
    int error = 0;
    uint32_t time_left = 0xFFFF;
    uint32_t reg_value;

    reg_value = a10_mmc_read_4(sc, A10_MMC_GLOBAL_CONTROL_REG);
    reg_value |= A10_MMC_HARDWARE_RESET_BITS;

    a10_mmc_write_4(sc, A10_MMC_GLOBAL_CONTROL_REG, reg_value);

    /* Wait until the reset is done or a timeout occurs. */
    do {
        reg_value = a10_mmc_read_4(sc, A10_MMC_GLOBAL_CONTROL_REG);
    } while ((reg_value & A10_MMC_HARDWARE_RESET_BITS) && (--time_left));

    if (!time_left) {
        device_printf(sc->device, "Reset timeout!\n");
        error = EIO;
    }

    return (error);
}

/* Clear the interrupt status flags. */
static void
a10_mmc_clear_interrupts(struct a10_mmc_softc *sc)
{
    sc->read_interrupts = 0;
    a10_mmc_write_4(sc, A10_MMC_RAW_INTERRUPT_STATUS_REG, 0xFFFFFFFF);
    a10_mmc_write_4(sc, A10_MMC_INTERRUPT_MASK_REG, 0);
}

/* Enable interrupts. */
static void
a10_mmc_enable_interrupts(struct a10_mmc_softc *sc)
{
    uint32_t reg_value;

    reg_value = a10_mmc_read_4(sc, A10_MMC_GLOBAL_CONTROL_REG);
    reg_value |= A10_MMC_INTERRUPT_ENABLE;

    a10_mmc_write_4(sc, A10_MMC_GLOBAL_CONTROL_REG, reg_value);
}

/* Service an MMC request by sending its associated command to the card and
 * enabling the appropriate interrupts. */
static int
a10_mmc_request(device_t bus, device_t child, struct mmc_request *request)
{
    struct a10_mmc_softc *sc = device_get_softc(bus);
    struct mmc_command *command = request->cmd;
    uint32_t command_reg_value = A10_MMC_START;
    uint32_t interrupt_mask = A10_MMC_COMMAND_DONE | A10_MMC_INTERRUPT_ERROR_BITS;
    uint32_t block_size;
    int error = 0;

    a10_mmc_lock(sc);

    if (sc->mmc_request) {
        a10_mmc_unlock(sc);
        return (EBUSY);
    }

    sc->mmc_request = request;

    if (command->opcode == MMC_GO_IDLE_STATE) {
       command_reg_value |= A10_MMC_SEND_INIT_SEQUENCE;
    }

    if (command->flags & MMC_RSP_PRESENT) {
        command_reg_value |= A10_MMC_RESPONSE_EXPECTED;
    }

    if (command->flags & MMC_RSP_136) {
        command_reg_value |= A10_MMC_LONG_RESPONSE;
    }

    if (command->flags & MMC_RSP_CRC){
        command_reg_value |= A10_MMC_CHECK_RESPONSE_CRC;
    }

    if (command->flags & MMC_RSP_BUSY) {
        interrupt_mask |= A10_MMC_DATA_READ_TIMEOUT;
    }

    if (command->data != NULL) {
        command_reg_value |= A10_MMC_DATA_EXPECTED | A10_MMC_WAIT_PREVIOUS_DATA_OVER;

    	if (request->stop != NULL) {   /* Multiple block transfer. */
            command_reg_value |= A10_MMC_SEND_AUTO_STOP;
            interrupt_mask |= A10_MMC_AUTO_COMMAND_DONE;
    	} else {   /* Single-block transfer. */
            interrupt_mask |= A10_MMC_DATA_TRANSFER_OVER;
        }

        if (command->data->flags & MMC_DATA_WRITE) {
            command_reg_value |= A10_MMC_WRITE;
        } else {   /* MMC_DATA_READ */
            command_reg_value &= ~A10_MMC_WRITE;
        }

        block_size = min(command->data->len, 512);

        a10_mmc_write_4(sc, A10_MMC_BLOCK_SIZE_REG, block_size);
        a10_mmc_write_4(sc, A10_MMC_BYTE_COUNT_REG, command->data->len);

        /* Choose access by AHB. */
        a10_mmc_write_4(sc, A10_MMC_GLOBAL_CONTROL_REG,
                        a10_mmc_read_4(sc, A10_MMC_GLOBAL_CONTROL_REG) |
                        A10_MMC_ACCESS_BY_AHB);
    }

    a10_mmc_write_4(sc, A10_MMC_INTERRUPT_MASK_REG, interrupt_mask);
    a10_mmc_enable_interrupts(sc);

    /* Send the command to the card. */
    a10_mmc_write_4(sc, A10_MMC_ARGUMENT_REG, command->arg);
    a10_mmc_write_4(sc, A10_MMC_COMMAND_REG, command_reg_value | command->opcode);

    if (command->data != NULL) {
	    error = a10_mmc_do_programmed_io(sc, command->data);
    }

    a10_mmc_unlock(sc);

    return (error);
}

/* Handle an IRQ by checking the interrupt status bits and the corresponding
 * request. */
static void
a10_mmc_interrupt_handler(void *arg)
{
    struct a10_mmc_softc *sc = (struct a10_mmc_softc *)arg;
    uint32_t masked_isr;

    a10_mmc_lock(sc);

    masked_isr = a10_mmc_read_4(sc, A10_MMC_MASKED_INTERRUPT_STATUS_REG);

    if (sc->mmc_request != NULL) {
        sc->read_interrupts |= masked_isr;

        /* After a RESPONSE_TIMEOUT, we must wait for a COMMAND_DONE.
         * Thus, if we've only read a RESPONSE_TIMEOUT from the ISR so far,
         * enable COMMAND_DONE interrupts now.
         */
        if (a10_mmc_timeout_without_command_done(sc)) {
            a10_mmc_write_4(sc, A10_MMC_INTERRUPT_MASK_REG, A10_MMC_COMMAND_DONE);
        } else if (a10_mmc_interrupt_error(sc)) {
            device_printf(sc->device, "IRQ error! Interrupts: 0x%08X\n", sc->read_interrupts);
            a10_mmc_request_error(sc);
        } else if (a10_mmc_interrupt_done(sc->read_interrupts, sc->mmc_request->cmd->data)) {
            a10_mmc_request_ok(sc);
        }
    } else {   /* NULL request */
        device_printf(sc->device, "NULL MMC Request; Masked ISR: 0x%08X\n", masked_isr);
    }

    /* Clear interrupts. */
    a10_mmc_write_4(sc, A10_MMC_RAW_INTERRUPT_STATUS_REG, masked_isr);

    a10_mmc_unlock(sc);
}

/* Sometimes we may get a RESPONSE_TIMEOUT interrupt without the COMMAND_DONE
 * bit set.
 */
static int
a10_mmc_timeout_without_command_done(struct a10_mmc_softc *sc) {
    return (sc->read_interrupts & A10_MMC_RESPONSE_TIMEOUT &&
            !(sc->read_interrupts & A10_MMC_COMMAND_DONE));
}

static int
a10_mmc_interrupt_error(struct a10_mmc_softc *sc) {
    return (sc->read_interrupts & A10_MMC_INTERRUPT_ERROR_BITS);
}

static int
a10_mmc_interrupt_done(uint32_t read_interrupts, struct mmc_data *command_data) {
    return ((read_interrupts & A10_MMC_COMMAND_DONE) ||
            ((command_data != NULL) && (read_interrupts & A10_MMC_DATA_TRANSFER_OVER)));
}

/* As we don't have DMA support yet, we have to do PIO for every transfer. */
static int
a10_mmc_do_programmed_io(struct a10_mmc_softc *sc, struct mmc_data *command_data)
{
    int i = 0;
    int error = 0;
    uint32_t *buffer = (uint32_t *)command_data->data;
    uint32_t data_length = command_data->len >> 2;

    if (command_data->flags & MMC_DATA_READ) {
        while (i < data_length && !error) {
            error = a10_mmc_fifo_wait(sc, 0xFFFFFFFF, A10_MMC_FIFO_EMPTY);

            if (!error) {
                buffer[i] = a10_mmc_read_4(sc, A10_MMC_FIFO_ACCESS_ADDRESS);
                ++i;
            }
        }
    } else {   /* MMC_DATA_WRITE */
        while (i < data_length && !error) {
            error = a10_mmc_fifo_wait(sc, 0xFFFFFFFF, A10_MMC_FIFO_FULL);

            if (!error) {
                a10_mmc_write_4(sc, A10_MMC_FIFO_ACCESS_ADDRESS, buffer[i]);
                ++i;
            }
        }
    }

    return (error);
}

/* Wait until the FIFO is ready. */
static int
a10_mmc_fifo_wait(struct a10_mmc_softc *sc, uint32_t time_left, uint32_t status_bits)
{
    int error = 0;
    uint32_t status_reg_value;

    do {
        status_reg_value = a10_mmc_read_4(sc, A10_MMC_STATUS_REG);
    } while ((status_reg_value & status_bits) && (--time_left));

    if (!time_left) {
        device_printf(sc->device, "Data transfer timeout!\n");
        error = EIO;
    }

    return (error);
}

/* We successfully completed a request. */
static void
a10_mmc_request_ok(struct a10_mmc_softc *sc)
{
    struct mmc_command *command = sc->mmc_request->cmd;
    uint32_t response_status;

    do {
        response_status = a10_mmc_read_4(sc, A10_MMC_STATUS_REG);
    } while (response_status & A10_MMC_CARD_DATA_BUSY);

    if (command->flags & MMC_RSP_136) {
        command->resp[0] = a10_mmc_read_4(sc, A10_MMC_RESPONSE_REG_3);
        command->resp[1] = a10_mmc_read_4(sc, A10_MMC_RESPONSE_REG_2);
        command->resp[2] = a10_mmc_read_4(sc, A10_MMC_RESPONSE_REG_1);
        command->resp[3] = a10_mmc_read_4(sc, A10_MMC_RESPONSE_REG_0);
    } else {
        command->resp[0] = a10_mmc_read_4(sc, A10_MMC_RESPONSE_REG_0);
    }

    command->error = MMC_ERR_NONE;

    a10_mmc_finalize_request(sc);
}

/* An error occurred when the current request was being serviced. */
static void
a10_mmc_request_error(struct a10_mmc_softc *sc)
{
    struct mmc_command *command = sc->mmc_request->cmd;

    device_printf(sc->device, "Error in request.\n");

    command->error = MMC_ERR_TIMEOUT;

    if (command->data != NULL) {
        device_printf(sc->device, "Data error, sending manual stop.\n");
        a10_mmc_send_manual_stop(sc, sc->mmc_request);
    }

    if (sc->mmc_request->stop != NULL) {
        sc->mmc_request->stop->error = MMC_ERR_TIMEOUT;
    }

    a10_mmc_finalize_request(sc);
}

/* Finish handling a request. */
static void
a10_mmc_finalize_request(struct a10_mmc_softc *sc)
{
    struct mmc_request *request = sc->mmc_request;

    a10_mmc_write_4(sc, A10_MMC_GLOBAL_CONTROL_REG,
                a10_mmc_read_4(sc, A10_MMC_GLOBAL_CONTROL_REG) |
                A10_MMC_FIFO_RESET);

    sc->mmc_request = NULL;
    request->done(request);
    a10_mmc_clear_interrupts(sc);
}

/* This host relies on manual stop commands being send on a data transfer error. */
static void
a10_mmc_send_manual_stop(struct a10_mmc_softc *sc, struct mmc_request *request)
{
    uint32_t response;
    uint32_t raw_isr;
    uint32_t command_reg_value = A10_MMC_START | A10_MMC_RESPONSE_EXPECTED |
                                 A10_MMC_STOP_ABORT_COMMAND | A10_MMC_CHECK_RESPONSE_CRC |
                                 MMC_STOP_TRANSMISSION;

    a10_mmc_clear_interrupts(sc);

    a10_mmc_write_4(sc, A10_MMC_ARGUMENT_REG, 0);
    a10_mmc_write_4(sc, A10_MMC_COMMAND_REG, command_reg_value);

    do {
        raw_isr = a10_mmc_read_4(sc, A10_MMC_RAW_INTERRUPT_STATUS_REG);
    } while (!(raw_isr &
               (A10_MMC_COMMAND_DONE | A10_MMC_INTERRUPT_ERROR_BITS)));

    if (!(raw_isr & A10_MMC_COMMAND_DONE) || (raw_isr & A10_MMC_INTERRUPT_ERROR_BITS)) {
        device_printf(sc->device, "Manual stop failed.\n");
        response = MMC_ERR_TIMEOUT;
    } else {
        response = a10_mmc_read_4(sc, A10_MMC_RESPONSE_REG_0);
    }

    if (request->stop != NULL) {
        request->stop->resp[0] = response;
    }
}

/* Return the current values of this device's instance variables. */
static int
a10_mmc_read_ivar(device_t bus, device_t child, int which,
                  uintptr_t *result)
{
    struct a10_mmc_softc *sc = device_get_softc(bus);
    int error = 0;

    switch (which) {
        case MMCBR_IVAR_BUS_MODE:
            *(int *)result = sc->mmc_host.ios.bus_mode;
            break;
        case MMCBR_IVAR_BUS_WIDTH:
            *(int *)result = sc->mmc_host.ios.bus_width;
            break;
        case MMCBR_IVAR_CHIP_SELECT:
            *(int *)result = sc->mmc_host.ios.chip_select;
            break;
        case MMCBR_IVAR_CLOCK:
            *(int *)result = sc->mmc_host.ios.clock;
            break;
        case MMCBR_IVAR_F_MIN:
            *(int *)result = sc->mmc_host.f_min;
            break;
        case MMCBR_IVAR_F_MAX:
            *(int *)result = sc->mmc_host.f_max;
            break;
        case MMCBR_IVAR_HOST_OCR:
            *(int *)result = sc->mmc_host.host_ocr;
            break;
        case MMCBR_IVAR_MODE:
            *(int *)result = sc->mmc_host.mode;
            break;
        case MMCBR_IVAR_OCR:
            *(int *)result = sc->mmc_host.ocr;
            break;
        case MMCBR_IVAR_POWER_MODE:
            *(int *)result = sc->mmc_host.ios.power_mode;
            break;
        case MMCBR_IVAR_VDD:
            *(int *)result = sc->mmc_host.ios.vdd;
            break;
        case MMCBR_IVAR_CAPS:
            *(int *)result = sc->mmc_host.caps;
            break;
        case MMCBR_IVAR_MAX_DATA:
            *(int *)result = 8192; /* This indicates we can handle multiblock transfers. */
            break;
        default:
            error = EINVAL;
    }

    return (error);
}

/* Set the current values of this device's instance variables. */
static int
a10_mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value)
{
    struct a10_mmc_softc *sc = device_get_softc(bus);
    int result = 0;

    switch (which) {
        case MMCBR_IVAR_BUS_MODE:
            sc->mmc_host.ios.bus_mode = value;
            break;
        case MMCBR_IVAR_BUS_WIDTH:
            sc->mmc_host.ios.bus_width = value;
            break;
        case MMCBR_IVAR_CHIP_SELECT:
            sc->mmc_host.ios.chip_select = value;
            break;
        case MMCBR_IVAR_CLOCK:
            sc->mmc_host.ios.clock = value;
            break;
        case MMCBR_IVAR_MODE:
            sc->mmc_host.mode = value;
            break;
        case MMCBR_IVAR_OCR:
            sc->mmc_host.ocr = value;
            break;
        case MMCBR_IVAR_POWER_MODE:
            sc->mmc_host.ios.power_mode = value;
            break;
        case MMCBR_IVAR_VDD:
            sc->mmc_host.ios.vdd = value;
            break;
        /* These are read-only. */
        case MMCBR_IVAR_CAPS:
        case MMCBR_IVAR_HOST_OCR:
        case MMCBR_IVAR_F_MIN:
        case MMCBR_IVAR_F_MAX:
        case MMCBR_IVAR_MAX_DATA:
        default:
            result = EINVAL;
    }

    return (result);
}

/* Update the current state of the host. */
static int
a10_mmc_update_ios(device_t bus, device_t child)
{
    int error = 0;
    struct a10_mmc_softc *sc = device_get_softc(bus);
    struct mmc_ios *ios = &sc->mmc_host.ios;

    /* Set the bus width. */
    a10_mmc_set_bus_width(sc, ios);

    if (ios->clock) {
        /* Disable clock. */
        error = a10_mmc_set_clock_enabled(sc, 0);

        if (!error) {
            /* Set clock rate. */
            error = a10_mmc_set_clock_rate(sc, ios);

            if (!error) {
                /* Enable clock. */
                error = a10_mmc_set_clock_enabled(sc, 1);
            }
        }
    }

    return (error);
}

/* Enable/disable the clock. */
static int
a10_mmc_set_clock_enabled(struct a10_mmc_softc *sc, int enabled)
{
    int error = 0;
    uint32_t clock_control_reg_value = a10_mmc_read_4(sc, A10_MMC_CLOCK_CONTROL_REG);

    if (enabled) {
        clock_control_reg_value |= A10_MMC_CARD_CLOCK_ON;
    } else {
        clock_control_reg_value &= ~A10_MMC_CARD_CLOCK_ON;
    }

    a10_mmc_write_4(sc, A10_MMC_CLOCK_CONTROL_REG, clock_control_reg_value);

    error = a10_mmc_update_clock(sc);

    return (error);
}

/* Set the clock rate. */
static int
a10_mmc_set_clock_rate(struct a10_mmc_softc *sc, struct mmc_ios *ios)
{
    int error = 0;
    uint32_t clock_divider = 0;
    uint32_t clock_control_reg_value = a10_mmc_read_4(sc, A10_MMC_CLOCK_CONTROL_REG);

    clock_divider = (sc->mod_clock + (ios->clock >> 1));
    clock_divider /= ios->clock;
    clock_divider /= 2;

    /* Change divider. */
    clock_control_reg_value &= ~(0xFF);
    clock_control_reg_value |= clock_divider;
    a10_mmc_write_4(sc, A10_MMC_CLOCK_CONTROL_REG, clock_control_reg_value);

    error = a10_mmc_update_clock(sc);

    return (error);
}

/* Issue a command which will update the clock registers. */
static int
a10_mmc_update_clock(struct a10_mmc_softc *sc)
{
    int error = 0;
    uint32_t time_left = 0xFFFF;
    uint32_t raw_isr;
    uint32_t command_reg_value = A10_MMC_START |
                                 A10_MMC_UPDATE_CLOCK_REGS_ONLY |
                                 A10_MMC_WAIT_PREVIOUS_DATA_OVER;

    a10_mmc_write_4(sc, A10_MMC_COMMAND_REG, command_reg_value);

    do {
        command_reg_value = a10_mmc_read_4(sc, A10_MMC_COMMAND_REG);
    } while ((command_reg_value & A10_MMC_START) && (--time_left));

    /* Updating the clock may set some ISR bits; clear them now. */
    raw_isr = a10_mmc_read_4(sc, A10_MMC_RAW_INTERRUPT_STATUS_REG);
    a10_mmc_write_4(sc, A10_MMC_RAW_INTERRUPT_STATUS_REG, raw_isr);

    if (!time_left) {
        device_printf(sc->device, "Clock update timeout!");
        error = EIO;
    }

    return (error);
}

static void
a10_mmc_set_bus_width(struct a10_mmc_softc *sc, struct mmc_ios *ios)
{
    switch (ios->bus_width) {
        case bus_width_1:
            a10_mmc_write_4(sc, A10_MMC_WIDTH_REG, A10_MMC_WIDTH1);
            break;
        case bus_width_4:
            a10_mmc_write_4(sc, A10_MMC_WIDTH_REG, A10_MMC_WIDTH4);
            break;
        case bus_width_8:
            a10_mmc_write_4(sc, A10_MMC_WIDTH_REG, A10_MMC_WIDTH8);
    }
}

static int
a10_mmc_get_ro(device_t bus, device_t child)
{
    return (0);
}

static int
a10_mmc_acquire_host(device_t bus, device_t child)
{
    struct a10_mmc_softc *sc = device_get_softc(bus);
    int error = 0;

    a10_mmc_lock(sc);

    while (sc->bus_busy) {
        error = mtx_sleep(sc, &sc->mutex, PZERO, "a10_mmc", 0);
    }

    sc->bus_busy++;
    a10_mmc_unlock(sc);

    return (error);
}

static int
a10_mmc_release_host(device_t bus, device_t child)
{
    struct a10_mmc_softc *sc = device_get_softc(bus);

    a10_mmc_lock(sc);
    sc->bus_busy--;
    wakeup(sc);
    a10_mmc_unlock(sc);

    return (0);
}

static device_method_t a10_mmc_methods[] = {
    /* Device interface. */
    DEVMETHOD(device_probe,   a10_mmc_probe),
    DEVMETHOD(device_attach,  a10_mmc_attach),
    DEVMETHOD(device_detach,  a10_mmc_detach),

    /* Bus interface. */
    DEVMETHOD(bus_read_ivar,   a10_mmc_read_ivar),
    DEVMETHOD(bus_write_ivar,  a10_mmc_write_ivar),
    DEVMETHOD(bus_print_child, bus_generic_print_child),

    /* MMC bridge interface. */
    DEVMETHOD(mmcbr_update_ios,   a10_mmc_update_ios),
    DEVMETHOD(mmcbr_request,      a10_mmc_request),
    DEVMETHOD(mmcbr_get_ro,       a10_mmc_get_ro),
    DEVMETHOD(mmcbr_acquire_host, a10_mmc_acquire_host),
    DEVMETHOD(mmcbr_release_host, a10_mmc_release_host),

    { 0, 0 }
};

static devclass_t a10_mmc_devclass;

static driver_t a10_mmc_driver = {
    "a10_mmc",
    a10_mmc_methods,
    sizeof(struct a10_mmc_softc)
};

DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, 0, 0);




/*-
 * Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
 * All rights reserved.
 *
 * Copyright (c) 2013-2014:
 * Computer Architecture Laboratory, National University of Cordoba. Cordoba, Argentina.
 * Nicolas Vidable <njvidable@gmail.com>
 * Martin Galvan <omgalvan.86@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

#ifndef _A10_MMC_H_
#define _A10_MMC_H_

#define A10_MMC_GLOBAL_CONTROL_REG                     0x00 /* Global Control Register */
#define A10_MMC_CLOCK_CONTROL_REG                      0x04 /* Clock Control Register */
#define A10_MMC_TIMEOUT_REG                            0x08 /* Time Out Register */
#define A10_MMC_WIDTH_REG                              0x0C /* Bus Width Register */
#define A10_MMC_BLOCK_SIZE_REG                         0x10 /* Block Size Register */
#define A10_MMC_BYTE_COUNT_REG                         0x14 /* Byte Count Register */
#define A10_MMC_COMMAND_REG                            0x18 /* Command Register */
#define A10_MMC_ARGUMENT_REG                           0x1C /* Argument Register */
#define A10_MMC_RESPONSE_REG_0                         0x20 /* Response Register 0 */
#define A10_MMC_RESPONSE_REG_1                         0x24 /* Response Register 1 */
#define A10_MMC_RESPONSE_REG_2                         0x28 /* Response Register 2 */
#define A10_MMC_RESPONSE_REG_3                         0x2C /* Response Register 3 */
#define A10_MMC_INTERRUPT_MASK_REG                     0x30 /* Interrupt Mask Register */
#define A10_MMC_MASKED_INTERRUPT_STATUS_REG            0x34 /* Masked Interrupt Status Register */
#define A10_MMC_RAW_INTERRUPT_STATUS_REG               0x38 /* Raw Interrupt Status Register */
#define A10_MMC_STATUS_REG                             0x3C /* Status Register */
#define A10_MMC_FIFO_THRESHOLD_WATERMARK_REG           0x40 /* FIFO Threshold Watermark Register */
#define A10_MMC_FUNCTION_SELECT_REG                    0x44 /* Function Select Register */
#define A10_MMC_CIU_BYTE_COUNT_REG                     0x48 /* CIU Byte Count Register */
#define A10_MMC_BIU_BYTE_COUNT_REG                     0x4C /* BIU Byte Count Register */
#define A10_MMC_DEBUG_ENABLE_REG                       0x50 /* Debug Enable Register */
#define A10_MMC_IDMAC_CONTROL_REG                      0x80 /* IDMAC Control Register */
#define A10_MMC_IDMAC_DESCRIPTOR_LIST_BASE_ADDRESS_REG 0x84 /* IDMAC Descriptor List Base Address Register */
#define A10_MMC_IDMAC_STATUS_REG                       0x88 /* IDMAC Status Register */
#define A10_MMC_IDMAC_INTERRUPT_ENABLE_REG             0x8C /* IDMAC Interrupt Enable Register */
#define A10_MMC_CURRENT_HOST_DESCRIPTOR_ADDRESS_REG    0x90 /* IDMAC Current Host Descriptor Address */
#define A10_MMC_CURRENT_BUFFER_DESCRIPTOR_ADDRESS_REG  0x94 /* IDMAC Current Buffer Descriptor Address */
#define A10_MMC_FIFO_ACCESS_ADDRESS                    0x100 /* FIFO Access Address */

/* Global control register bits (A10_MMC_GLOBAL_CONTROL_REG) */
#define A10_MMC_SOFT_RESET               (1 << 0)
#define A10_MMC_FIFO_RESET               (1 << 1)
#define A10_MMC_DMA_RESET                (1 << 2)
#define A10_MMC_INTERRUPT_ENABLE         (1 << 4)
#define A10_MMC_DMA_ENABLE               (1 << 5)
#define A10_MMC_DEBOUNCE_ENABLE          (1 << 8)
#define A10_MMC_POSEDGE_LATCH_DATA       (1 << 9) /* 0: Negedge; 1: Posedge */
#define A10_MMC_DDR_MODE                 (1 << 10)
#define A10_MMC_ACCESS_DONE_DIRECT       (1 << 30)
#define A10_MMC_ACCESS_BY_AHB            (1 << 31) /* 0: DMA; 1: AHB */
#define A10_MMC_HARDWARE_RESET_BITS    \
    (A10_MMC_SOFT_RESET |              \
     A10_MMC_FIFO_RESET |              \
     A10_MMC_DMA_RESET)

/* Clock control bits (A10_MMC_CLOCK_CONTROL_REG) */
#define A10_MMC_CARD_CLOCK_ON            (1 << 16)
#define A10_MMC_CARD_CLOCK_OFF           (0 << 16)
#define A10_MMC_LOW_POWER_ON             (1 << 17)
#define A10_MMC_LOW_POWER_OFF            (0 << 17)

/* Bus width (A10_MMC_WIDTH_REG) */
#define A10_MMC_WIDTH1                   (0)
#define A10_MMC_WIDTH4                   (1)
#define A10_MMC_WIDTH8                   (2)

/* Command bits (A10_MMC_COMMAND_REG) */
#define A10_MMC_RESPONSE_EXPECTED        (1 << 6)
#define A10_MMC_LONG_RESPONSE            (1 << 7)
#define A10_MMC_CHECK_RESPONSE_CRC       (1 << 8)
#define A10_MMC_DATA_EXPECTED            (1 << 9)
#define A10_MMC_WRITE                    (1 << 10)
#define A10_MMC_STREAM_MODE              (1 << 11)  /* 0: Block mode; 1: Stream mode */
#define A10_MMC_SEND_AUTO_STOP           (1 << 12)
#define A10_MMC_WAIT_PREVIOUS_DATA_OVER  (1 << 13)
#define A10_MMC_STOP_ABORT_COMMAND       (1 << 14)
#define A10_MMC_SEND_INIT_SEQUENCE       (1 << 15)
#define A10_MMC_UPDATE_CLOCK_REGS_ONLY   (1 << 21)
#define A10_MMC_READ_CEATA_DEVICE        (1 << 22)
#define A10_MMC_CCS_EXPECTED             (1 << 23) /* CCS: Command Completion Signal */
#define A10_MMC_ENABLE_BOOT              (1 << 24)
#define A10_MMC_ALT_BOOT_OPTIONS         (1 << 25) /* 0: Mandatory; 1: Alternative */
#define A10_MMC_BOOT_ACK_EXPIRE          (1 << 26)
#define A10_MMC_DISABLE_BOOT             (1 << 27)
#define A10_MMC_VOLTAGE_SWITCH           (1 << 28)
#define A10_MMC_START                    (1 << 31)

/* Interrupt bits (A10_MMC_INTERRUPT_MASK_REG, A10_MMC_MASKED_INTERRUPT_STATUS_REG
 *and A10_MMC_RAW_INTERRUPT_STATUS_REG)
 */
#define A10_MMC_RESPONSE_ERROR           (1 << 1)
#define A10_MMC_COMMAND_DONE             (1 << 2)
#define A10_MMC_DATA_TRANSFER_OVER       (1 << 3)
#define A10_MMC_TX_DATA_REQUEST          (1 << 4)
#define A10_MMC_RX_DATA_REQUEST          (1 << 5)
#define A10_MMC_RESPONSE_CRC_ERROR       (1 << 6)
#define A10_MMC_DATA_CRC_ERROR           (1 << 7)
#define A10_MMC_RESPONSE_TIMEOUT         (1 << 8)
#define A10_MMC_BOOT_ACK_RECEIVED        (1 << 8)
#define A10_MMC_DATA_READ_TIMEOUT        (1 << 9)
#define A10_MMC_BOOT_DATA_START          (1 << 9)
#define A10_MMC_DATA_STARVATION_BY_HOST  (1 << 10)
#define A10_MMC_VOLTAGE_CHANGE_DONE      (1 << 10)
#define A10_MMC_FIFO_RUN_ERROR           (1 << 11) /* Underrun/overrun error */
#define A10_MMC_HARDWARE_LOCKED          (1 << 12)
#define A10_MMC_START_BIT_ERROR          (1 << 13)
#define A10_MMC_AUTO_COMMAND_DONE        (1 << 14)
#define A10_MMC_END_BIT_ERROR            (1 << 15)
#define A10_MMC_SDIO_INTERRUPT           (1 << 16)
#define A10_MMC_CARD_INSERT              (1 << 30)
#define A10_MMC_CARD_REMOVE              (1 << 31)
#define A10_MMC_INTERRUPT_ERROR_BITS   \
    (A10_MMC_RESPONSE_ERROR |          \
     A10_MMC_RESPONSE_CRC_ERROR |      \
     A10_MMC_DATA_CRC_ERROR |          \
     A10_MMC_RESPONSE_TIMEOUT |        \
     A10_MMC_DATA_READ_TIMEOUT |       \
     A10_MMC_FIFO_RUN_ERROR |          \
     A10_MMC_HARDWARE_LOCKED |         \
     A10_MMC_START_BIT_ERROR |         \
     A10_MMC_END_BIT_ERROR)
#define A10_MMC_INTERRUPT_DONE_BITS    \
    (A10_MMC_AUTO_COMMAND_DONE |       \
     A10_MMC_DATA_TRANSFER_OVER |      \
     A10_MMC_COMMAND_DONE |            \
     A10_MMC_VOLTAGE_CHANGE_DONE)

/* Status bits (A10_MMC_STATUS_REG) */
#define A10_MMC_RX_WATERMARK_LEVEL_REACHED  (1 << 0)
#define A10_MMC_TX_WATERMARK_LEVEL_REACHED  (1 << 1)
#define A10_MMC_FIFO_EMPTY                  (1 << 2)
#define A10_MMC_FIFO_FULL                   (1 << 3)
#define A10_MMC_CARD_PRESENT                (1 << 8)
#define A10_MMC_CARD_DATA_BUSY              (1 << 9)
#define A10_MMC_DATA_FSM_BUSY               (1 << 10)
#define A10_MMC_DMA_REQUEST                 (1 << 31)
#define A10_MMC_FIFO_SIZE                   (16)

/* Function select bits (A10_MMC_FUNCTION_SELECT_REG) */
#define A10_MMC_CE_ATA_ON                      (0xCEAAU << 16)
#define A10_MMC_SEND_IRQ_RESPONSE              (1 << 0)
#define A10_MMC_SDIO_READ_WAIT                 (1 << 1)
#define A10_MMC_ABORT_READ_DATA                (1 << 2)
#define A10_MMC_SEND_CC_SD                     (1 << 8)
#define A10_MMC_SEND_AUTO_STOP_CC_SD           (1 << 9)
#define A10_MMC_CE_ATA_DEVICE_INTERRUPT_ENABLE (1 << 10)

/* IDMA descriptor fields and configuration bits */
#define A10_MMC_ALIGNMENT                              4
#define A10_MMC_MAX_BLOCK_SIZE                         4096
#define A10_MMC_IDMAC_MAX_SEGMENT_SIZE                 8192
#define A10_MMC_IDMAC_DISABLE_INTERRUPT_ON_COMPLETION  (1 << 1) /* Disable interrupt on completion */
#define A10_MMC_IDMAC_LAST_DESCRIPTOR	               (1 << 2) /* Last descriptor */
#define A10_MMC_IDMAC_FIRST_DESCRIPTOR	               (1 << 3) /* First descriptor */
#define A10_MMC_IDMAC_SECOND_ADDRESS_CHAINED	       (1 << 4) /* Chain mode */
#define A10_MMC_IDMAC_OWNED_BY_IDMAC	               (1 << 31) /* 1: owned by IDMAC; 0: owned by host */
#define A10_MMC_IDMAC_DESCRIPTOR_CONFIG_BITS          \
    (A10_MMC_IDMAC_SECOND_ADDRESS_CHAINED |           \
     A10_MMC_IDMAC_OWNED_BY_IDMAC |                   \
     A10_MMC_IDMAC_DISABLE_INTERRUPT_ON_COMPLETION)

/* IDMA controller bus mod bit field */
#define A10_MMC_IDMAC_SOFT_RESET         (1 << 0)
#define A10_MMC_IDMAC_FIX_BURST          (1 << 1)
#define A10_MMC_IDMAC_IDMA_ON            (1 << 7)
#define A10_MMC_IDMAC_REFETCH_DES        (1 << 31)

/* IDMA controller status bits (A10_MMC_IDMAC_STATUS_REG) */
#define A10_MMC_IDMAC_TRANSMIT_INTERRUPT         (1 << 0)
#define A10_MMC_IDMAC_RECEIVE_INTERRUPT          (1 << 1)
#define A10_MMC_IDMAC_FATAL_BUS_ERROR            (1 << 2)
#define A10_MMC_IDMAC_DESCRIPTOR_UNAVAILABLE     (1 << 4)
#define A10_MMC_IDMAC_CARD_ERROR_SUMMARY         (1 << 5)
#define A10_MMC_IDMAC_NORMAL_INTERRUPT_SUMMARY   (1 << 8)
#define A10_MMC_IDMAC_ABNORMAL_INTERRUPT_SUMMARY (1 << 9)
#define A10_MMC_IDMAC_HOST_ABORT                 (1 << 10)
#define A10_MMC_IDMAC_SUSPEND                    (1 << 13) /* 0: Idle; 1: Suspend */
#define A10_MMC_IDMAC_DESC_READ                  (0x2U << 13)
#define A10_MMC_IDMAC_DESC_CHECK                 (0x3U << 13)
#define A10_MMC_IDMAC_READ_REQUEST_WAIT          (0x4U << 13)
#define A10_MMC_IDMAC_WRITE_REQUEST_WAIT         (0x5U << 13)
#define A10_MMC_IDMAC_READ                       (0x6U << 13)
#define A10_MMC_IDMAC_WRITE                      (0x7U << 13)
#define A10_MMC_IDMAC_DESC_CLOSE                 (0x8U << 13)

#define A10_MMC_IDMAC_OVER_BITS                \
    (A10_MMC_IDMAC_TRANSMIT_INTERRUPT |        \
     A10_MMC_IDMAC_RECEIVE_INTERRUPT |         \
     A10_MMC_IDMAC_NORMAL_INTERRUPT_SUMMARY)

#define A10_MMC_IDMAC_ERROR_BITS               \
    (A10_MMC_IDMAC_FATAL_BUS_ERROR |           \
     A10_MMC_IDMAC_DESCRIPTOR_UNAVAILABLE |    \
     A10_MMC_IDMAC_CARD_ERROR_SUMMARY |        \
     A10_MMC_IDMAC_ABNORMAL_INTERRUPT_SUMMARY)

#endif /* _A10_MMC_H_ */

Lines 15-20 arm/allwinner/a10_ehci.c optional ehci Link Here

(-)b/sys/arm/allwinner/files.a10 (+1 lines)
15	arm/allwinner/a10_machdep.c standard	15	arm/allwinner/a10_machdep.c standard
16	arm/allwinner/a10_sramc.c standard	16	arm/allwinner/a10_sramc.c standard
17	arm/allwinner/a10_wdog.c standard	17	arm/allwinner/a10_wdog.c standard
		18	arm/allwinner/a10_mmc.c optional mmc
18	arm/allwinner/a20/a20_cpu_cfg.c standard	19	arm/allwinner/a20/a20_cpu_cfg.c standard
19	arm/allwinner/aintc.c standard	20	arm/allwinner/aintc.c standard
20	arm/allwinner/if_emac.c optional emac	21	arm/allwinner/if_emac.c optional emac

Lines 78-85 options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed Link Here

(-)b/sys/arm/conf/CUBIEBOARD (-2 / +2 lines)
78	#options BOOTP_WIRED_TO=cpsw0	78	#options BOOTP_WIRED_TO=cpsw0
79		79
80	# MMC/SD/SDIO card slot support	80	# MMC/SD/SDIO card slot support
81	#device mmc # mmc/sd bus	81	device mmc # mmc/sd bus
82	#device mmcsd # mmc/sd flash cards	82	device mmcsd # mmc/sd flash cards
83		83
84	# Boot device is 2nd slice on MMC/SD card	84	# Boot device is 2nd slice on MMC/SD card
85	options ROOTDEVNAME=\"ufs:/dev/da0s2\"	85	options ROOTDEVNAME=\"ufs:/dev/da0s2\"

Lines 60-65 Link Here

(-)b/sys/boot/fdt/dts/arm/cubieboard.dts (+4 lines)
60	emac@01c0b000 {	60	emac@01c0b000 {
61	status = "okay";	61	status = "okay";
62	};	62	};
		63
		64	mmc@0x01c0f000 {
		65	status = "okay";
		66	};
63	};	67	};
64		68
65	chosen {	69	chosen {

Lines 103-108 Link Here

(-)b/sys/boot/fdt/dts/arm/sun4i-a10.dtsi (+7 lines)
103	interrupt-parent = <&AINTC>;	103	interrupt-parent = <&AINTC>;
104	};	104	};
105		105
		106	mmc@0x01c0f000 {
		107	compatible = "allwinner,sun4i-mmc";
		108	reg = <0x01c0f000 0x1000>;
		109	interrupts = <32>;
		110	interrupt-parent = <&AINTC>;
		111	};
		112
106	sata@01c18000 {	113	sata@01c18000 {
107	compatible = "allwinner,sun4i-ahci";	114	compatible = "allwinner,sun4i-ahci";
108	reg = <0x01c18000 0x1000>;	115	reg = <0x01c18000 0x1000>;

Lines 1774-1777 DRIVER_MODULE(mmc, sdhci_pci, mmc_driver, mmc_devclass, NULL, NULL); Link Here

(-)b/sys/dev/mmc/mmc.c (-1 / +1 lines)
1774	DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL);	1774	DRIVER_MODULE(mmc, sdhci_ti, mmc_driver, mmc_devclass, NULL, NULL);
1775	DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL);	1775	DRIVER_MODULE(mmc, ti_mmchs, mmc_driver, mmc_devclass, NULL, NULL);
1776	DRIVER_MODULE(mmc, dwmmc, mmc_driver, mmc_devclass, NULL, NULL);	1776	DRIVER_MODULE(mmc, dwmmc, mmc_driver, mmc_devclass, NULL, NULL);
1777		1777	DRIVER_MODULE(mmc, a10_mmc, mmc_driver, mmc_devclass, NULL, NULL);

Return to bug 196081

Lines 41-46 __FBSDID("$FreeBSD$"); Link Here

(-)b/sys/arm/allwinner/a10_clk.c (-9 / +46 lines)
41	#include <sys/watchdog.h>	41	#include <sys/watchdog.h>
42	#include <machine/bus.h>	42	#include <machine/bus.h>
43	#include <machine/cpu.h>	43	#include <machine/cpu.h>
		44	#include <machine/frame.h>
44	#include <machine/intr.h>	45	#include <machine/intr.h>
45		46
46	#include <dev/fdt/fdt_common.h>	47	#include <dev/fdt/fdt_common.h>
Lines 69-84 static struct a10_ccm_softc *a10_ccm_sc = NULL; Link Here
69	static int	70	static int
70	a10_ccm_probe(device_t dev)	71	a10_ccm_probe(device_t dev)
71	{	72	{
72		73	int result = ENXIO;
73	if (!ofw_bus_status_okay(dev))
74	return (ENXIO);
75		74
76	if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) {	75	if (ofw_bus_is_compatible(dev, "allwinner,sun4i-ccm")) {
77	device_set_desc(dev, "Allwinner Clock Control Module");	76	device_set_desc(dev, "Allwinner Clock Control Module");
78	return(BUS_PROBE_DEFAULT);	77	result = BUS_PROBE_DEFAULT;
79	}	78	}
80		79
81	return (ENXIO);	80	return (result);
82	}	81	}
83		82
84	static int	83	static int
Lines 87-94 a10_ccm_attach(device_t dev) Link Here
87	struct a10_ccm_softc *sc = device_get_softc(dev);	86	struct a10_ccm_softc *sc = device_get_softc(dev);
88	int rid = 0;	87	int rid = 0;
89		88
90	if (a10_ccm_sc)	89	if (a10_ccm_sc) {
91	return (ENXIO);	90	return (ENXIO);
		91	}
92		92
93	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);	93	sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
94	if (!sc->res) {	94	if (!sc->res) {
Lines 101-106 a10_ccm_attach(device_t dev) Link Here
101		101
102	a10_ccm_sc = sc;	102	a10_ccm_sc = sc;
103		103
		104	ccm_write_4(sc, CCM_PLL6_CFG, CCM_PLL6_DEFAULT_CONFIG);
		105
104	return (0);	106	return (0);
105	}	107	}
106		108
Lines 126-133 a10_clk_usb_activate(void) Link Here
126	struct a10_ccm_softc *sc = a10_ccm_sc;	128	struct a10_ccm_softc *sc = a10_ccm_sc;
127	uint32_t reg_value;	129	uint32_t reg_value;
128		130
129	if (sc == NULL)	131	if (sc == NULL) {
130	return (ENXIO);	132	return (ENXIO);
		133	}
131		134
132	/* Gating AHB clock for USB */	135	/* Gating AHB clock for USB */
133	reg_value = ccm_read_4(sc, CCM_AHB_GATING0);	136	reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
Lines 153-160 a10_clk_usb_deactivate(void) Link Here
153	struct a10_ccm_softc *sc = a10_ccm_sc;	156	struct a10_ccm_softc *sc = a10_ccm_sc;
154	uint32_t reg_value;	157	uint32_t reg_value;
155		158
156	if (sc == NULL)	159	if (sc == NULL) {
157	return (ENXIO);	160	return (ENXIO);
		161	}
158		162
159	/* Disable clock for USB */	163	/* Disable clock for USB */
160	reg_value = ccm_read_4(sc, CCM_USB_CLK);	164	reg_value = ccm_read_4(sc, CCM_USB_CLK);
Lines 175-180 a10_clk_usb_deactivate(void) Link Here
175	}	179	}
176		180
177	int	181	int
		182	a10_clk_mmc_activate(uint32_t *mod_clk)
		183	{
		184	struct a10_ccm_softc *sc = a10_ccm_sc;
		185	uint32_t reg_value;
		186	uint32_t pll6_clk;
		187	uint32_t divider;
		188	uint32_t n, k;
		189
		190	if (sc == NULL) {
		191	return (ENXIO);
		192	}
		193
		194	/* Gating AHB clock for SDMMC0 */
		195	reg_value = ccm_read_4(sc, CCM_AHB_GATING0);
		196	reg_value \|= CCM_AHB_GATING_SDMMC0 \| CCM_AHB_GATING_DMA;
		197	ccm_write_4(sc, CCM_AHB_GATING0, reg_value);
		198
		199	/* Config mod clock */
		200	reg_value = ccm_read_4(sc, CCM_PLL6_CFG);
		201	n = (reg_value >> 8) & 0x1f;
		202	k = ((reg_value >> 4) & 3) + 1;
		203	pll6_clk = 24000000 * n * k / 2;
		204
		205	divider = ((pll6_clk + 99999999) / 100000000) - 1;
		206
		207	ccm_write_4(sc, CCM_MMC0_SCLK_CFG,
		208	CCM_MMC0_GATE_PASS \| CCM_MMC0_CLK_SRC_PLL6 \| divider);
		209
		210	*mod_clk = pll6_clk / (divider + 1);
		211
		212	return (0);
		213	}
		214
		215	int
178	a10_clk_emac_activate(void) {	216	a10_clk_emac_activate(void) {
179	struct a10_ccm_softc *sc = a10_ccm_sc;	217	struct a10_ccm_softc *sc = a10_ccm_sc;
180	uint32_t reg_value;	218	uint32_t reg_value;
Lines 189-192 a10_clk_emac_activate(void) { Link Here
189		227
190	return (0);	228	return (0);
191	}	229	}
192

Added Link Here

(-)b/sys/arm/allwinner/a10_mmcreg.h (+223 lines)
1	/*-
2	* Copyright (c) 2013 Alexander Fedorov <alexander.fedorov@rtlservice.com>
3	* All rights reserved.
4	*
5	* Copyright (c) 2013-2014:
6	* Computer Architecture Laboratory, National University of Cordoba. Cordoba, Argentina.
7	* Nicolas Vidable <njvidable@gmail.com>
8	* Martin Galvan <omgalvan.86@gmail.com>
9	* All rights reserved.
10	*
11	* Redistribution and use in source and binary forms, with or without
12	* modification, are permitted provided that the following conditions
13	* are met:
14	* 1. Redistributions of source code must retain the above copyright
15	* notice, this list of conditions and the following disclaimer.
16	* 2. Redistributions in binary form must reproduce the above copyright
17	* notice, this list of conditions and the following disclaimer in the
18	* documentation and/or other materials provided with the distribution.
19	*
20	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30	* SUCH DAMAGE.
31	*
32	*/
33
34	#ifndef _A10_MMC_H_
35	#define _A10_MMC_H_
36
37	#define A10_MMC_GLOBAL_CONTROL_REG 0x00 /* Global Control Register */
38	#define A10_MMC_CLOCK_CONTROL_REG 0x04 /* Clock Control Register */
39	#define A10_MMC_TIMEOUT_REG 0x08 /* Time Out Register */
40	#define A10_MMC_WIDTH_REG 0x0C /* Bus Width Register */
41	#define A10_MMC_BLOCK_SIZE_REG 0x10 /* Block Size Register */
42	#define A10_MMC_BYTE_COUNT_REG 0x14 /* Byte Count Register */
43	#define A10_MMC_COMMAND_REG 0x18 /* Command Register */
44	#define A10_MMC_ARGUMENT_REG 0x1C /* Argument Register */
45	#define A10_MMC_RESPONSE_REG_0 0x20 /* Response Register 0 */
46	#define A10_MMC_RESPONSE_REG_1 0x24 /* Response Register 1 */
47	#define A10_MMC_RESPONSE_REG_2 0x28 /* Response Register 2 */
48	#define A10_MMC_RESPONSE_REG_3 0x2C /* Response Register 3 */
49	#define A10_MMC_INTERRUPT_MASK_REG 0x30 /* Interrupt Mask Register */
50	#define A10_MMC_MASKED_INTERRUPT_STATUS_REG 0x34 /* Masked Interrupt Status Register */
51	#define A10_MMC_RAW_INTERRUPT_STATUS_REG 0x38 /* Raw Interrupt Status Register */
52	#define A10_MMC_STATUS_REG 0x3C /* Status Register */
53	#define A10_MMC_FIFO_THRESHOLD_WATERMARK_REG 0x40 /* FIFO Threshold Watermark Register */
54	#define A10_MMC_FUNCTION_SELECT_REG 0x44 /* Function Select Register */
55	#define A10_MMC_CIU_BYTE_COUNT_REG 0x48 /* CIU Byte Count Register */
56	#define A10_MMC_BIU_BYTE_COUNT_REG 0x4C /* BIU Byte Count Register */
57	#define A10_MMC_DEBUG_ENABLE_REG 0x50 /* Debug Enable Register */
58	#define A10_MMC_IDMAC_CONTROL_REG 0x80 /* IDMAC Control Register */
59	#define A10_MMC_IDMAC_DESCRIPTOR_LIST_BASE_ADDRESS_REG 0x84 /* IDMAC Descriptor List Base Address Register */
60	#define A10_MMC_IDMAC_STATUS_REG 0x88 /* IDMAC Status Register */
61	#define A10_MMC_IDMAC_INTERRUPT_ENABLE_REG 0x8C /* IDMAC Interrupt Enable Register */
62	#define A10_MMC_CURRENT_HOST_DESCRIPTOR_ADDRESS_REG 0x90 /* IDMAC Current Host Descriptor Address */
63	#define A10_MMC_CURRENT_BUFFER_DESCRIPTOR_ADDRESS_REG 0x94 /* IDMAC Current Buffer Descriptor Address */
64	#define A10_MMC_FIFO_ACCESS_ADDRESS 0x100 /* FIFO Access Address */
65
66	/* Global control register bits (A10_MMC_GLOBAL_CONTROL_REG) */
67	#define A10_MMC_SOFT_RESET (1 << 0)
68	#define A10_MMC_FIFO_RESET (1 << 1)
69	#define A10_MMC_DMA_RESET (1 << 2)
70	#define A10_MMC_INTERRUPT_ENABLE (1 << 4)
71	#define A10_MMC_DMA_ENABLE (1 << 5)
72	#define A10_MMC_DEBOUNCE_ENABLE (1 << 8)
73	#define A10_MMC_POSEDGE_LATCH_DATA (1 << 9) /* 0: Negedge; 1: Posedge */
74	#define A10_MMC_DDR_MODE (1 << 10)
75	#define A10_MMC_ACCESS_DONE_DIRECT (1 << 30)
76	#define A10_MMC_ACCESS_BY_AHB (1 << 31) /* 0: DMA; 1: AHB */
77	#define A10_MMC_HARDWARE_RESET_BITS \
78	(A10_MMC_SOFT_RESET \| \
79	A10_MMC_FIFO_RESET \| \
80	A10_MMC_DMA_RESET)
81
82	/* Clock control bits (A10_MMC_CLOCK_CONTROL_REG) */
83	#define A10_MMC_CARD_CLOCK_ON (1 << 16)
84	#define A10_MMC_CARD_CLOCK_OFF (0 << 16)
85	#define A10_MMC_LOW_POWER_ON (1 << 17)
86	#define A10_MMC_LOW_POWER_OFF (0 << 17)
87
88	/* Bus width (A10_MMC_WIDTH_REG) */
89	#define A10_MMC_WIDTH1 (0)
90	#define A10_MMC_WIDTH4 (1)
91	#define A10_MMC_WIDTH8 (2)
92
93	/* Command bits (A10_MMC_COMMAND_REG) */
94	#define A10_MMC_RESPONSE_EXPECTED (1 << 6)
95	#define A10_MMC_LONG_RESPONSE (1 << 7)
96	#define A10_MMC_CHECK_RESPONSE_CRC (1 << 8)
97	#define A10_MMC_DATA_EXPECTED (1 << 9)
98	#define A10_MMC_WRITE (1 << 10)
99	#define A10_MMC_STREAM_MODE (1 << 11) /* 0: Block mode; 1: Stream mode */
100	#define A10_MMC_SEND_AUTO_STOP (1 << 12)
101	#define A10_MMC_WAIT_PREVIOUS_DATA_OVER (1 << 13)
102	#define A10_MMC_STOP_ABORT_COMMAND (1 << 14)
103	#define A10_MMC_SEND_INIT_SEQUENCE (1 << 15)
104	#define A10_MMC_UPDATE_CLOCK_REGS_ONLY (1 << 21)
105	#define A10_MMC_READ_CEATA_DEVICE (1 << 22)
106	#define A10_MMC_CCS_EXPECTED (1 << 23) /* CCS: Command Completion Signal */
107	#define A10_MMC_ENABLE_BOOT (1 << 24)
108	#define A10_MMC_ALT_BOOT_OPTIONS (1 << 25) /* 0: Mandatory; 1: Alternative */
109	#define A10_MMC_BOOT_ACK_EXPIRE (1 << 26)
110	#define A10_MMC_DISABLE_BOOT (1 << 27)
111	#define A10_MMC_VOLTAGE_SWITCH (1 << 28)
112	#define A10_MMC_START (1 << 31)
113
114	/* Interrupt bits (A10_MMC_INTERRUPT_MASK_REG, A10_MMC_MASKED_INTERRUPT_STATUS_REG
115	*and A10_MMC_RAW_INTERRUPT_STATUS_REG)
116	*/
117	#define A10_MMC_RESPONSE_ERROR (1 << 1)
118	#define A10_MMC_COMMAND_DONE (1 << 2)
119	#define A10_MMC_DATA_TRANSFER_OVER (1 << 3)
120	#define A10_MMC_TX_DATA_REQUEST (1 << 4)
121	#define A10_MMC_RX_DATA_REQUEST (1 << 5)
122	#define A10_MMC_RESPONSE_CRC_ERROR (1 << 6)
123	#define A10_MMC_DATA_CRC_ERROR (1 << 7)
124	#define A10_MMC_RESPONSE_TIMEOUT (1 << 8)
125	#define A10_MMC_BOOT_ACK_RECEIVED (1 << 8)
126	#define A10_MMC_DATA_READ_TIMEOUT (1 << 9)
127	#define A10_MMC_BOOT_DATA_START (1 << 9)
128	#define A10_MMC_DATA_STARVATION_BY_HOST (1 << 10)
129	#define A10_MMC_VOLTAGE_CHANGE_DONE (1 << 10)
130	#define A10_MMC_FIFO_RUN_ERROR (1 << 11) /* Underrun/overrun error */
131	#define A10_MMC_HARDWARE_LOCKED (1 << 12)
132	#define A10_MMC_START_BIT_ERROR (1 << 13)
133	#define A10_MMC_AUTO_COMMAND_DONE (1 << 14)
134	#define A10_MMC_END_BIT_ERROR (1 << 15)
135	#define A10_MMC_SDIO_INTERRUPT (1 << 16)
136	#define A10_MMC_CARD_INSERT (1 << 30)
137	#define A10_MMC_CARD_REMOVE (1 << 31)
138	#define A10_MMC_INTERRUPT_ERROR_BITS \
139	(A10_MMC_RESPONSE_ERROR \| \
140	A10_MMC_RESPONSE_CRC_ERROR \| \
141	A10_MMC_DATA_CRC_ERROR \| \
142	A10_MMC_RESPONSE_TIMEOUT \| \
143	A10_MMC_DATA_READ_TIMEOUT \| \
144	A10_MMC_FIFO_RUN_ERROR \| \
145	A10_MMC_HARDWARE_LOCKED \| \
146	A10_MMC_START_BIT_ERROR \| \
147	A10_MMC_END_BIT_ERROR)
148	#define A10_MMC_INTERRUPT_DONE_BITS \
149	(A10_MMC_AUTO_COMMAND_DONE \| \
150	A10_MMC_DATA_TRANSFER_OVER \| \
151	A10_MMC_COMMAND_DONE \| \
152	A10_MMC_VOLTAGE_CHANGE_DONE)
153
154	/* Status bits (A10_MMC_STATUS_REG) */
155	#define A10_MMC_RX_WATERMARK_LEVEL_REACHED (1 << 0)
156	#define A10_MMC_TX_WATERMARK_LEVEL_REACHED (1 << 1)
157	#define A10_MMC_FIFO_EMPTY (1 << 2)
158	#define A10_MMC_FIFO_FULL (1 << 3)
159	#define A10_MMC_CARD_PRESENT (1 << 8)
160	#define A10_MMC_CARD_DATA_BUSY (1 << 9)
161	#define A10_MMC_DATA_FSM_BUSY (1 << 10)
162	#define A10_MMC_DMA_REQUEST (1 << 31)
163	#define A10_MMC_FIFO_SIZE (16)
164
165	/* Function select bits (A10_MMC_FUNCTION_SELECT_REG) */
166	#define A10_MMC_CE_ATA_ON (0xCEAAU << 16)
167	#define A10_MMC_SEND_IRQ_RESPONSE (1 << 0)
168	#define A10_MMC_SDIO_READ_WAIT (1 << 1)
169	#define A10_MMC_ABORT_READ_DATA (1 << 2)
170	#define A10_MMC_SEND_CC_SD (1 << 8)
171	#define A10_MMC_SEND_AUTO_STOP_CC_SD (1 << 9)
172	#define A10_MMC_CE_ATA_DEVICE_INTERRUPT_ENABLE (1 << 10)
173
174	/* IDMA descriptor fields and configuration bits */
175	#define A10_MMC_ALIGNMENT 4
176	#define A10_MMC_MAX_BLOCK_SIZE 4096
177	#define A10_MMC_IDMAC_MAX_SEGMENT_SIZE 8192
178	#define A10_MMC_IDMAC_DISABLE_INTERRUPT_ON_COMPLETION (1 << 1) /* Disable interrupt on completion */
179	#define A10_MMC_IDMAC_LAST_DESCRIPTOR (1 << 2) /* Last descriptor */
180	#define A10_MMC_IDMAC_FIRST_DESCRIPTOR (1 << 3) /* First descriptor */
181	#define A10_MMC_IDMAC_SECOND_ADDRESS_CHAINED (1 << 4) /* Chain mode */
182	#define A10_MMC_IDMAC_OWNED_BY_IDMAC (1 << 31) /* 1: owned by IDMAC; 0: owned by host */
183	#define A10_MMC_IDMAC_DESCRIPTOR_CONFIG_BITS \
184	(A10_MMC_IDMAC_SECOND_ADDRESS_CHAINED \| \
185	A10_MMC_IDMAC_OWNED_BY_IDMAC \| \
186	A10_MMC_IDMAC_DISABLE_INTERRUPT_ON_COMPLETION)
187
188	/* IDMA controller bus mod bit field */
189	#define A10_MMC_IDMAC_SOFT_RESET (1 << 0)
190	#define A10_MMC_IDMAC_FIX_BURST (1 << 1)
191	#define A10_MMC_IDMAC_IDMA_ON (1 << 7)
192	#define A10_MMC_IDMAC_REFETCH_DES (1 << 31)
193
194	/* IDMA controller status bits (A10_MMC_IDMAC_STATUS_REG) */
195	#define A10_MMC_IDMAC_TRANSMIT_INTERRUPT (1 << 0)
196	#define A10_MMC_IDMAC_RECEIVE_INTERRUPT (1 << 1)
197	#define A10_MMC_IDMAC_FATAL_BUS_ERROR (1 << 2)
198	#define A10_MMC_IDMAC_DESCRIPTOR_UNAVAILABLE (1 << 4)
199	#define A10_MMC_IDMAC_CARD_ERROR_SUMMARY (1 << 5)
200	#define A10_MMC_IDMAC_NORMAL_INTERRUPT_SUMMARY (1 << 8)
201	#define A10_MMC_IDMAC_ABNORMAL_INTERRUPT_SUMMARY (1 << 9)
202	#define A10_MMC_IDMAC_HOST_ABORT (1 << 10)
203	#define A10_MMC_IDMAC_SUSPEND (1 << 13) /* 0: Idle; 1: Suspend */
204	#define A10_MMC_IDMAC_DESC_READ (0x2U << 13)
205	#define A10_MMC_IDMAC_DESC_CHECK (0x3U << 13)
206	#define A10_MMC_IDMAC_READ_REQUEST_WAIT (0x4U << 13)
207	#define A10_MMC_IDMAC_WRITE_REQUEST_WAIT (0x5U << 13)
208	#define A10_MMC_IDMAC_READ (0x6U << 13)
209	#define A10_MMC_IDMAC_WRITE (0x7U << 13)
210	#define A10_MMC_IDMAC_DESC_CLOSE (0x8U << 13)
211
212	#define A10_MMC_IDMAC_OVER_BITS \
213	(A10_MMC_IDMAC_TRANSMIT_INTERRUPT \| \
214	A10_MMC_IDMAC_RECEIVE_INTERRUPT \| \
215	A10_MMC_IDMAC_NORMAL_INTERRUPT_SUMMARY)
216
217	#define A10_MMC_IDMAC_ERROR_BITS \
218	(A10_MMC_IDMAC_FATAL_BUS_ERROR \| \
219	A10_MMC_IDMAC_DESCRIPTOR_UNAVAILABLE \| \
220	A10_MMC_IDMAC_CARD_ERROR_SUMMARY \| \
221	A10_MMC_IDMAC_ABNORMAL_INTERRUPT_SUMMARY)
222
223	#endif /* _A10_MMC_H_ */