Attachment #152502 for bug #197259




// bswap MipsPattern
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;

// Carry pattern
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
              (DSUBu GPR64:$lhs, GPR64:$rhs)>;
let AdditionalPredicates = [NotDSP] in {
  def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
                (DADDu GPR64:$lhs, GPR64:$rhs)>;
  def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
                (DADDiu GPR64:$lhs, imm:$imm)>;
}

//===----------------------------------------------------------------------===//
// Instruction aliases
//===----------------------------------------------------------------------===//

Lines 261-266 MipsTargetLowering::MipsTargetLowering(const MipsT Link Here

(-)lib/Target/Mips/MipsISelLowering.cpp (-26 / +28 lines)
261	setOperationAction(ISD::LOAD, MVT::i64, Custom);	261	setOperationAction(ISD::LOAD, MVT::i64, Custom);
262	setOperationAction(ISD::STORE, MVT::i64, Custom);	262	setOperationAction(ISD::STORE, MVT::i64, Custom);
263	setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);	263	setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
		264	setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
		265	setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
		266	setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
264	}	267	}
265		268
266	if (!Subtarget.isGP64bit()) {	269	if (!Subtarget.isGP64bit()) {
Lines 2017-2026 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDVa Link Here
2017	SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,	2020	SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2018	SelectionDAG &DAG) const {	2021	SelectionDAG &DAG) const {
2019	SDLoc DL(Op);	2022	SDLoc DL(Op);
		2023	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
		2024
2020	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);	2025	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2021	SDValue Shamt = Op.getOperand(2);	2026	SDValue Shamt = Op.getOperand(2);
2022		2027	// if shamt < (VT.bits):
2023	// if shamt < 32:
2024	// lo = (shl lo, shamt)	2028	// lo = (shl lo, shamt)
2025	// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))	2029	// hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2026	// else:	2030	// else:
Lines 2028-2045 SDValue MipsTargetLowering::lowerShiftLeftParts(SD Link Here
2028	// hi = (shl lo, shamt[4:0])	2032	// hi = (shl lo, shamt[4:0])
2029	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,	2033	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2030	DAG.getConstant(-1, MVT::i32));	2034	DAG.getConstant(-1, MVT::i32));
2031	SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,	2035	SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2032	DAG.getConstant(1, MVT::i32));	2036	DAG.getConstant(1, VT));
2033	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,	2037	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2034	Not);	2038	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2035	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);	2039	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2036	SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);	2040	SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2037	SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
2038	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,	2041	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2039	DAG.getConstant(0x20, MVT::i32));	2042	DAG.getConstant(0x20, MVT::i32));
2040	Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,	2043	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2041	DAG.getConstant(0, MVT::i32), ShiftLeftLo);	2044	DAG.getConstant(0, VT), ShiftLeftLo);
2042	Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);	2045	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2043		2046
2044	SDValue Ops[2] = {Lo, Hi};	2047	SDValue Ops[2] = {Lo, Hi};
2045	return DAG.getMergeValues(Ops, DL);	2048	return DAG.getMergeValues(Ops, DL);
Lines 2050-2057 SDValue MipsTargetLowering::lowerShiftRightParts(S Link Here
2050	SDLoc DL(Op);	2053	SDLoc DL(Op);
2051	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);	2054	SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2052	SDValue Shamt = Op.getOperand(2);	2055	SDValue Shamt = Op.getOperand(2);
		2056	MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2053		2057
2054	// if shamt < 32:	2058	// if shamt < (VT.bits):
2055	// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))	2059	// lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2056	// if isSRA:	2060	// if isSRA:
2057	// hi = (sra hi, shamt)	2061	// hi = (sra hi, shamt)
Lines 2066-2086 SDValue MipsTargetLowering::lowerShiftRightParts(S Link Here
2066	// hi = 0	2070	// hi = 0
2067	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,	2071	SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2068	DAG.getConstant(-1, MVT::i32));	2072	DAG.getConstant(-1, MVT::i32));
2069	SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,	2073	SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2070	DAG.getConstant(1, MVT::i32));	2074	DAG.getConstant(1, VT));
2071	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);	2075	SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2072	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);	2076	SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2073	SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);	2077	SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2074	SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,	2078	SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2075	Hi, Shamt);	2079	DL, VT, Hi, Shamt);
2076	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,	2080	SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2077	DAG.getConstant(0x20, MVT::i32));	2081	DAG.getConstant(0x20, MVT::i32));
2078	SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,	2082	SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
2079	DAG.getConstant(31, MVT::i32));	2083	Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2080	Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);	2084	Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2081	Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,	2085	IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
2082	IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
2083	ShiftRightHi);
2084		2086
2085	SDValue Ops[2] = {Lo, Hi};	2087	SDValue Ops[2] = {Lo, Hi};
2086	return DAG.getMergeValues(Ops, DL);	2088	return DAG.getMergeValues(Ops, DL);




          (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
         "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");

  unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
  if (Subtarget->isGP64bit()) {
    SLTuOp = Mips::SLTu64;
    ADDuOp = Mips::DADDu;
  }

  SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
  SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
  EVT VT = LHS.getValueType();

  SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);

  if (Subtarget->isGP64bit()) {
    // On 64-bit targets, sltu produces an i64 but our backend currently says
    // that SLTu64 produces an i32. We need to fix this in the long run but for
    // now, just make the DAG type-correct by asserting the upper bits are zero.
    Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
                                   CurDAG->getTargetConstant(0, VT),
                                   SDValue(Carry, 0),
                                   CurDAG->getTargetConstant(Mips::sub_32, VT));
  }

  SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT,
                                            SDValue(Carry, 0), RHS);

  return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
                              SDValue(AddCarry, 0));
}


  case ISD::SUBE: {
    SDValue InFlag = Node->getOperand(2);
    unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
    Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
    return std::make_pair(true, Result);
  }


    if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
      break;
    SDValue InFlag = Node->getOperand(2);
    unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
    Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
    return std::make_pair(true, Result);
  }


Lines 122-127 MipsSETargetLowering::MipsSETargetLowering(const M Link Here

(-)lib/Target/Mips/MipsSEISelLowering.cpp (+4 lines)
122	setOperationAction(ISD::MUL, MVT::i64, Custom);	122	setOperationAction(ISD::MUL, MVT::i64, Custom);
123		123
124	if (Subtarget.isGP64bit()) {	124	if (Subtarget.isGP64bit()) {
		125	setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
		126	setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
125	setOperationAction(ISD::MULHS, MVT::i64, Custom);	127	setOperationAction(ISD::MULHS, MVT::i64, Custom);
126	setOperationAction(ISD::MULHU, MVT::i64, Custom);	128	setOperationAction(ISD::MULHU, MVT::i64, Custom);
127	setOperationAction(ISD::SDIVREM, MVT::i64, Custom);	129	setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
Lines 200-205 MipsSETargetLowering::MipsSETargetLowering(const M Link Here
200	if (Subtarget.hasMips64r6()) {	202	if (Subtarget.hasMips64r6()) {
201	// MIPS64r6 replaces the accumulator-based multiplies with a three register	203	// MIPS64r6 replaces the accumulator-based multiplies with a three register
202	// instruction	204	// instruction
		205	setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
		206	setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
203	setOperationAction(ISD::MUL, MVT::i64, Legal);	207	setOperationAction(ISD::MUL, MVT::i64, Legal);
204	setOperationAction(ISD::MULHS, MVT::i64, Legal);	208	setOperationAction(ISD::MULHS, MVT::i64, Legal);
205	setOperationAction(ISD::MULHU, MVT::i64, Legal);	209	setOperationAction(ISD::MULHU, MVT::i64, Legal);

Return to bug 197259

Lines 440-445 def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), Link Here

(-)lib/Target/Mips/Mips64InstrInfo.td (+10 lines)
440	// bswap MipsPattern	440	// bswap MipsPattern
441	def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;	441	def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
442		442
		443	// Carry pattern
		444	def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
		445	(DSUBu GPR64:$lhs, GPR64:$rhs)>;
		446	let AdditionalPredicates = [NotDSP] in {
		447	def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
		448	(DADDu GPR64:$lhs, GPR64:$rhs)>;
		449	def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
		450	(DADDiu GPR64:$lhs, imm:$imm)>;
		451	}
		452
443	//===----------------------------------------------------------------------===//	453	//===----------------------------------------------------------------------===//
444	// Instruction aliases	454	// Instruction aliases
445	//===----------------------------------------------------------------------===//	455	//===----------------------------------------------------------------------===//

Lines 236-248 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigne Link Here

(-)lib/Target/Mips/MipsSEISelDAGToDAG.cpp (-4 / +24 lines)
236	(Opc == ISD::SUBC \|\| Opc == ISD::SUBE)) &&	236	(Opc == ISD::SUBC \|\| Opc == ISD::SUBE)) &&
237	"(ADD\|SUB)E flag operand must come from (ADD\|SUB)C/E insn");	237	"(ADD\|SUB)E flag operand must come from (ADD\|SUB)C/E insn");
238		238
		239	unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
		240	if (Subtarget->isGP64bit()) {
		241	SLTuOp = Mips::SLTu64;
		242	ADDuOp = Mips::DADDu;
		243	}
		244
239	SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };	245	SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
240	SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);	246	SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
241	EVT VT = LHS.getValueType();	247	EVT VT = LHS.getValueType();
242		248
243	SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);	249	SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
244	SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,	250
		251	if (Subtarget->isGP64bit()) {
		252	// On 64-bit targets, sltu produces an i64 but our backend currently says
		253	// that SLTu64 produces an i32. We need to fix this in the long run but for
		254	// now, just make the DAG type-correct by asserting the upper bits are zero.
		255	Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
		256	CurDAG->getTargetConstant(0, VT),
		257	SDValue(Carry, 0),
		258	CurDAG->getTargetConstant(Mips::sub_32, VT));
		259	}
		260
		261	SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT,
245	SDValue(Carry, 0), RHS);	262	SDValue(Carry, 0), RHS);
		263
246	return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,	264	return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
247	SDValue(AddCarry, 0));	265	SDValue(AddCarry, 0));
248	}	266	}
Lines 641-647 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selec Link Here
641		659
642	case ISD::SUBE: {	660	case ISD::SUBE: {
643	SDValue InFlag = Node->getOperand(2);	661	SDValue InFlag = Node->getOperand(2);
644	Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);	662	unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
		663	Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
645	return std::make_pair(true, Result);	664	return std::make_pair(true, Result);
646	}	665	}
647		666
Lines 649-655 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selec Link Here
649	if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.	668	if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
650	break;	669	break;
651	SDValue InFlag = Node->getOperand(2);	670	SDValue InFlag = Node->getOperand(2);
652	Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);	671	unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
		672	Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
653	return std::make_pair(true, Result);	673	return std::make_pair(true, Result);
654	}	674	}
655		675