Attachment #152990 for bug #197535





	ifp = sc->rl_ifp;

	rxfilt = RL_RX_MAXDMA | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD;
	if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
		rxfilt |= RL_RXCFG_EARLYOFF;
	else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)
		rxfilt |= RL_RXCFG_EARLYOFFV2;
	if ((sc->rl_flags & RL_FLAG_FETCHMULTI) != 0)
		rxfilt |= RL_RXCFG_FETCHMULTI;
	else if ((sc->rl_flags & RL_FLAG_SINGLEFETCHV2) != 0)
		rxfilt |= RL_RXCFG_SINGLEFETCHV2;
	if ((sc->rl_flags & RL_FLAG_128INT) != 0)
		rxfilt |= RL_RXCFG_128INT;
	if ((sc->rl_flags & RL_FLAG_FIFOTHRESH) != 0)
		rxfilt |= RL_RXFIFO_NOTHRESH;

	if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
		if (ifp->if_flags & IFF_PROMISC)


	switch (hw_rev->rl_rev) {
	case RL_HWREV_8139CPLUS:
		sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD |
		    RL_FLAG_FIFOTHRESH;
		break;
	case RL_HWREV_8100E:
	case RL_HWREV_8101E:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER |
		   RL_FLAG_FIFOTHRESH;
		break;
	case RL_HWREV_8103E:
		sc->rl_flags |= RL_FLAG_MACSLEEP;
		/* FALLTHROUGH */
	case RL_HWREV_8102E:
	case RL_HWREV_8102EL:
	case RL_HWREV_8102EL_SPIN1:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 |
		    RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP |
		    RL_FLAG_AUTOPAD | RL_FLAG_FIFOTHRESH;
		break;
	case RL_HWREV_8402:
		sc->rl_flags |= RL_FLAG_CMDSTOP_WAIT_TXQ;
		/* FALLTHROUGH */
		    RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP;
		break;
	case RL_HWREV_8401E:
	case RL_HWREV_8105E:
	case RL_HWREV_8105E_SPIN1:

	case RL_HWREV_8106E:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD;
		break;
	case RL_HWREV_8402:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
		    RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD |
		    RL_FLAG_FIFOTHRESH;
		break;
	case RL_HWREV_8168B_SPIN1:
	case RL_HWREV_8168B_SPIN2:
		sc->rl_flags |= RL_FLAG_WOLRXENB | RL_FLAG_FIFOTHRESH;
		/* FALLTHROUGH */
	case RL_HWREV_8168B_SPIN3:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT;

	case RL_HWREV_8168CP:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK |
		    RL_FLAG_FETCHMULTI | RL_FLAG_128INT;
		break;
	case RL_HWREV_8168D:
	case RL_HWREV_8168E:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
		    RL_FLAG_WOL_MANLINK | RL_FLAG_128INT;
		break;
	case RL_HWREV_8168DP:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD |
		    RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL |
		    RL_FLAG_WOL_MANLINK | RL_FLAG_128INT | RL_FLAG_LGSENDV2;
		break;
	case RL_HWREV_8168E:
		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM |
		    RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT |
		    RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
		    RL_FLAG_WOL_MANLINK;
		break;
	case RL_HWREV_8168E_VL:
	case RL_HWREV_8168F:
		sc->rl_flags |= RL_FLAG_EARLYOFF;

		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
		    RL_FLAG_128INT | RL_FLAG_AUTOFIFO;
		break;
	case RL_HWREV_8168EP:
	case RL_HWREV_8168G:

		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
		    RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 |
		    RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK |
		    RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED |
		    RL_FLAG_SINGLEFETCHV2 | RL_FLAG_128INT | RL_FLAG_AUTOFIFO;
		break;
	case RL_HWREV_8168GU:
		if (pci_get_device(dev) == RT_DEVICEID_8101E) {

		sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR |
		    RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP |
		    RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ |
		    RL_FLAG_EARLYOFFV2 | RL_FLAG_RXDV_GATED |
		    RL_FLAG_SINGLEFETCHV2 | RL_FLAG_128INT | RL_FLAG_AUTOFIFO;
		break;
	case RL_HWREV_8169_8110SB:
	case RL_HWREV_8169_8110SBL:

	case RL_HWREV_8169:
	case RL_HWREV_8169S:
	case RL_HWREV_8110S:
		sc->rl_flags |= RL_FLAG_MACRESET | RL_FLAG_FIFOTHRESH;
		break;
	default:
		break;

	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
	/*
	 * Don't enable TSO by default.  It is known to generate
	 * corrupted TCP segments (bad TCP options) under certain
	 * circumstances.
	 */
	ifp->if_hwassist &= ~CSUM_TSO;

	vlanctl = 0;
	csum_flags = 0;
	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
		if ((sc->rl_flags & RL_FLAG_LGSENDV2) != 0) {
			vlanctl |= RL_TDESC_CMD_LGSENDV2 |
			    ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
			    RL_TDESC_CMD_MSSVALV2_SHIFT);
		} else if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
			csum_flags |= RL_TDESC_CMD_LGSEND;
			vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
			    RL_TDESC_CMD_MSSVALV2_SHIFT);

		}
	} else {
		/*
		 * Unconditionally enable IP checksuming if TCP or UDP
		 * checksum is required. Otherwise, TCP/UDP checksuming
		 * doesn't take effect.
		 */
		if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
			if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {

	desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF);

	/*
	 * Ensure that the map for this transmission is placed at the array
	 * index of the last descriptor in this chain (swap last and first
	 * dmamap).
	 */
	txd_last = &sc->rl_ldata.rl_tx_desc[ei];
	map = txd->tx_dmamap;

	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
	    RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));

	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0) {
		CSR_WRITE_1(sc, RL_PPSW, CSR_READ_1(sc, RL_PPSW) & ~0x08);
		DELAY(2000);
	}

	/*
	 * Enable transmit and receive.

	/*
	 * Set the initial TX configuration.
	 */
	reg = RL_TXCFG_CONFIG;
	if (sc->rl_testmode) {
		if (sc->rl_type == RL_8169)
			reg |= RL_LOOPTEST_ON;
			    RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
		else
			reg |= RL_LOOPTEST_ON_CPLUS;
	}
	if ((sc->rl_flags & RL_FLAG_AUTOFIFO) != 0)
		reg |= RL_TXCFG_AUTOFIFO;
	CSR_WRITE_4(sc, RL_TXCFG, reg);

	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT);

	/*
	 * Set the initial RX configuration.

	    ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI |
	    RL_RXCFG_RX_BROAD));

	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0) {
		CSR_WRITE_1(sc, RL_PPSW, CSR_READ_1(sc, RL_PPSW) | 0x08);
		DELAY(2000);
	}

	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
		for (i = RL_TIMEOUT; i > 0; i--) {
			if ((CSR_READ_1(sc, sc->rl_txstart) &




#define	RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
#define	RL_INTRMOD		0x00E2	/* 16 bits */
#define	RL_MISC			0x00F0
#define	RL_PPSW			0x00F2

/*
 * TX config register bits
 */
#define	RL_TXCFG_CLRABRT	0x00000001	/* retransmit aborted pkt */
#define	RL_TXCFG_AUTOFIFO	0x00000080	/* 8168E-VL or higher */
#define	RL_TXCFG_MAXDMA		0x00000700	/* max DMA burst size */
#define	RL_TXCFG_QUEUE_EMPTY	0x00000800	/* 8168E-VL or higher */
#define	RL_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */

#define	RL_RXCFG_RX_BROAD	0x00000008	/* accept all broadcast */
#define	RL_RXCFG_RX_RUNT	0x00000010
#define	RL_RXCFG_RX_ERRPKT	0x00000020
#define	RL_RXCFG_9356SEL	0x00000040
#define	RL_RXCFG_WRAP		0x00000080
#define	RL_RXCFG_EARLYOFFV2	0x00000800
#define	RL_RXCFG_MAXDMA		0x00000700
#define	RL_RXCFG_BUFSZ		0x00001800
#define	RL_RXCFG_HALFREFETCH	0x00002000
#define	RL_RXCFG_EARLYOFF	0x00003800
#define	RL_RXCFG_FETCHMULTI	0x00004000
#define	RL_RXCFG_SINGLEFETCHV2	0x00004000
#define	RL_RXCFG_128INT		0x00008000
#define	RL_RXCFG_FIFOTHRESH	0x0000E000
#define	RL_RXCFG_EARLYTHRESH	0x07000000


#define	RL_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
#define	RL_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
#define	RL_TDESC_CMD_MSSVAL_SHIFT	16	/* Large send MSS value shift */
#define	RL_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enable */
#define	RL_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
#define	RL_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
#define	RL_TDESC_CMD_EOR	0x40000000	/* end of ring marker */


#define	RL_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
#define	RL_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
/* 8168DP */
#define	RL_TDESC_CMD_LGSENDV2	0x00010000
/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
#define	RL_TDESC_CMD_UDPCSUMV2	0x80000000
#define	RL_TDESC_CMD_TCPCSUMV2	0x40000000

#define	RL_FLAG_EARLYOFF	0x00020000
#define	RL_FLAG_EARLYOFFV2	0x00040000
#define	RL_FLAG_RXDV_GATED	0x00080000
#define	RL_FLAG_FETCHMULTI	0x00100000
#define	RL_FLAG_SINGLEFETCHV2	0x00200000
#define	RL_FLAG_128INT		0x00400000
#define	RL_FLAG_FIFOTHRESH	0x00800000
#define	RL_FLAG_AUTOFIFO	0x01000000
#define	RL_FLAG_LGSENDV2	0x02000000
#define	RL_FLAG_PCIE		0x40000000
#define	RL_FLAG_LINK		0x80000000
};

Return to bug 197535

Lines 655-665 re_set_rxmode(struct rl_softc *sc) Link Here

(-)re/if_re.c (-47 / +64 lines)
655		655
656	ifp = sc->rl_ifp;	656	ifp = sc->rl_ifp;
657		657
658	rxfilt = RL_RXCFG_CONFIG \| RL_RXCFG_RX_INDIV \| RL_RXCFG_RX_BROAD;	658	rxfilt = RL_RX_MAXDMA \| RL_RXCFG_RX_INDIV \| RL_RXCFG_RX_BROAD;
659	if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)	659	if ((sc->rl_flags & RL_FLAG_EARLYOFF) != 0)
660	rxfilt \|= RL_RXCFG_EARLYOFF;	660	rxfilt \|= RL_RXCFG_EARLYOFF;
661	else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)	661	else if ((sc->rl_flags & RL_FLAG_EARLYOFFV2) != 0)
662	rxfilt \|= RL_RXCFG_EARLYOFFV2;	662	rxfilt \|= RL_RXCFG_EARLYOFFV2;
		663	if ((sc->rl_flags & RL_FLAG_FETCHMULTI) != 0)
		664	rxfilt \|= RL_RXCFG_FETCHMULTI;
		665	else if ((sc->rl_flags & RL_FLAG_SINGLEFETCHV2) != 0)
		666	rxfilt \|= RL_RXCFG_SINGLEFETCHV2;
		667	if ((sc->rl_flags & RL_FLAG_128INT) != 0)
		668	rxfilt \|= RL_RXCFG_128INT;
		669	if ((sc->rl_flags & RL_FLAG_FIFOTHRESH) != 0)
		670	rxfilt \|= RL_RXFIFO_NOTHRESH;
663		671
664	if (ifp->if_flags & (IFF_ALLMULTI \| IFF_PROMISC)) {	672	if (ifp->if_flags & (IFF_ALLMULTI \| IFF_PROMISC)) {
665	if (ifp->if_flags & IFF_PROMISC)	673	if (ifp->if_flags & IFF_PROMISC)
Lines 1404-1427 re_attach(device_t dev) Link Here
1404		1412
1405	switch (hw_rev->rl_rev) {	1413	switch (hw_rev->rl_rev) {
1406	case RL_HWREV_8139CPLUS:	1414	case RL_HWREV_8139CPLUS:
1407	sc->rl_flags \|= RL_FLAG_FASTETHER \| RL_FLAG_AUTOPAD;	1415	sc->rl_flags \|= RL_FLAG_FASTETHER \| RL_FLAG_AUTOPAD \|
		1416	RL_FLAG_FIFOTHRESH;
1408	break;	1417	break;
1409	case RL_HWREV_8100E:	1418	case RL_HWREV_8100E:
1410	case RL_HWREV_8101E:	1419	case RL_HWREV_8101E:
1411	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_FASTETHER;	1420	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_FASTETHER \|
		1421	RL_FLAG_FIFOTHRESH;
1412	break;	1422	break;
		1423	case RL_HWREV_8103E:
		1424	sc->rl_flags \|= RL_FLAG_MACSLEEP;
		1425	/* FALLTHROUGH */
1413	case RL_HWREV_8102E:	1426	case RL_HWREV_8102E:
1414	case RL_HWREV_8102EL:	1427	case RL_HWREV_8102EL:
1415	case RL_HWREV_8102EL_SPIN1:	1428	case RL_HWREV_8102EL_SPIN1:
1416	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \| RL_FLAG_DESCV2 \|	1429	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \| RL_FLAG_DESCV2 \|
1417	RL_FLAG_MACSTAT \| RL_FLAG_FASTETHER \| RL_FLAG_CMDSTOP \|	1430	RL_FLAG_MACSTAT \| RL_FLAG_FASTETHER \| RL_FLAG_CMDSTOP \|
1418	RL_FLAG_AUTOPAD;	1431	RL_FLAG_AUTOPAD \| RL_FLAG_FIFOTHRESH;
1419	break;	1432	break;
1420	case RL_HWREV_8103E:	1433	case RL_HWREV_8402:
1421	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \| RL_FLAG_DESCV2 \|	1434	sc->rl_flags \|= RL_FLAG_CMDSTOP_WAIT_TXQ;
1422	RL_FLAG_MACSTAT \| RL_FLAG_FASTETHER \| RL_FLAG_CMDSTOP \|	1435	/* FALLTHROUGH */
1423	RL_FLAG_AUTOPAD \| RL_FLAG_MACSLEEP;
1424	break;
1425	case RL_HWREV_8401E:	1436	case RL_HWREV_8401E:
1426	case RL_HWREV_8105E:	1437	case RL_HWREV_8105E:
1427	case RL_HWREV_8105E_SPIN1:	1438	case RL_HWREV_8105E_SPIN1:
Lines 1428-1444 re_attach(device_t dev) Link Here
1428	case RL_HWREV_8106E:	1439	case RL_HWREV_8106E:
1429	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PHYWAKE_PM \|	1440	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PHYWAKE_PM \|
1430	RL_FLAG_PAR \| RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \|	1441	RL_FLAG_PAR \| RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \|
1431	RL_FLAG_FASTETHER \| RL_FLAG_CMDSTOP \| RL_FLAG_AUTOPAD;
1432	break;
1433	case RL_HWREV_8402:
1434	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PHYWAKE_PM \|
1435	RL_FLAG_PAR \| RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \|
1436	RL_FLAG_FASTETHER \| RL_FLAG_CMDSTOP \| RL_FLAG_AUTOPAD \|	1442	RL_FLAG_FASTETHER \| RL_FLAG_CMDSTOP \| RL_FLAG_AUTOPAD \|
1437	RL_FLAG_CMDSTOP_WAIT_TXQ;	1443	RL_FLAG_FIFOTHRESH;
1438	break;	1444	break;
1439	case RL_HWREV_8168B_SPIN1:	1445	case RL_HWREV_8168B_SPIN1:
1440	case RL_HWREV_8168B_SPIN2:	1446	case RL_HWREV_8168B_SPIN2:
1441	sc->rl_flags \|= RL_FLAG_WOLRXENB;	1447	sc->rl_flags \|= RL_FLAG_WOLRXENB \| RL_FLAG_FIFOTHRESH;
1442	/* FALLTHROUGH */	1448	/* FALLTHROUGH */
1443	case RL_HWREV_8168B_SPIN3:	1449	case RL_HWREV_8168B_SPIN3:
1444	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_MACSTAT;	1450	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_MACSTAT;
Lines 1453-1477 re_attach(device_t dev) Link Here
1453	case RL_HWREV_8168CP:	1459	case RL_HWREV_8168CP:
1454	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|	1460	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|
1455	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|	1461	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|
1456	RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \| RL_FLAG_WOL_MANLINK;	1462	RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \| RL_FLAG_WOL_MANLINK \|
		1463	RL_FLAG_FETCHMULTI \| RL_FLAG_128INT;
1457	break;	1464	break;
1458	case RL_HWREV_8168D:	1465	case RL_HWREV_8168D:
		1466	case RL_HWREV_8168E:
1459	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PHYWAKE_PM \|	1467	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PHYWAKE_PM \|
1460	RL_FLAG_PAR \| RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \|	1468	RL_FLAG_PAR \| RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \|
1461	RL_FLAG_CMDSTOP \| RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|	1469	RL_FLAG_CMDSTOP \| RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|
1462	RL_FLAG_WOL_MANLINK;	1470	RL_FLAG_WOL_MANLINK \| RL_FLAG_128INT;
1463	break;	1471	break;
1464	case RL_HWREV_8168DP:	1472	case RL_HWREV_8168DP:
1465	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|	1473	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|
1466	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_AUTOPAD \|	1474	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_AUTOPAD \|
1467	RL_FLAG_JUMBOV2 \| RL_FLAG_WAIT_TXPOLL \| RL_FLAG_WOL_MANLINK;	1475	RL_FLAG_JUMBOV2 \| RL_FLAG_WAIT_TXPOLL \|
		1476	RL_FLAG_WOL_MANLINK \| RL_FLAG_128INT \| RL_FLAG_LGSENDV2;
1468	break;	1477	break;
1469	case RL_HWREV_8168E:
1470	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PHYWAKE_PM \|
1471	RL_FLAG_PAR \| RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \|
1472	RL_FLAG_CMDSTOP \| RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|
1473	RL_FLAG_WOL_MANLINK;
1474	break;
1475	case RL_HWREV_8168E_VL:	1478	case RL_HWREV_8168E_VL:
1476	case RL_HWREV_8168F:	1479	case RL_HWREV_8168F:
1477	sc->rl_flags \|= RL_FLAG_EARLYOFF;	1480	sc->rl_flags \|= RL_FLAG_EARLYOFF;
Lines 1480-1486 re_attach(device_t dev) Link Here
1480	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|	1483	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|
1481	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|	1484	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|
1482	RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|	1485	RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|
1483	RL_FLAG_CMDSTOP_WAIT_TXQ \| RL_FLAG_WOL_MANLINK;	1486	RL_FLAG_CMDSTOP_WAIT_TXQ \| RL_FLAG_WOL_MANLINK \|
		1487	RL_FLAG_128INT \| RL_FLAG_AUTOFIFO;
1484	break;	1488	break;
1485	case RL_HWREV_8168EP:	1489	case RL_HWREV_8168EP:
1486	case RL_HWREV_8168G:	1490	case RL_HWREV_8168G:
Lines 1489-1495 re_attach(device_t dev) Link Here
1489	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|	1493	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|
1490	RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|	1494	RL_FLAG_AUTOPAD \| RL_FLAG_JUMBOV2 \|
1491	RL_FLAG_CMDSTOP_WAIT_TXQ \| RL_FLAG_WOL_MANLINK \|	1495	RL_FLAG_CMDSTOP_WAIT_TXQ \| RL_FLAG_WOL_MANLINK \|
1492	RL_FLAG_EARLYOFFV2 \| RL_FLAG_RXDV_GATED;	1496	RL_FLAG_EARLYOFFV2 \| RL_FLAG_RXDV_GATED \|
		1497	RL_FLAG_SINGLEFETCHV2 \| RL_FLAG_128INT \| RL_FLAG_AUTOFIFO;
1493	break;	1498	break;
1494	case RL_HWREV_8168GU:	1499	case RL_HWREV_8168GU:
1495	if (pci_get_device(dev) == RT_DEVICEID_8101E) {	1500	if (pci_get_device(dev) == RT_DEVICEID_8101E) {
Lines 1501-1507 re_attach(device_t dev) Link Here
1501	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|	1506	sc->rl_flags \|= RL_FLAG_PHYWAKE \| RL_FLAG_PAR \|
1502	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|	1507	RL_FLAG_DESCV2 \| RL_FLAG_MACSTAT \| RL_FLAG_CMDSTOP \|
1503	RL_FLAG_AUTOPAD \| RL_FLAG_CMDSTOP_WAIT_TXQ \|	1508	RL_FLAG_AUTOPAD \| RL_FLAG_CMDSTOP_WAIT_TXQ \|
1504	RL_FLAG_EARLYOFFV2 \| RL_FLAG_RXDV_GATED;	1509	RL_FLAG_EARLYOFFV2 \| RL_FLAG_RXDV_GATED \|
		1510	RL_FLAG_SINGLEFETCHV2 \| RL_FLAG_128INT \| RL_FLAG_AUTOFIFO;
1505	break;	1511	break;
1506	case RL_HWREV_8169_8110SB:	1512	case RL_HWREV_8169_8110SB:
1507	case RL_HWREV_8169_8110SBL:	1513	case RL_HWREV_8169_8110SBL:
Lines 1512-1518 re_attach(device_t dev) Link Here
1512	case RL_HWREV_8169:	1518	case RL_HWREV_8169:
1513	case RL_HWREV_8169S:	1519	case RL_HWREV_8169S:
1514	case RL_HWREV_8110S:	1520	case RL_HWREV_8110S:
1515	sc->rl_flags \|= RL_FLAG_MACRESET;	1521	sc->rl_flags \|= RL_FLAG_MACRESET \| RL_FLAG_FIFOTHRESH;
1516	break;	1522	break;
1517	default:	1523	default:
1518	break;	1524	break;
Lines 1674-1680 re_attach(device_t dev) Link Here
1674	ifp->if_capenable &= ~(IFCAP_WOL_UCAST \| IFCAP_WOL_MCAST);	1680	ifp->if_capenable &= ~(IFCAP_WOL_UCAST \| IFCAP_WOL_MCAST);
1675	/*	1681	/*
1676	* Don't enable TSO by default. It is known to generate	1682	* Don't enable TSO by default. It is known to generate
1677	* corrupted TCP segments(bad TCP options) under certain	1683	* corrupted TCP segments (bad TCP options) under certain
1678	* circumstances.	1684	* circumstances.
1679	*/	1685	*/
1680	ifp->if_hwassist &= ~CSUM_TSO;	1686	ifp->if_hwassist &= ~CSUM_TSO;
Lines 2813-2819 re_encap(struct rl_softc sc, struct mbuf *m_head Link Here
2813	vlanctl = 0;	2819	vlanctl = 0;
2814	csum_flags = 0;	2820	csum_flags = 0;
2815	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {	2821	if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2816	if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {	2822	if ((sc->rl_flags & RL_FLAG_LGSENDV2) != 0) {
		2823	vlanctl \|= RL_TDESC_CMD_LGSENDV2 \|
		2824	((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
		2825	RL_TDESC_CMD_MSSVALV2_SHIFT);
		2826	} else if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) {
2817	csum_flags \|= RL_TDESC_CMD_LGSEND;	2827	csum_flags \|= RL_TDESC_CMD_LGSEND;
2818	vlanctl \|= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<	2828	vlanctl \|= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz <<
2819	RL_TDESC_CMD_MSSVALV2_SHIFT);	2829	RL_TDESC_CMD_MSSVALV2_SHIFT);
Lines 2824-2832 re_encap(struct rl_softc sc, struct mbuf *m_head Link Here
2824	}	2834	}
2825	} else {	2835	} else {
2826	/*	2836	/*
2827	* Unconditionally enable IP checksum if TCP or UDP	2837	* Unconditionally enable IP checksuming if TCP or UDP
2828	* checksum is required. Otherwise, TCP/UDP checksum	2838	* checksum is required. Otherwise, TCP/UDP checksuming
2829	* doesn't make effects.	2839	* doesn't take effect.
2830	*/	2840	*/
2831	if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {	2841	if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) {
2832	if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {	2842	if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) {
Lines 2885-2893 re_encap(struct rl_softc sc, struct mbuf *m_head Link Here
2885	desc->rl_cmdstat \|= htole32(RL_TDESC_CMD_OWN \| RL_TDESC_CMD_SOF);	2895	desc->rl_cmdstat \|= htole32(RL_TDESC_CMD_OWN \| RL_TDESC_CMD_SOF);
2886		2896
2887	/*	2897	/*
2888	* Insure that the map for this transmission	2898	* Ensure that the map for this transmission is placed at the array
2889	* is placed at the array index of the last descriptor	2899	* index of the last descriptor in this chain (swap last and first
2890	* in this chain. (Swap last and first dmamaps.)	2900	* dmamap).
2891	*/	2901	*/
2892	txd_last = &sc->rl_ldata.rl_tx_desc[ei];	2902	txd_last = &sc->rl_ldata.rl_tx_desc[ei];
2893	map = txd->tx_dmamap;	2903	map = txd->tx_dmamap;
Lines 3191-3199 re_init_locked(struct rl_softc *sc) Link Here
3191	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,	3201	CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
3192	RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));	3202	RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
3193		3203
3194	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0)	3204	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0) {
3195	CSR_WRITE_4(sc, RL_MISC, CSR_READ_4(sc, RL_MISC) &	3205	CSR_WRITE_1(sc, RL_PPSW, CSR_READ_1(sc, RL_PPSW) & ~0x08);
3196	~0x00080000);	3206	DELAY(2000);
		3207	}
3197		3208
3198	/*	3209	/*
3199	* Enable transmit and receive.	3210	* Enable transmit and receive.
Lines 3203-3219 re_init_locked(struct rl_softc *sc) Link Here
3203	/*	3214	/*
3204	* Set the initial TX configuration.	3215	* Set the initial TX configuration.
3205	*/	3216	*/
		3217	reg = RL_TXCFG_CONFIG;
3206	if (sc->rl_testmode) {	3218	if (sc->rl_testmode) {
3207	if (sc->rl_type == RL_8169)	3219	if (sc->rl_type == RL_8169)
3208	CSR_WRITE_4(sc, RL_TXCFG,	3220	reg \|= RL_LOOPTEST_ON;
3209	RL_TXCFG_CONFIG\|RL_LOOPTEST_ON);
3210	else	3221	else
3211	CSR_WRITE_4(sc, RL_TXCFG,	3222	reg \|= RL_LOOPTEST_ON_CPLUS;
3212	RL_TXCFG_CONFIG\|RL_LOOPTEST_ON_CPLUS);	3223	}
3213	} else	3224	if ((sc->rl_flags & RL_FLAG_AUTOFIFO) != 0)
3214	CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);	3225	reg \|= RL_TXCFG_AUTOFIFO;
		3226	CSR_WRITE_4(sc, RL_TXCFG, reg);
3215		3227
3216	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);	3228	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, RL_EARLYTXTHRESH_CNT);
3217		3229
3218	/*	3230	/*
3219	* Set the initial RX configuration.	3231	* Set the initial RX configuration.
Lines 3584-3589 re_stop(struct rl_softc *sc) Link Here
3584	~(RL_RXCFG_RX_ALLPHYS \| RL_RXCFG_RX_INDIV \| RL_RXCFG_RX_MULTI \|	3596	~(RL_RXCFG_RX_ALLPHYS \| RL_RXCFG_RX_INDIV \| RL_RXCFG_RX_MULTI \|
3585	RL_RXCFG_RX_BROAD));	3597	RL_RXCFG_RX_BROAD));
3586		3598
		3599	if ((sc->rl_flags & RL_FLAG_RXDV_GATED) != 0) {
		3600	CSR_WRITE_1(sc, RL_PPSW, CSR_READ_1(sc, RL_PPSW) \| 0x08);
		3601	DELAY(2000);
		3602	}
		3603
3587	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {	3604	if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) {
3588	for (i = RL_TIMEOUT; i > 0; i--) {	3605	for (i = RL_TIMEOUT; i > 0; i--) {
3589	if ((CSR_READ_1(sc, sc->rl_txstart) &	3606	if ((CSR_READ_1(sc, sc->rl_txstart) &

Lines 146-156 Link Here

(-)rl/if_rlreg.h (-1 / +16 lines)
146	#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */	146	#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
147	#define RL_INTRMOD 0x00E2 /* 16 bits */	147	#define RL_INTRMOD 0x00E2 /* 16 bits */
148	#define RL_MISC 0x00F0	148	#define RL_MISC 0x00F0
		149	#define RL_PPSW 0x00F2
149		150
150	/*	151	/*
151	* TX config register bits	152	* TX config register bits
152	*/	153	*/
153	#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */	154	#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
		155	#define RL_TXCFG_AUTOFIFO 0x00000080 /* 8168E-VL or higher */
154	#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */	156	#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
155	#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */	157	#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */
156	#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */	158	#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
Lines 286-296 Link Here
286	#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */	288	#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
287	#define RL_RXCFG_RX_RUNT 0x00000010	289	#define RL_RXCFG_RX_RUNT 0x00000010
288	#define RL_RXCFG_RX_ERRPKT 0x00000020	290	#define RL_RXCFG_RX_ERRPKT 0x00000020
		291	#define RL_RXCFG_9356SEL 0x00000040
289	#define RL_RXCFG_WRAP 0x00000080	292	#define RL_RXCFG_WRAP 0x00000080
290	#define RL_RXCFG_EARLYOFFV2 0x00000800	293	#define RL_RXCFG_EARLYOFFV2 0x00000800
291	#define RL_RXCFG_MAXDMA 0x00000700	294	#define RL_RXCFG_MAXDMA 0x00000700
292	#define RL_RXCFG_BUFSZ 0x00001800	295	#define RL_RXCFG_BUFSZ 0x00001800
		296	#define RL_RXCFG_HALFREFETCH 0x00002000
293	#define RL_RXCFG_EARLYOFF 0x00003800	297	#define RL_RXCFG_EARLYOFF 0x00003800
		298	#define RL_RXCFG_FETCHMULTI 0x00004000
		299	#define RL_RXCFG_SINGLEFETCHV2 0x00004000
		300	#define RL_RXCFG_128INT 0x00008000
294	#define RL_RXCFG_FIFOTHRESH 0x0000E000	301	#define RL_RXCFG_FIFOTHRESH 0x0000E000
295	#define RL_RXCFG_EARLYTHRESH 0x07000000	302	#define RL_RXCFG_EARLYTHRESH 0x07000000
296		303
Lines 656-662 struct rl_desc { Link Here
656	#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */	663	#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
657	#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */	664	#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
658	#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */	665	#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
659	#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */	666	#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enable */
660	#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */	667	#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
661	#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */	668	#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
662	#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */	669	#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
Lines 664-669 struct rl_desc { Link Here
664		671
665	#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */	672	#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
666	#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */	673	#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
		674	/* 8168DP */
		675	#define RL_TDESC_CMD_LGSENDV2 0x00010000
667	/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */	676	/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */
668	#define RL_TDESC_CMD_UDPCSUMV2 0x80000000	677	#define RL_TDESC_CMD_UDPCSUMV2 0x80000000
669	#define RL_TDESC_CMD_TCPCSUMV2 0x40000000	678	#define RL_TDESC_CMD_TCPCSUMV2 0x40000000
Lines 932-937 struct rl_softc { Link Here
932	#define RL_FLAG_EARLYOFF 0x00020000	941	#define RL_FLAG_EARLYOFF 0x00020000
933	#define RL_FLAG_EARLYOFFV2 0x00040000	942	#define RL_FLAG_EARLYOFFV2 0x00040000
934	#define RL_FLAG_RXDV_GATED 0x00080000	943	#define RL_FLAG_RXDV_GATED 0x00080000
		944	#define RL_FLAG_FETCHMULTI 0x00100000
		945	#define RL_FLAG_SINGLEFETCHV2 0x00200000
		946	#define RL_FLAG_128INT 0x00400000
		947	#define RL_FLAG_FIFOTHRESH 0x00800000
		948	#define RL_FLAG_AUTOFIFO 0x01000000
		949	#define RL_FLAG_LGSENDV2 0x02000000
935	#define RL_FLAG_PCIE 0x40000000	950	#define RL_FLAG_PCIE 0x40000000
936	#define RL_FLAG_LINK 0x80000000	951	#define RL_FLAG_LINK 0x80000000
937	};	952	};