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Lines 1-6
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| 1 |
/*- |
1 |
/*- |
| 2 |
* Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. |
2 |
* Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. |
| 3 |
* Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. |
3 |
* Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. |
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|
4 |
* Copyright (c) 2015 Emmanuel Vadot <manu@megadrive.org>. |
| 4 |
* All rights reserved. |
5 |
* All rights reserved. |
| 5 |
* |
6 |
* |
| 6 |
* Redistribution and use in source and binary forms, with or without |
7 |
* Redistribution and use in source and binary forms, with or without |
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Lines 74-79
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| 74 |
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75 |
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| 75 |
#include "iicbus_if.h" |
76 |
#include "iicbus_if.h" |
| 76 |
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77 |
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|
78 |
#define BUFSIZE 1024 |
| 79 |
|
| 77 |
/** |
80 |
/** |
| 78 |
* I2C device driver context, a pointer to this is stored in the device |
81 |
* I2C device driver context, a pointer to this is stored in the device |
| 79 |
* driver structure. |
82 |
* driver structure. |
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Lines 91-101
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| 91 |
struct mtx sc_mtx; |
94 |
struct mtx sc_mtx; |
| 92 |
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95 |
|
| 93 |
struct iic_msg* sc_buffer; |
96 |
struct iic_msg* sc_buffer; |
|
|
97 |
uint8_t sc_buffer_buf[bufsize]; |
| 94 |
int sc_bus_inuse; |
98 |
int sc_bus_inuse; |
| 95 |
int sc_buffer_pos; |
99 |
int sc_buffer_pos; |
|
|
100 |
uint16_t sc_buffer_flags; |
| 96 |
int sc_error; |
101 |
int sc_error; |
| 97 |
int sc_fifo_trsh; |
102 |
int sc_fifo_trsh; |
| 98 |
int sc_timeout; |
103 |
int sc_timeout; |
|
|
104 |
uint8_t sc_slave_addr; |
| 99 |
|
105 |
|
| 100 |
uint16_t sc_con_reg; |
106 |
uint16_t sc_con_reg; |
| 101 |
uint16_t sc_rev; |
107 |
uint16_t sc_rev; |
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Lines 158-163
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| 158 |
#define ti_i2c_dbg(_sc, fmt, args...) |
164 |
#define ti_i2c_dbg(_sc, fmt, args...) |
| 159 |
#endif |
165 |
#endif |
| 160 |
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166 |
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|
167 |
static int ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed); |
| 168 |
|
| 169 |
|
| 161 |
/** |
170 |
/** |
| 162 |
* ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers |
171 |
* ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers |
| 163 |
* @sc: I2C device context |
172 |
* @sc: I2C device context |
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Lines 200-237
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| 200 |
ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) |
209 |
ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) |
| 201 |
{ |
210 |
{ |
| 202 |
int amount, done, i; |
211 |
int amount, done, i; |
|
|
212 |
uint16_t fifo_size; |
| 203 |
|
213 |
|
| 204 |
done = 0; |
214 |
done = 0; |
| 205 |
amount = 0; |
215 |
amount = 0; |
| 206 |
/* Check for the error conditions. */ |
|
|
| 207 |
if (status & I2C_STAT_NACK) { |
| 208 |
/* No ACK from slave. */ |
| 209 |
ti_i2c_dbg(sc, "NACK\n"); |
| 210 |
ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); |
| 211 |
sc->sc_error = ENXIO; |
| 212 |
} else if (status & I2C_STAT_AL) { |
| 213 |
/* Arbitration lost. */ |
| 214 |
ti_i2c_dbg(sc, "Arbitration lost\n"); |
| 215 |
ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); |
| 216 |
sc->sc_error = ENXIO; |
| 217 |
} |
| 218 |
|
216 |
|
| 219 |
/* Check if we have finished. */ |
|
|
| 220 |
if (status & I2C_STAT_ARDY) { |
| 221 |
/* Register access ready - transaction complete basically. */ |
| 222 |
ti_i2c_dbg(sc, "ARDY transaction complete\n"); |
| 223 |
if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { |
| 224 |
ti_i2c_write_2(sc, I2C_REG_CON, |
| 225 |
sc->sc_con_reg | I2C_CON_STP); |
| 226 |
} |
| 227 |
ti_i2c_write_2(sc, I2C_REG_STATUS, |
| 228 |
I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | |
| 229 |
I2C_STAT_XDR | I2C_STAT_XRDY); |
| 230 |
return (1); |
| 231 |
} |
| 232 |
|
| 233 |
if (sc->sc_buffer->flags & IIC_M_RD) { |
217 |
if (sc->sc_buffer->flags & IIC_M_RD) { |
| 234 |
/* Read some data. */ |
218 |
/* Read some data. */ |
|
|
219 |
|
| 235 |
if (status & I2C_STAT_RDR) { |
220 |
if (status & I2C_STAT_RDR) { |
| 236 |
/* |
221 |
/* |
| 237 |
* Receive draining interrupt - last data received. |
222 |
* Receive draining interrupt - last data received. |
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Lines 238-263
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| 238 |
* The set FIFO threshold wont be reached to trigger |
223 |
* The set FIFO threshold wont be reached to trigger |
| 239 |
* RRDY. |
224 |
* RRDY. |
| 240 |
*/ |
225 |
*/ |
| 241 |
ti_i2c_dbg(sc, "Receive draining interrupt\n"); |
|
|
| 242 |
|
226 |
|
| 243 |
/* |
227 |
fifo_size = (ti_i2c_read_2(sc, I2C_REG_BUFSTAT) & I2C_BUFSTAT_RXSTAT_MASK) >> I2C_BUFSTAT_RXSTAT_SHIFT; |
| 244 |
* Drain the FIFO. Read the pending data in the FIFO. |
228 |
amount = min(fifo_size, sc->sc_buffer->len - sc->sc_buffer_pos); |
| 245 |
*/ |
229 |
ti_i2c_dbg(sc, "Receive draining interrupt, draining %d bytes\n", amount); |
| 246 |
amount = sc->sc_buffer->len - sc->sc_buffer_pos; |
|
|
| 247 |
} else if (status & I2C_STAT_RRDY) { |
230 |
} else if (status & I2C_STAT_RRDY) { |
| 248 |
/* |
231 |
/* |
| 249 |
* Receive data ready interrupt - FIFO has reached the |
232 |
* Receive data ready interrupt - FIFO has reached the |
| 250 |
* set threshold. |
233 |
* set threshold. |
| 251 |
*/ |
234 |
*/ |
| 252 |
ti_i2c_dbg(sc, "Receive data ready interrupt\n"); |
|
|
| 253 |
|
| 254 |
amount = min(sc->sc_fifo_trsh, |
235 |
amount = min(sc->sc_fifo_trsh, |
| 255 |
sc->sc_buffer->len - sc->sc_buffer_pos); |
236 |
sc->sc_buffer->len - sc->sc_buffer_pos); |
|
|
237 |
ti_i2c_dbg(sc, "Receive data ready interrupt, reading %d bytes\n", amount); |
| 256 |
} |
238 |
} |
| 257 |
|
239 |
|
| 258 |
/* Read the bytes from the fifo. */ |
240 |
/* Read the bytes from the fifo. */ |
| 259 |
for (i = 0; i < amount; i++) |
241 |
for (i = 0; i < amount; i++) |
| 260 |
sc->sc_buffer->buf[sc->sc_buffer_pos++] = |
242 |
sc->sc_buffer->buf[sc->sc_buffer_pos++] = |
| 261 |
(uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); |
243 |
(uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); |
| 262 |
|
244 |
|
| 263 |
if (status & I2C_STAT_RDR) |
245 |
if (status & I2C_STAT_RDR) |
|
Lines 265-285
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| 265 |
if (status & I2C_STAT_RRDY) |
247 |
if (status & I2C_STAT_RRDY) |
| 266 |
ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); |
248 |
ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); |
| 267 |
|
249 |
|
|
|
250 |
ti_i2c_dbg(sc, "%d bytes to read\n", ti_i2c_read_2(sc, I2C_REG_CNT)); |
| 251 |
|
| 268 |
} else { |
252 |
} else { |
| 269 |
/* Write some data. */ |
253 |
/* Write some data. */ |
|
|
254 |
|
| 270 |
if (status & I2C_STAT_XDR) { |
255 |
if (status & I2C_STAT_XDR) { |
| 271 |
/* |
256 |
/* |
| 272 |
* Transmit draining interrupt - FIFO level is below |
257 |
* Transmit draining interrupt - FIFO level is below |
| 273 |
* the set threshold and the amount of data still to |
258 |
* the set threshold and the amount of data still to |
| 274 |
* be transferred wont reach the set FIFO threshold. |
259 |
* be transferred wont reach the set FIFO threshold. |
| 275 |
*/ |
|
|
| 276 |
ti_i2c_dbg(sc, "Transmit draining interrupt\n"); |
| 277 |
|
| 278 |
/* |
| 279 |
* Drain the TX data. Write the pending data in the |
260 |
* Drain the TX data. Write the pending data in the |
| 280 |
* FIFO. |
261 |
* FIFO. |
| 281 |
*/ |
262 |
*/ |
| 282 |
amount = sc->sc_buffer->len - sc->sc_buffer_pos; |
263 |
|
|
|
264 |
fifo_size = (ti_i2c_read_2(sc, I2C_REG_BUFSTAT) & I2C_BUFSTAT_TXSTAT_MASK) >> I2C_BUFSTAT_TXSTAT_SHIFT; |
| 265 |
amount = min(fifo_size, sc->sc_buffer->len - sc->sc_buffer_pos); |
| 266 |
ti_i2c_dbg(sc, "Transmit draining interrupt, draining %d bytes\n", amount); |
| 283 |
} else if (status & I2C_STAT_XRDY) { |
267 |
} else if (status & I2C_STAT_XRDY) { |
| 284 |
/* |
268 |
/* |
| 285 |
* Transmit data ready interrupt - the FIFO level |
269 |
* Transmit data ready interrupt - the FIFO level |
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Lines 322-328
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| 322 |
{ |
306 |
{ |
| 323 |
int done; |
307 |
int done; |
| 324 |
struct ti_i2c_softc *sc; |
308 |
struct ti_i2c_softc *sc; |
| 325 |
uint16_t events, status; |
309 |
uint16_t status; |
| 326 |
|
310 |
|
| 327 |
sc = (struct ti_i2c_softc *)arg; |
311 |
sc = (struct ti_i2c_softc *)arg; |
| 328 |
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312 |
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Lines 334-355
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| 334 |
return; |
318 |
return; |
| 335 |
} |
319 |
} |
| 336 |
|
320 |
|
| 337 |
/* Save enabled interrupts. */ |
321 |
ti_i2c_dbg(sc, "Interrupt status, %x\n", status); |
| 338 |
events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); |
|
|
| 339 |
|
322 |
|
| 340 |
/* We only care about enabled interrupts. */ |
|
|
| 341 |
status &= events; |
| 342 |
|
| 343 |
done = 0; |
323 |
done = 0; |
| 344 |
|
324 |
|
| 345 |
if (sc->sc_buffer != NULL) |
325 |
/* Check for the error conditions. */ |
| 346 |
done = ti_i2c_transfer_intr(sc, status); |
326 |
if (status & I2C_STAT_NACK) { |
| 347 |
else { |
327 |
/* No ACK from slave. */ |
| 348 |
ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); |
328 |
ti_i2c_dbg(sc, "NACK\n"); |
| 349 |
sc->sc_error = EINVAL; |
329 |
ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); |
|
|
330 |
sc->sc_error = ENXIO; |
| 331 |
goto out; |
| 332 |
} else if (status & I2C_STAT_AL) { |
| 333 |
/* Arbitration lost. */ |
| 334 |
ti_i2c_dbg(sc, "Arbitration lost\n"); |
| 335 |
ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); |
| 336 |
sc->sc_error = ENXIO; |
| 337 |
goto out; |
| 338 |
} else if (status & I2C_STAT_ARDY) { |
| 339 |
/* Register access ready - transaction complete basically. */ |
| 340 |
ti_i2c_dbg(sc, "ARDY transaction complete\n"); |
| 341 |
if (sc->sc_error != 0 && ! sc->sc_buffer->flags & IIC_M_NOSTOP) { |
| 342 |
ti_i2c_write_2(sc, I2C_REG_CON, |
| 343 |
sc->sc_con_reg | I2C_CON_STP); |
| 344 |
} |
| 345 |
ti_i2c_write_2(sc, I2C_REG_STATUS, |
| 346 |
I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | |
| 347 |
I2C_STAT_XDR | I2C_STAT_XRDY); |
| 350 |
done = 1; |
348 |
done = 1; |
|
|
349 |
goto out; |
| 350 |
} else if (status & I2C_STAT_RRDY || status & I2C_STAT_XRDY || status & I2C_STAT_RDR || status & I2C_STAT_XDR) { |
| 351 |
if (sc->sc_buffer != NULL) |
| 352 |
done = ti_i2c_transfer_intr(sc, status); |
| 353 |
else { |
| 354 |
ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); |
| 355 |
sc->sc_error = EINVAL; |
| 356 |
done = 1; |
| 357 |
} |
| 351 |
} |
358 |
} |
| 352 |
|
359 |
|
|
|
360 |
out: |
| 353 |
if (done) |
361 |
if (done) |
| 354 |
/* Wakeup the process that started the transaction. */ |
362 |
/* Wakeup the process that started the transaction. */ |
| 355 |
wakeup(sc); |
363 |
wakeup(sc); |
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Lines 359-386
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| 359 |
|
367 |
|
| 360 |
/** |
368 |
/** |
| 361 |
* ti_i2c_transfer - called to perform the transfer |
369 |
* ti_i2c_transfer - called to perform the transfer |
| 362 |
* @dev: i2c device handle |
370 |
* @sc: I2C device context |
| 363 |
* @msgs: the messages to send/receive |
371 |
* @msgs: the messages to send/receive |
| 364 |
* @nmsgs: the number of messages in the msgs array |
372 |
* @nmsgs: the number of messages in the msgs array |
| 365 |
* |
373 |
* |
| 366 |
* |
374 |
* |
| 367 |
* LOCKING: |
|
|
| 368 |
* Internally locked |
| 369 |
* |
| 370 |
* RETURNS: |
375 |
* RETURNS: |
| 371 |
* 0 on function succeeded |
376 |
* 0 on function succeeded |
| 372 |
* EINVAL if invalid message is passed as an arg |
377 |
* EINVAL if invalid message is passed as an arg |
| 373 |
*/ |
378 |
*/ |
| 374 |
static int |
379 |
static int |
| 375 |
ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) |
380 |
ti_i2c_transfer(struct ti_i2c_softc *sc, struct iic_msg *msgs, uint32_t nmsgs) |
| 376 |
{ |
381 |
{ |
| 377 |
int err, i, repstart, timeout; |
382 |
int err, i, repstart, timeout; |
| 378 |
struct ti_i2c_softc *sc; |
|
|
| 379 |
uint16_t reg; |
383 |
uint16_t reg; |
| 380 |
|
384 |
|
| 381 |
sc = device_get_softc(dev); |
|
|
| 382 |
TI_I2C_LOCK(sc); |
| 383 |
|
| 384 |
/* If the controller is busy wait until it is available. */ |
385 |
/* If the controller is busy wait until it is available. */ |
| 385 |
while (sc->sc_bus_inuse == 1) |
386 |
while (sc->sc_bus_inuse == 1) |
| 386 |
mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); |
387 |
mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); |
|
Lines 388-394
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|
| 388 |
/* Now we have control over the I2C controller. */ |
389 |
/* Now we have control over the I2C controller. */ |
| 389 |
sc->sc_bus_inuse = 1; |
390 |
sc->sc_bus_inuse = 1; |
| 390 |
|
391 |
|
| 391 |
err = 0; |
392 |
err = IIC_NOERR; |
| 392 |
repstart = 0; |
393 |
repstart = 0; |
| 393 |
for (i = 0; i < nmsgs; i++) { |
394 |
for (i = 0; i < nmsgs; i++) { |
| 394 |
|
395 |
|
|
Lines 436-443
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|
| 436 |
ti_i2c_write_2(sc, I2C_REG_BUF, reg); |
437 |
ti_i2c_write_2(sc, I2C_REG_BUF, reg); |
| 437 |
|
438 |
|
| 438 |
reg = sc->sc_con_reg | I2C_CON_STT; |
439 |
reg = sc->sc_con_reg | I2C_CON_STT; |
| 439 |
if (repstart == 0) |
440 |
if (repstart == 0) { |
| 440 |
reg |= I2C_CON_STP; |
441 |
reg |= I2C_CON_STP; |
|
|
442 |
} |
| 441 |
if ((sc->sc_buffer->flags & IIC_M_RD) == 0) |
443 |
if ((sc->sc_buffer->flags & IIC_M_RD) == 0) |
| 442 |
reg |= I2C_CON_TRX; |
444 |
reg |= I2C_CON_TRX; |
| 443 |
ti_i2c_write_2(sc, I2C_REG_CON, reg); |
445 |
ti_i2c_write_2(sc, I2C_REG_CON, reg); |
|
Lines 469-476
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|
| 469 |
/* Wake up the processes that are waiting for the bus. */ |
471 |
/* Wake up the processes that are waiting for the bus. */ |
| 470 |
wakeup(sc); |
472 |
wakeup(sc); |
| 471 |
|
473 |
|
| 472 |
TI_I2C_UNLOCK(sc); |
|
|
| 473 |
|
| 474 |
return (err); |
474 |
return (err); |
| 475 |
} |
475 |
} |
| 476 |
|
476 |
|
|
Lines 524-530
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|
| 524 |
sc->sc_con_reg = 0; |
524 |
sc->sc_con_reg = 0; |
| 525 |
ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); |
525 |
ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); |
| 526 |
|
526 |
|
| 527 |
/* 2. Issue a softreset to the controller. */ |
527 |
/* 2. Issue a softreset to the controller and enable auto-idle. */ |
| 528 |
bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); |
528 |
bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); |
| 529 |
|
529 |
|
| 530 |
/* |
530 |
/* |
|
Lines 675-680
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|
| 675 |
} |
675 |
} |
| 676 |
|
676 |
|
| 677 |
static int |
677 |
static int |
|
|
678 |
ti_i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) |
| 679 |
{ |
| 680 |
struct ti_i2c_softc *sc; |
| 681 |
struct iic_msg msg; |
| 682 |
int err; |
| 683 |
|
| 684 |
err = IIC_NOERR; |
| 685 |
sc = device_get_softc(dev); |
| 686 |
TI_I2C_LOCK(sc); |
| 687 |
|
| 688 |
msg.buf = buf; |
| 689 |
msg.len = len; |
| 690 |
msg.flags = IIC_M_RD | sc->sc_buffer_flags; |
| 691 |
msg.slave = sc->sc_slave_addr; |
| 692 |
|
| 693 |
err = ti_i2c_transfer(sc, &msg, 1); |
| 694 |
|
| 695 |
*read = sc->sc_buffer_pos; |
| 696 |
|
| 697 |
TI_I2C_UNLOCK(sc); |
| 698 |
|
| 699 |
if (err) |
| 700 |
return (err); |
| 701 |
|
| 702 |
return (IIC_NOERR); |
| 703 |
} |
| 704 |
|
| 705 |
static int |
| 706 |
ti_i2c_write(device_t dev, const char *buf, int len, int *sent, int delay) |
| 707 |
{ |
| 708 |
struct ti_i2c_softc *sc; |
| 709 |
struct iic_msg msg; |
| 710 |
int err; |
| 711 |
|
| 712 |
if (len > BUFSIZE) |
| 713 |
return (ENODEV); |
| 714 |
|
| 715 |
err = IIC_NOERR; |
| 716 |
sc = device_get_softc(dev); |
| 717 |
TI_I2C_LOCK(sc); |
| 718 |
|
| 719 |
memcpy(sc->sc_buffer_buf, buf, len); |
| 720 |
|
| 721 |
msg.buf = sc->sc_buffer_buf; |
| 722 |
msg.len = len; |
| 723 |
msg.flags = sc->sc_buffer_flags; |
| 724 |
msg.slave = sc->sc_slave_addr; |
| 725 |
|
| 726 |
err = ti_i2c_transfer(sc, &msg, 1); |
| 727 |
|
| 728 |
*sent = sc->sc_buffer_pos; |
| 729 |
|
| 730 |
TI_I2C_UNLOCK(sc); |
| 731 |
|
| 732 |
if (err) |
| 733 |
return (err); |
| 734 |
|
| 735 |
return (IIC_NOERR); |
| 736 |
} |
| 737 |
|
| 738 |
static int |
| 739 |
ti_i2c_start(device_t dev, u_char slave, int timeout) |
| 740 |
{ |
| 741 |
struct ti_i2c_softc *sc; |
| 742 |
|
| 743 |
sc = device_get_softc(dev); |
| 744 |
TI_I2C_LOCK(sc); |
| 745 |
|
| 746 |
/* Configure slave address */ |
| 747 |
sc->sc_slave_addr = slave; |
| 748 |
sc->sc_buffer_flags = 0; |
| 749 |
|
| 750 |
TI_I2C_UNLOCK(sc); |
| 751 |
|
| 752 |
return (IIC_NOERR); |
| 753 |
} |
| 754 |
|
| 755 |
static int |
| 756 |
ti_i2c_repeated_start(device_t dev, u_char slave, int timeout) |
| 757 |
{ |
| 758 |
struct ti_i2c_softc *sc; |
| 759 |
|
| 760 |
sc = device_get_softc(dev); |
| 761 |
TI_I2C_LOCK(sc); |
| 762 |
|
| 763 |
/* Configure slave address */ |
| 764 |
sc->sc_slave_addr = slave; |
| 765 |
sc->sc_buffer_flags = IIC_M_NOSTOP; |
| 766 |
|
| 767 |
TI_I2C_UNLOCK(sc); |
| 768 |
|
| 769 |
return (IIC_NOERR); |
| 770 |
} |
| 771 |
|
| 772 |
static int |
| 773 |
ti_i2c_stop(device_t dev) |
| 774 |
{ |
| 775 |
return (IIC_NOERR); |
| 776 |
} |
| 777 |
|
| 778 |
static int |
| 779 |
ti_i2c_iicbus_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) |
| 780 |
{ |
| 781 |
struct ti_i2c_softc *sc; |
| 782 |
int err; |
| 783 |
|
| 784 |
sc = device_get_softc(dev); |
| 785 |
TI_I2C_LOCK(sc); |
| 786 |
err = ti_i2c_transfer(sc, msgs, nmsgs); |
| 787 |
TI_I2C_UNLOCK(sc); |
| 788 |
if (err) |
| 789 |
return (err); |
| 790 |
|
| 791 |
return (IIC_ENOADDR); |
| 792 |
} |
| 793 |
|
| 794 |
static int |
| 678 |
ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) |
795 |
ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) |
| 679 |
{ |
796 |
{ |
| 680 |
struct ti_i2c_softc *sc; |
797 |
struct ti_i2c_softc *sc; |
|
Lines 790-796
Link Here
|
| 790 |
|
907 |
|
| 791 |
sc = arg1; |
908 |
sc = arg1; |
| 792 |
|
909 |
|
| 793 |
/* |
910 |
/* |
| 794 |
* MTX_DEF lock can't be held while doing uimove in |
911 |
* MTX_DEF lock can't be held while doing uimove in |
| 795 |
* sysctl_handle_int |
912 |
* sysctl_handle_int |
| 796 |
*/ |
913 |
*/ |
|
Lines 882-889
Link Here
|
| 882 |
device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", |
999 |
device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", |
| 883 |
sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); |
1000 |
sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); |
| 884 |
|
1001 |
|
| 885 |
/* Set the FIFO threshold to 5 for now. */ |
1002 |
/* Set the FIFO threshold to 8 for now. */ |
| 886 |
sc->sc_fifo_trsh = 5; |
1003 |
sc->sc_fifo_trsh = 8; |
| 887 |
|
1004 |
|
| 888 |
/* Set I2C bus timeout */ |
1005 |
/* Set I2C bus timeout */ |
| 889 |
sc->sc_timeout = 5*hz; |
1006 |
sc->sc_timeout = 5*hz; |
|
Lines 959-965
Link Here
|
| 959 |
/* iicbus interface */ |
1076 |
/* iicbus interface */ |
| 960 |
DEVMETHOD(iicbus_callback, iicbus_null_callback), |
1077 |
DEVMETHOD(iicbus_callback, iicbus_null_callback), |
| 961 |
DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), |
1078 |
DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), |
| 962 |
DEVMETHOD(iicbus_transfer, ti_i2c_transfer), |
1079 |
DEVMETHOD(iicbus_transfer, ti_i2c_iicbus_transfer), |
|
|
1080 |
DEVMETHOD(iicbus_start, ti_i2c_start), |
| 1081 |
DEVMETHOD(iicbus_repeated_start, ti_i2c_repeated_start), |
| 1082 |
DEVMETHOD(iicbus_stop, ti_i2c_stop), |
| 1083 |
DEVMETHOD(iicbus_read, ti_i2c_read), |
| 1084 |
DEVMETHOD(iicbus_write, ti_i2c_write), |
| 963 |
|
1085 |
|
| 964 |
DEVMETHOD_END |
1086 |
DEVMETHOD_END |
| 965 |
}; |
1087 |
}; |