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(-)sys/dev/wpi/if_wpi.c (-11 / +14 lines)
Lines 3710-3715 Link Here
3710
	struct ifnet *ifp = sc->sc_ifp;
3710
	struct ifnet *ifp = sc->sc_ifp;
3711
	struct ieee80211com *ic = ifp->if_l2com;
3711
	struct ieee80211com *ic = ifp->if_l2com;
3712
	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3712
	struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3713
	struct ieee80211_channel *c = ic->ic_curchan;
3713
	uint32_t flags;
3714
	uint32_t flags;
3714
	int error;
3715
	int error;
3715
3716
Lines 3734-3742 Link Here
3734
	IEEE80211_ADDR_COPY(sc->rxon.myaddr, vap->iv_myaddr);
3735
	IEEE80211_ADDR_COPY(sc->rxon.myaddr, vap->iv_myaddr);
3735
3736
3736
	/* Set default channel. */
3737
	/* Set default channel. */
3737
	sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
3738
	sc->rxon.chan = ieee80211_chan2ieee(ic, c);
3738
	sc->rxon.flags = htole32(WPI_RXON_TSF | WPI_RXON_CTS_TO_SELF);
3739
	sc->rxon.flags = htole32(WPI_RXON_TSF | WPI_RXON_CTS_TO_SELF);
3739
	if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
3740
	if (IEEE80211_IS_CHAN_2GHZ(c))
3740
		sc->rxon.flags |= htole32(WPI_RXON_AUTO | WPI_RXON_24GHZ);
3741
		sc->rxon.flags |= htole32(WPI_RXON_AUTO | WPI_RXON_24GHZ);
3741
3742
3742
	sc->rxon.filter = WPI_FILTER_MULTICAST;
3743
	sc->rxon.filter = WPI_FILTER_MULTICAST;
Lines 4044-4049 Link Here
4044
{
4045
{
4045
	struct ieee80211com *ic = vap->iv_ic;
4046
	struct ieee80211com *ic = vap->iv_ic;
4046
	struct ieee80211_node *ni = vap->iv_bss;
4047
	struct ieee80211_node *ni = vap->iv_bss;
4048
	struct ieee80211_channel *c = ni->ni_chan;
4047
	int error;
4049
	int error;
4048
4050
4049
	WPI_RXON_LOCK(sc);
4051
	WPI_RXON_LOCK(sc);
Lines 4054-4071 Link Here
4054
	sc->rxon.associd = 0;
4056
	sc->rxon.associd = 0;
4055
	sc->rxon.filter &= ~htole32(WPI_FILTER_BSS);
4057
	sc->rxon.filter &= ~htole32(WPI_FILTER_BSS);
4056
	IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4058
	IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4057
	sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
4059
	sc->rxon.chan = ieee80211_chan2ieee(ic, c);
4058
	sc->rxon.flags = htole32(WPI_RXON_TSF | WPI_RXON_CTS_TO_SELF);
4060
	sc->rxon.flags = htole32(WPI_RXON_TSF | WPI_RXON_CTS_TO_SELF);
4059
	if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4061
	if (IEEE80211_IS_CHAN_2GHZ(c))
4060
		sc->rxon.flags |= htole32(WPI_RXON_AUTO | WPI_RXON_24GHZ);
4062
		sc->rxon.flags |= htole32(WPI_RXON_AUTO | WPI_RXON_24GHZ);
4061
	if (ic->ic_flags & IEEE80211_F_SHSLOT)
4063
	if (ic->ic_flags & IEEE80211_F_SHSLOT)
4062
		sc->rxon.flags |= htole32(WPI_RXON_SHSLOT);
4064
		sc->rxon.flags |= htole32(WPI_RXON_SHSLOT);
4063
	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4065
	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4064
		sc->rxon.flags |= htole32(WPI_RXON_SHPREAMBLE);
4066
		sc->rxon.flags |= htole32(WPI_RXON_SHPREAMBLE);
4065
	if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
4067
	if (IEEE80211_IS_CHAN_A(c)) {
4066
		sc->rxon.cck_mask  = 0;
4068
		sc->rxon.cck_mask  = 0;
4067
		sc->rxon.ofdm_mask = 0x15;
4069
		sc->rxon.ofdm_mask = 0x15;
4068
	} else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
4070
	} else if (IEEE80211_IS_CHAN_B(c)) {
4069
		sc->rxon.cck_mask  = 0x03;
4071
		sc->rxon.cck_mask  = 0x03;
4070
		sc->rxon.ofdm_mask = 0;
4072
		sc->rxon.ofdm_mask = 0;
4071
	} else {
4073
	} else {
Lines 4243-4248 Link Here
4243
{
4245
{
4244
	struct ieee80211com *ic = vap->iv_ic;
4246
	struct ieee80211com *ic = vap->iv_ic;
4245
	struct ieee80211_node *ni = vap->iv_bss;
4247
	struct ieee80211_node *ni = vap->iv_bss;
4248
	struct ieee80211_channel *c = ni->ni_chan;
4246
	int error;
4249
	int error;
4247
4250
4248
	DPRINTF(sc, WPI_DEBUG_TRACE, TRACE_STR_BEGIN, __func__);
4251
	DPRINTF(sc, WPI_DEBUG_TRACE, TRACE_STR_BEGIN, __func__);
Lines 4254-4260 Link Here
4254
	}
4257
	}
4255
4258
4256
	/* XXX kernel panic workaround */
4259
	/* XXX kernel panic workaround */
4257
	if (ni->ni_chan == IEEE80211_CHAN_ANYC) {
4260
	if (c == IEEE80211_CHAN_ANYC) {
4258
		device_printf(sc->sc_dev, "%s: incomplete configuration\n",
4261
		device_printf(sc->sc_dev, "%s: incomplete configuration\n",
4259
		    __func__);
4262
		    __func__);
4260
		return EINVAL;
4263
		return EINVAL;
Lines 4270-4287 Link Here
4270
	WPI_RXON_LOCK(sc);
4273
	WPI_RXON_LOCK(sc);
4271
	IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4274
	IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
4272
	sc->rxon.associd = htole16(IEEE80211_NODE_AID(ni));
4275
	sc->rxon.associd = htole16(IEEE80211_NODE_AID(ni));
4273
	sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
4276
	sc->rxon.chan = ieee80211_chan2ieee(ic, c);
4274
	sc->rxon.flags = htole32(WPI_RXON_TSF | WPI_RXON_CTS_TO_SELF);
4277
	sc->rxon.flags = htole32(WPI_RXON_TSF | WPI_RXON_CTS_TO_SELF);
4275
	if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
4278
	if (IEEE80211_IS_CHAN_2GHZ(c))
4276
		sc->rxon.flags |= htole32(WPI_RXON_AUTO | WPI_RXON_24GHZ);
4279
		sc->rxon.flags |= htole32(WPI_RXON_AUTO | WPI_RXON_24GHZ);
4277
	if (ic->ic_flags & IEEE80211_F_SHSLOT)
4280
	if (ic->ic_flags & IEEE80211_F_SHSLOT)
4278
		sc->rxon.flags |= htole32(WPI_RXON_SHSLOT);
4281
		sc->rxon.flags |= htole32(WPI_RXON_SHSLOT);
4279
	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4282
	if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
4280
		sc->rxon.flags |= htole32(WPI_RXON_SHPREAMBLE);
4283
		sc->rxon.flags |= htole32(WPI_RXON_SHPREAMBLE);
4281
	if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
4284
	if (IEEE80211_IS_CHAN_A(c)) {
4282
		sc->rxon.cck_mask  = 0;
4285
		sc->rxon.cck_mask  = 0;
4283
		sc->rxon.ofdm_mask = 0x15;
4286
		sc->rxon.ofdm_mask = 0x15;
4284
	} else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
4287
	} else if (IEEE80211_IS_CHAN_B(c)) {
4285
		sc->rxon.cck_mask  = 0x03;
4288
		sc->rxon.cck_mask  = 0x03;
4286
		sc->rxon.ofdm_mask = 0;
4289
		sc->rxon.ofdm_mask = 0;
4287
	} else {
4290
	} else {

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