Attachment #157917 for bug #196081

Lines 66-72 Link Here

(-)sys/arm/allwinner/a10_mmc.h (-1 / +21 lines)
66	#define A10_MMC_DMA_ENABLE (1U << 5)	66	#define A10_MMC_DMA_ENABLE (1U << 5)
67	#define A10_MMC_DEBOUNCE_ENABLE (1U << 8)	67	#define A10_MMC_DEBOUNCE_ENABLE (1U << 8)
68	#define A10_MMC_DDR_MODE (1U << 10)	68	#define A10_MMC_DDR_MODE (1U << 10)
69	#define A10_MMC_ACCESS_BY_DMA (1U << 30)	69	#define A10_MMC_ACCESS_BY_DMA (0U << 31)
70	#define A10_MMC_ACCESS_BY_AHB (1U << 31)	70	#define A10_MMC_ACCESS_BY_AHB (1U << 31)
71	#define A10_MMC_RESET \	71	#define A10_MMC_RESET \
72	(A10_MMC_SOFT_RESET \| A10_MMC_FIFO_RESET \| A10_MMC_DMA_RESET)	72	(A10_MMC_SOFT_RESET \| A10_MMC_FIFO_RESET \| A10_MMC_DMA_RESET)
Lines 175-179 Link Here
175	#define A10_MMC_IDMAC_RD (6U << 13)	175	#define A10_MMC_IDMAC_RD (6U << 13)
176	#define A10_MMC_IDMAC_WR (7U << 13)	176	#define A10_MMC_IDMAC_WR (7U << 13)
177	#define A10_MMC_IDMAC_DESC_CLOSE (8U << 13)	177	#define A10_MMC_IDMAC_DESC_CLOSE (8U << 13)
		178	#define A10_MMC_IDMAC_ERROR \
		179	(A10_MMC_IDMAC_FATAL_BUS_ERR \| A10_MMC_IDMAC_CARD_ERR_SUM \| A10_MMC_IDMAC_DES_INVALID \| \
		180	A10_MMC_IDMAC_ABNORMAL_INT_SUM)
		181	#define A10_MMC_IDMAC_COMPLETE \
		182	(A10_MMC_IDMAC_TRANSMIT_INT \| A10_MMC_IDMAC_RECEIVE_INT)
178		183
		184	/* Used to make the descriptor table for suppoting DMA Access */
		185	struct a10_mmc_dma_desc {
		186	uint32_t config ;
		187	#define A10_MMC_DMA_CONFIG_DIC (1U << 1)
		188	#define A10_MMC_DMA_CONFIG_LD (1U << 2)
		189	#define A10_MMC_DMA_CONFIG_FD (1U << 3)
		190	#define A10_MMC_DMA_CONFIG_CH (1U << 4)
		191	#define A10_MMC_DMA_CONFIG_ER (1U << 5)
		192	#define A10_MMC_DMA_CONFIG_CES (1U << 30)
		193	#define A10_MMC_DMA_CONFIG_OWN (1U << 31)
		194	uint32_t buff_size ;
		195	uint32_t buff_addr ;
		196	uint32_t next;
		197	} ;
		198
179	#endif /* _A10_MMC_H_ */	199	#endif /* _A10_MMC_H_ */




#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <sys/endian.h>

#include <machine/bus.h>


#include <dev/mmc/mmcreg.h>
#include <dev/mmc/mmcbrvar.h>


#include <arm/allwinner/a10_clk.h>
#include <arm/allwinner/a10_mmc.h>


#define	A10_MMC_MEMRES		0
#define	A10_MMC_IRQRES		1
#define	A10_MMC_RESSZ		2
#define A10_MMC_NDESC		16
#define A10_DMA_NSEGS		16
#define A10_DMA_BUFF_SIZE	0x2000
#define A10_DMA_MAX_SIZE	0x20000
#define A10_MMC_DMA_FTRGLEVEL_A20	0x20070008
#define A10_MMC_DMA_FTRGLEVEL_A10 	0x00070208
#define A10_MMC_DMA_MAXLEN  	(A10_DMA_MAX_SIZE)
#define A10_MMC_DMA_MINLEN	512

struct a10_mmc_softc {
	bus_space_handle_t	a10_bsh;

	struct mtx		a10_mtx;
	struct resource *	a10_res[A10_MMC_RESSZ];
	uint32_t		a10_intr;
	uint32_t		a10_idst ;
	uint32_t		a10_intr_wait;
	void *			a10_intrhand;
	int 			a10_use_dma ;

	/* Fields required for DMA access */
	bus_addr_t	  	a10_dma_cb_arg ;
	bus_dmamap_t		a10_dma_map ;
	bus_dma_tag_t 		a10_dma_tag ;
	void* 			a10_dma_desc ;
	bus_dma_tag_t		a10_dma_buff_tag ;
	bus_dmamap_t		a10_dma_buff_map ;
	bus_addr_t		a10_dma_buff_addrs[A10_DMA_NSEGS] ;
	bus_size_t		a10_dma_buff_sizes[A10_DMA_NSEGS] ;  
	uint32_t 		a10_dma_nsegs ; 

};

static struct resource_spec a10_mmc_res_spec[] = {


static int a10_mmc_probe(device_t);
static int a10_mmc_attach(device_t);
static int a10_mmc_setup_dma(struct a10_mmc_softc*, device_t) ;
static int a10_mmc_prepare_dma(struct a10_mmc_softc*) ;
static int a10_mmc_can_do_dma(struct mmc_request*) ;
static void a10_dma_buff_cb(void*, bus_dma_segment_t*, int, int) ;
static int a10_mmc_detach(device_t);
static int a10_mmc_reset(struct a10_mmc_softc *);
static void a10_mmc_intr(void *);
static int a10_mmc_update_clock(struct a10_mmc_softc *);

static void a10_dma_cb(void*, bus_dma_segment_t*, int, int) ;
static int a10_mmc_update_ios(device_t, device_t);
static int a10_mmc_request(device_t, device_t, struct mmc_request *);
static int a10_mmc_get_ro(device_t, device_t);

	bus_space_read_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg)
#define	A10_MMC_WRITE_4(_sc, _reg, _value)				\
	bus_space_write_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value)
#define	A10_MMC_READ_2(_sc, _reg)					\
	bus_space_read_2((_sc)->a10_bst, (_sc)->a10_bsh, _reg)
#define	A10_MMC_WRITE_2(_sc, _reg, _value)				\
	bus_space_write_2((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value)



static int
a10_mmc_probe(device_t dev)
{

	struct sysctl_oid_list *tree;

	sc = device_get_softc(dev);
	sc->a10_use_dma = 1 ;
	sc->a10_dev = dev;
	sc->a10_req = NULL;
	sc->a10_id = device_get_unit(dev);

		goto fail;
	}

	if (sc->a10_use_dma == 1) {
		if (a10_mmc_setup_dma(sc,dev) != 0) {
			device_printf(sc->a10_dev, "Couldn't setup DMA!\n") ;
			sc->a10_use_dma = 0 ;
		}
	}
	//device_printf(sc->a10_dev, "The address of desc is %p\n",sc->a10_dma_desc) ; 
	sc->a10_dma_nsegs = 0 ; 
#ifdef DEBUG
	device_printf(sc->a10_dev, "DMA status %d\n", sc->a10_use_dma) ;
#endif
	return (0);

fail:

}

static int
a10_mmc_setup_dma(struct a10_mmc_softc* sc, device_t dev)
{
	uint32_t a10_dma_size = sizeof(struct a10_mmc_dma_desc)*(A10_MMC_NDESC);

	uint32_t error ;
	error = bus_dma_tag_create(bus_get_dma_tag(dev),1,
				a10_dma_size,BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
				NULL,NULL,a10_dma_size,
				1,a10_dma_size,0,
				NULL,NULL,&sc->a10_dma_tag) ;
	if (error)
		return (error) ;
	error = bus_dmamem_alloc(sc->a10_dma_tag,&sc->a10_dma_desc,BUS_DMA_WAITOK|BUS_DMA_ZERO,&sc->a10_dma_map) ;
		if (error)
			return (error) ;

	error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map,sc->a10_dma_desc,a10_dma_size,a10_dma_cb, &sc->a10_dma_cb_arg,0) ;

	if ((error != 0)&&(error != EINPROGRESS))
		return (error) ;
	error = bus_dma_tag_create(bus_get_dma_tag(dev),1,
				0,BUS_SPACE_MAXADDR_32BIT,BUS_SPACE_MAXADDR,
				NULL,NULL,A10_DMA_MAX_SIZE,
				A10_DMA_NSEGS,A10_DMA_BUFF_SIZE,0,
				NULL,NULL,&sc->a10_dma_buff_tag) ;
	if (error)
		return (error) ;

	error = bus_dmamap_create(sc->a10_dma_buff_tag,0,&sc->a10_dma_buff_map) ;
	if (error)
		return (error) ;

	return(0) ;

}

static int
a10_mmc_prepare_dma(struct a10_mmc_softc* sc)
{

	struct a10_mmc_dma_desc* dma = sc->a10_dma_desc ;
	struct mmc_command* cmd = sc->a10_req->cmd ;
	bus_addr_t desc_paddr = sc->a10_dma_cb_arg ;
	int desc, rem ;
	uint32_t val;
	desc = 0 ;
	rem = min(A10_MMC_DMA_MAXLEN,cmd->data->len) ;
	uint32_t error = bus_dmamap_load(sc->a10_dma_buff_tag, sc->a10_dma_buff_map,
					cmd->data->data,rem,a10_dma_buff_cb,
					sc,0) ;
	if (error == EINPROGRESS) {
		for( ; sc->a10_dma_nsegs == 0 ; )  { }
	}
	else if (error != 0)  {
		device_printf(sc->a10_dev, "DMA transaction failed due to insufficient resources! error = %u\n",error) ;
		return EIO  ;
	}

	dma[0].config |= htole32(A10_MMC_DMA_CONFIG_FD) ; 
	while (desc < A10_MMC_NDESC) { 
		dma[desc].buff_size = htole32(sc->a10_dma_buff_sizes[desc]) ;
		dma[desc].buff_addr = htole32(sc->a10_dma_buff_addrs[desc]) ;
		dma[desc].config = htole32(A10_MMC_DMA_CONFIG_CH|A10_MMC_DMA_CONFIG_OWN) ;
		rem -= sc->a10_dma_buff_sizes[desc] ; 
		cmd->data->len -= sc->a10_dma_buff_sizes[desc] ; 
		if (rem > 0) {
			dma[desc].config |= htole32(A10_MMC_DMA_CONFIG_DIC) ;
			dma[desc].next = htole32(desc_paddr + ((desc+1)*sizeof(struct a10_mmc_dma_desc))) ;
		}
		else {
			dma[desc].config |= htole32(A10_MMC_DMA_CONFIG_LD | A10_MMC_DMA_CONFIG_ER) ; 
			dma[desc].next = 0  ; 
			break ; 
		}
		desc++ ;
	}
	if (rem > 0) {
		device_printf(sc->a10_dev, "Couldn't find enough descriptors for DMA transfer!, rem = %d\n", rem);
		return EIO ;
	}

	if (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE)
		bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_PREWRITE) ;
	else
		bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_PREREAD) ;

	bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE) ;

	val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) ;
	val |= A10_MMC_DMA_ENABLE ;
	val |= A10_MMC_INT_ENABLE ;
	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,val) ;
	val |= A10_MMC_DMA_RESET ;
	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,val) ;
	A10_MMC_WRITE_4(sc, A10_MMC_DMAC,A10_MMC_IDMAC_SOFT_RST) ;
	A10_MMC_WRITE_4(sc, A10_MMC_DMAC,A10_MMC_IDMAC_IDMA_ON | A10_MMC_IDMAC_FIX_BURST) ;
	val = A10_MMC_READ_4(sc,A10_MMC_IDIE) ;
	val &= ~(A10_MMC_IDMAC_RECEIVE_INT | A10_MMC_IDMAC_TRANSMIT_INT) ;
	A10_MMC_WRITE_4(sc,A10_MMC_IDIE, val) ;
	if (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE)
		val |= A10_MMC_IDMAC_TRANSMIT_INT ;
	else
		val |= A10_MMC_IDMAC_RECEIVE_INT ;
	A10_MMC_WRITE_4(sc, A10_MMC_IDIE,val) ;
	A10_MMC_WRITE_4(sc, A10_MMC_DLBA,desc_paddr) ;
	A10_MMC_WRITE_4(sc, A10_MMC_FTRGL,A10_MMC_DMA_FTRGLEVEL_A10) ;

	return (0) ;
}


static int
a10_mmc_can_do_dma(struct mmc_request* req)
{
	if (req->cmd->data->len >= A10_MMC_DMA_MAXLEN) 
		return (0) ;
	else
		return (1) ;
}
static void
a10_dma_cb(void* arg, bus_dma_segment_t* segs, int nsegs, int error)
{
	if (error) {
		printf("a10_mmc: Error in a10_dma_callback function, code = %d\n",error) ;
		return ;
	}

	*(bus_addr_t*)arg = segs[0].ds_addr ;
}

static void
a10_dma_buff_cb(void* arg, bus_dma_segment_t* segs, int nsegs, int error)
{
	if (error) {
		printf("a10_mmc: Error in a10_dma_buff_callback function, code = %d\n", error) ;
		return  ;
	}
	int i ; 
	struct a10_mmc_softc* sc = (struct a10_mmc_softc*) arg ; 
	sc->a10_dma_nsegs = nsegs ; 
	for(i=0; i<nsegs; i++) { 
		sc->a10_dma_buff_addrs[i] = segs[i].ds_addr ; 
		sc->a10_dma_buff_sizes[i] = segs[i].ds_len ; 
	}
}

static int
a10_mmc_detach(device_t dev)
{


	if (timeout == 0)
		return (ETIMEDOUT);

	/* Set the timeout. */
	A10_MMC_WRITE_4(sc, A10_MMC_TIMEOUT, 0xffffffff);

	/* Clear pending interrupts. */
	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff);
	A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff) ;
	/* Unmask interrupts. */
	A10_MMC_WRITE_4(sc, A10_MMC_IMASK,
	    A10_MMC_CMD_DONE | A10_MMC_INT_ERR_BIT |
	    A10_MMC_DATA_OVER | A10_MMC_AUTOCMD_DONE |
	    A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ);
	uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ;
	temp_val  = temp_val & (~A10_MMC_DMA_ENABLE) ;
	/* Enable interrupts and AHB access. */
	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,temp_val) ;
	    A10_MMC_READ_4(sc, A10_MMC_GCTRL) |
	    A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB);

	return (0);
}


	sc->a10_req = NULL;
	sc->a10_intr = 0;
	sc->a10_resid = 0;
	sc->a10_idst = 0 ;
	sc->a10_intr_wait = 0;
	sc->a10_dma_nsegs = 0 ;
	req->done(req);
}


	a10_mmc_req_done(sc);
}

static void
a10_mmc_timeout(void *arg)
{
	struct a10_mmc_softc *sc;

{
	struct a10_mmc_softc *sc;
	struct mmc_data *data;
	uint32_t imask, rint,idst;

	sc = (struct a10_mmc_softc *)arg;
	A10_MMC_LOCK(sc);
	rint = A10_MMC_READ_4(sc, A10_MMC_RINTR);
	imask = A10_MMC_READ_4(sc, A10_MMC_IMASK);
	idst = A10_MMC_READ_4(sc, A10_MMC_IDST) ;

	if (imask == 0 && rint == 0 && idst == 0 ) {
		A10_MMC_UNLOCK(sc);
		return;
	}

	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint) ;
	A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst) ;
	A10_MMC_WRITE_4(sc, A10_MMC_IMASK, imask) ;
	//device_printf(sc->a10_dev, "imask: %#x, rint: %#x, idst: %#x, gctrl: %#x\n", imask, rint,idst, A10_MMC_READ_4(sc, A10_MMC_GCTRL));
	if (sc->a10_req == NULL) {
		device_printf(sc->a10_dev,
		    "Spurious interrupt - no active request, rint: 0x%08X\n",
		    rint);
		A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
		A10_MMC_UNLOCK(sc);
		return;
	}

	sc->a10_intr |= rint;
	if (rint & A10_MMC_INT_ERR_BIT) {
		device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint);
		if (rint & A10_MMC_RESP_TIMEOUT) {
			sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
		}
		else
			sc->a10_req->cmd->error = MMC_ERR_FAILED;
		A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
		a10_mmc_req_done(sc);
		A10_MMC_UNLOCK(sc);
		return;
	}

	if (idst & A10_MMC_IDMAC_ERROR) {
		device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst) ;
		sc->a10_req->cmd->error = MMC_ERR_FAILED ;
		a10_mmc_req_done(sc) ;
		A10_MMC_UNLOCK(sc) ;
		return ;
	}

	if ((idst & A10_MMC_IDMAC_COMPLETE) && ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)) {
		if (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE)
			bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_POSTWRITE) ;
		else 
			bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_POSTREAD) ;
		bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_POSTWRITE) ; 
		bus_dmamap_unload(sc->a10_dma_buff_tag, sc->a10_dma_buff_map) ;
		a10_mmc_req_ok(sc) ;
		A10_MMC_UNLOCK(sc) ;
		return ;
	}

	if ((idst)&&(!(idst & A10_MMC_IDMAC_COMPLETE))) {
		device_printf(sc->a10_dev, "DMA timeout error!\n") ;
		sc->a10_req->cmd->error = MMC_ERR_TIMEOUT ;
		a10_mmc_req_done(sc) ;
		A10_MMC_UNLOCK(sc) ;
		return  ;
	}

	data = sc->a10_req->cmd->data;

	if (data != NULL && (rint & (A10_MMC_DATA_OVER |
	    A10_MMC_RX_DATA_REQ | A10_MMC_TX_DATA_REQ)) != 0)
			a10_mmc_pio_transfer(sc, data);
	if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)
		a10_mmc_req_ok(sc);

	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
	A10_MMC_UNLOCK(sc);
}


	int blksz;
	struct a10_mmc_softc *sc;
	struct mmc_command *cmd;
	uint32_t cmdreg ;

	sc = device_get_softc(bus);
	A10_MMC_LOCK(sc);

		A10_MMC_UNLOCK(sc);
		return (EBUSY);
	}

	sc->a10_req = req;
	cmd = req->cmd;
	cmdreg = A10_MMC_START;


	sc->a10_intr = 0;
	sc->a10_resid = 0;
	sc->a10_idst = 0 ;
	sc->a10_intr_wait = A10_MMC_CMD_DONE;
	cmd->error = MMC_ERR_NONE;

	if (cmd->data != NULL) {
		sc->a10_intr_wait |= A10_MMC_DATA_OVER;
		cmdreg |= A10_MMC_DATA_EXP | A10_MMC_WAIT_PREOVER;

			cmdreg |= A10_MMC_SEND_AUTOSTOP;
			sc->a10_intr_wait |= A10_MMC_AUTOCMD_DONE;
		}
		if (cmd->data->flags & MMC_DATA_WRITE) {
			cmdreg |= A10_MMC_WRITE;
		}

		blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
		A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz);
		A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len);

		if ((sc->a10_use_dma == 1)&&(a10_mmc_can_do_dma(req))) {
			uint32_t error = a10_mmc_prepare_dma(sc) ;
			if (error == 0) {
				A10_MMC_WRITE_4(sc, A10_MMC_IMASK, A10_MMC_READ_4(sc, A10_MMC_IMASK) | (A10_MMC_TX_DATA_REQ | A10_MMC_RX_DATA_REQ)) ;
			}
			else {
				uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ;
				temp_val  = temp_val & (~A10_MMC_DMA_ENABLE) ;
				A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ;
			}
		}
		else
		{
			uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ;
			temp_val  = temp_val & (~A10_MMC_DMA_ENABLE) ;
			A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ;
		}

	}
	else
	{
		uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) | A10_MMC_INT_ENABLE | A10_MMC_ACCESS_BY_AHB ;
		temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ;
		A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ;
	}

	A10_MMC_WRITE_4(sc, A10_MMC_CARG, cmd->arg);
	A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode);

}

static int
a10_mmc_read_ivar(device_t bus, device_t child, int which,
    uintptr_t *result)
{
	struct a10_mmc_softc *sc;

Return to bug 196081

Lines 38-43 Link Here

(-)sys/arm/allwinner/a10_mmc.c (-22 / +277 lines)
38	#include <sys/resource.h>	38	#include <sys/resource.h>
39	#include <sys/rman.h>	39	#include <sys/rman.h>
40	#include <sys/sysctl.h>	40	#include <sys/sysctl.h>
		41	#include <sys/endian.h>
41		42
42	#include <machine/bus.h>	43	#include <machine/bus.h>
43		44
Lines 48-53 Link Here
48	#include <dev/mmc/mmcreg.h>	49	#include <dev/mmc/mmcreg.h>
49	#include <dev/mmc/mmcbrvar.h>	50	#include <dev/mmc/mmcbrvar.h>
50		51
		52
51	#include <arm/allwinner/a10_clk.h>	53	#include <arm/allwinner/a10_clk.h>
52	#include <arm/allwinner/a10_mmc.h>	54	#include <arm/allwinner/a10_mmc.h>
53		55
Lines 54-59 Link Here
54	#define A10_MMC_MEMRES 0	56	#define A10_MMC_MEMRES 0
55	#define A10_MMC_IRQRES 1	57	#define A10_MMC_IRQRES 1
56	#define A10_MMC_RESSZ 2	58	#define A10_MMC_RESSZ 2
		59	#define A10_MMC_NDESC 16
		60	#define A10_DMA_NSEGS 16
		61	#define A10_DMA_BUFF_SIZE 0x2000
		62	#define A10_DMA_MAX_SIZE 0x20000
		63	#define A10_MMC_DMA_FTRGLEVEL_A20 0x20070008
		64	#define A10_MMC_DMA_FTRGLEVEL_A10 0x00070208
		65	#define A10_MMC_DMA_MAXLEN (A10_DMA_MAX_SIZE)
		66	#define A10_MMC_DMA_MINLEN 512
57		67
58	struct a10_mmc_softc {	68	struct a10_mmc_softc {
59	bus_space_handle_t a10_bsh;	69	bus_space_handle_t a10_bsh;
Lines 69-76 Link Here
69	struct mtx a10_mtx;	79	struct mtx a10_mtx;
70	struct resource * a10_res[A10_MMC_RESSZ];	80	struct resource * a10_res[A10_MMC_RESSZ];
71	uint32_t a10_intr;	81	uint32_t a10_intr;
		82	uint32_t a10_idst ;
72	uint32_t a10_intr_wait;	83	uint32_t a10_intr_wait;
73	void * a10_intrhand;	84	void * a10_intrhand;
		85	int a10_use_dma ;
		86
		87	/* Fields required for DMA access */
		88	bus_addr_t a10_dma_cb_arg ;
		89	bus_dmamap_t a10_dma_map ;
		90	bus_dma_tag_t a10_dma_tag ;
		91	void* a10_dma_desc ;
		92	bus_dma_tag_t a10_dma_buff_tag ;
		93	bus_dmamap_t a10_dma_buff_map ;
		94	bus_addr_t a10_dma_buff_addrs[A10_DMA_NSEGS] ;
		95	bus_size_t a10_dma_buff_sizes[A10_DMA_NSEGS] ;
		96	uint32_t a10_dma_nsegs ;
		97
74	};	98	};
75		99
76	static struct resource_spec a10_mmc_res_spec[] = {	100	static struct resource_spec a10_mmc_res_spec[] = {
Lines 81-91 Link Here
81		105
82	static int a10_mmc_probe(device_t);	106	static int a10_mmc_probe(device_t);
83	static int a10_mmc_attach(device_t);	107	static int a10_mmc_attach(device_t);
		108	static int a10_mmc_setup_dma(struct a10_mmc_softc*, device_t) ;
		109	static int a10_mmc_prepare_dma(struct a10_mmc_softc*) ;
		110	static int a10_mmc_can_do_dma(struct mmc_request*) ;
		111	static void a10_dma_buff_cb(void, bus_dma_segment_t, int, int) ;
84	static int a10_mmc_detach(device_t);	112	static int a10_mmc_detach(device_t);
85	static int a10_mmc_reset(struct a10_mmc_softc *);	113	static int a10_mmc_reset(struct a10_mmc_softc *);
86	static void a10_mmc_intr(void *);	114	static void a10_mmc_intr(void *);
87	static int a10_mmc_update_clock(struct a10_mmc_softc *);	115	static int a10_mmc_update_clock(struct a10_mmc_softc *);
88		116
		117	static void a10_dma_cb(void, bus_dma_segment_t, int, int) ;
89	static int a10_mmc_update_ios(device_t, device_t);	118	static int a10_mmc_update_ios(device_t, device_t);
90	static int a10_mmc_request(device_t, device_t, struct mmc_request *);	119	static int a10_mmc_request(device_t, device_t, struct mmc_request *);
91	static int a10_mmc_get_ro(device_t, device_t);	120	static int a10_mmc_get_ro(device_t, device_t);
Lines 98-104 Link Here
98	bus_space_read_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg)	127	bus_space_read_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg)
99	#define A10_MMC_WRITE_4(_sc, _reg, _value) \	128	#define A10_MMC_WRITE_4(_sc, _reg, _value) \
100	bus_space_write_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value)	129	bus_space_write_4((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value)
		130	#define A10_MMC_READ_2(_sc, _reg) \
		131	bus_space_read_2((_sc)->a10_bst, (_sc)->a10_bsh, _reg)
		132	#define A10_MMC_WRITE_2(_sc, _reg, _value) \
		133	bus_space_write_2((_sc)->a10_bst, (_sc)->a10_bsh, _reg, _value)
101		134
		135
		136
102	static int	137	static int
103	a10_mmc_probe(device_t dev)	138	a10_mmc_probe(device_t dev)
104	{	139	{
Lines 121-126 Link Here
121	struct sysctl_oid_list *tree;	156	struct sysctl_oid_list *tree;
122		157
123	sc = device_get_softc(dev);	158	sc = device_get_softc(dev);
		159	sc->a10_use_dma = 1 ;
124	sc->a10_dev = dev;	160	sc->a10_dev = dev;
125	sc->a10_req = NULL;	161	sc->a10_req = NULL;
126	sc->a10_id = device_get_unit(dev);	162	sc->a10_id = device_get_unit(dev);
Lines 183-188 Link Here
183	goto fail;	219	goto fail;
184	}	220	}
185		221
		222	if (sc->a10_use_dma == 1) {
		223	if (a10_mmc_setup_dma(sc,dev) != 0) {
		224	device_printf(sc->a10_dev, "Couldn't setup DMA!\n") ;
		225	sc->a10_use_dma = 0 ;
		226	}
		227	}
		228	//device_printf(sc->a10_dev, "The address of desc is %p\n",sc->a10_dma_desc) ;
		229	sc->a10_dma_nsegs = 0 ;
		230	#ifdef DEBUG
		231	device_printf(sc->a10_dev, "DMA status %d\n", sc->a10_use_dma) ;
		232	#endif
186	return (0);	233	return (0);
187		234
188	fail:	235	fail:
Lines 195-200 Link Here
195	}	242	}
196		243
197	static int	244	static int
		245	a10_mmc_setup_dma(struct a10_mmc_softc* sc, device_t dev)
		246	{
		247	uint32_t a10_dma_size = sizeof(struct a10_mmc_dma_desc)*(A10_MMC_NDESC);
		248
		249	uint32_t error ;
		250	error = bus_dma_tag_create(bus_get_dma_tag(dev),1,
		251	a10_dma_size,BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
		252	NULL,NULL,a10_dma_size,
		253	1,a10_dma_size,0,
		254	NULL,NULL,&sc->a10_dma_tag) ;
		255	if (error)
		256	return (error) ;
		257	error = bus_dmamem_alloc(sc->a10_dma_tag,&sc->a10_dma_desc,BUS_DMA_WAITOK\|BUS_DMA_ZERO,&sc->a10_dma_map) ;
		258	if (error)
		259	return (error) ;
		260
		261	error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map,sc->a10_dma_desc,a10_dma_size,a10_dma_cb, &sc->a10_dma_cb_arg,0) ;
		262
		263	if ((error != 0)&&(error != EINPROGRESS))
		264	return (error) ;
		265	error = bus_dma_tag_create(bus_get_dma_tag(dev),1,
		266	0,BUS_SPACE_MAXADDR_32BIT,BUS_SPACE_MAXADDR,
		267	NULL,NULL,A10_DMA_MAX_SIZE,
		268	A10_DMA_NSEGS,A10_DMA_BUFF_SIZE,0,
		269	NULL,NULL,&sc->a10_dma_buff_tag) ;
		270	if (error)
		271	return (error) ;
		272
		273	error = bus_dmamap_create(sc->a10_dma_buff_tag,0,&sc->a10_dma_buff_map) ;
		274	if (error)
		275	return (error) ;
		276
		277	return(0) ;
		278
		279	}
		280
		281	static int
		282	a10_mmc_prepare_dma(struct a10_mmc_softc* sc)
		283	{
		284
		285	struct a10_mmc_dma_desc* dma = sc->a10_dma_desc ;
		286	struct mmc_command* cmd = sc->a10_req->cmd ;
		287	bus_addr_t desc_paddr = sc->a10_dma_cb_arg ;
		288	int desc, rem ;
		289	uint32_t val;
		290	desc = 0 ;
		291	rem = min(A10_MMC_DMA_MAXLEN,cmd->data->len) ;
		292	uint32_t error = bus_dmamap_load(sc->a10_dma_buff_tag, sc->a10_dma_buff_map,
		293	cmd->data->data,rem,a10_dma_buff_cb,
		294	sc,0) ;
		295	if (error == EINPROGRESS) {
		296	for( ; sc->a10_dma_nsegs == 0 ; ) { }
		297	}
		298	else if (error != 0) {
		299	device_printf(sc->a10_dev, "DMA transaction failed due to insufficient resources! error = %u\n",error) ;
		300	return EIO ;
		301	}
		302
		303	dma[0].config \|= htole32(A10_MMC_DMA_CONFIG_FD) ;
		304	while (desc < A10_MMC_NDESC) {
		305	dma[desc].buff_size = htole32(sc->a10_dma_buff_sizes[desc]) ;
		306	dma[desc].buff_addr = htole32(sc->a10_dma_buff_addrs[desc]) ;
		307	dma[desc].config = htole32(A10_MMC_DMA_CONFIG_CH\|A10_MMC_DMA_CONFIG_OWN) ;
		308	rem -= sc->a10_dma_buff_sizes[desc] ;
309	cmd->data->len -= sc->a10_dma_buff_sizes[desc] ;
310	if (rem > 0) {
311	dma[desc].config \|= htole32(A10_MMC_DMA_CONFIG_DIC) ;
312	dma[desc].next = htole32(desc_paddr + ((desc+1)*sizeof(struct a10_mmc_dma_desc))) ;
313	}
314	else {
315	dma[desc].config \|= htole32(A10_MMC_DMA_CONFIG_LD \| A10_MMC_DMA_CONFIG_ER) ;
316	dma[desc].next = 0 ;
317	break ;
318	}
319	desc++ ;
320	}
321	if (rem > 0) {
322	device_printf(sc->a10_dev, "Couldn't find enough descriptors for DMA transfer!, rem = %d\n", rem);
323	return EIO ;
324	}
325
326	if (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE)
327	bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_PREWRITE) ;
328	else
329	bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_PREREAD) ;
330
331	bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE) ;
332
333	val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) ;
334	val \|= A10_MMC_DMA_ENABLE ;
335	val \|= A10_MMC_INT_ENABLE ;
336	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,val) ;
337	val \|= A10_MMC_DMA_RESET ;
338	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,val) ;
339	A10_MMC_WRITE_4(sc, A10_MMC_DMAC,A10_MMC_IDMAC_SOFT_RST) ;
340	A10_MMC_WRITE_4(sc, A10_MMC_DMAC,A10_MMC_IDMAC_IDMA_ON \| A10_MMC_IDMAC_FIX_BURST) ;
341	val = A10_MMC_READ_4(sc,A10_MMC_IDIE) ;
342	val &= ~(A10_MMC_IDMAC_RECEIVE_INT \| A10_MMC_IDMAC_TRANSMIT_INT) ;
343	A10_MMC_WRITE_4(sc,A10_MMC_IDIE, val) ;
344	if (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE)
345	val \|= A10_MMC_IDMAC_TRANSMIT_INT ;
346	else
347	val \|= A10_MMC_IDMAC_RECEIVE_INT ;
348	A10_MMC_WRITE_4(sc, A10_MMC_IDIE,val) ;
349	A10_MMC_WRITE_4(sc, A10_MMC_DLBA,desc_paddr) ;
350	A10_MMC_WRITE_4(sc, A10_MMC_FTRGL,A10_MMC_DMA_FTRGLEVEL_A10) ;
351
352	return (0) ;
353	}
354
355
356	static int
357	a10_mmc_can_do_dma(struct mmc_request* req)
358	{
359	if (req->cmd->data->len >= A10_MMC_DMA_MAXLEN)
360	return (0) ;
361	else
362	return (1) ;
363	}
364	static void
365	a10_dma_cb(void* arg, bus_dma_segment_t* segs, int nsegs, int error)
366	{
367	if (error) {
368	printf("a10_mmc: Error in a10_dma_callback function, code = %d\n",error) ;
369	return ;
370	}
371
372	(bus_addr_t)arg = segs[0].ds_addr ;
373	}
374
375	static void
376	a10_dma_buff_cb(void* arg, bus_dma_segment_t* segs, int nsegs, int error)
377	{
378	if (error) {
379	printf("a10_mmc: Error in a10_dma_buff_callback function, code = %d\n", error) ;
380	return ;
381	}
382	int i ;
383	struct a10_mmc_softc* sc = (struct a10_mmc_softc*) arg ;
384	sc->a10_dma_nsegs = nsegs ;
385	for(i=0; i<nsegs; i++) {
386	sc->a10_dma_buff_addrs[i] = segs[i].ds_addr ;
387	sc->a10_dma_buff_sizes[i] = segs[i].ds_len ;
388	}
389	}
390
391	static int
198	a10_mmc_detach(device_t dev)	392	a10_mmc_detach(device_t dev)
199	{	393	{
200		394
Lines 217-237 Link Here
217	if (timeout == 0)	412	if (timeout == 0)
218	return (ETIMEDOUT);	413	return (ETIMEDOUT);
219		414
220	/* Set the timeout. */
221	A10_MMC_WRITE_4(sc, A10_MMC_TIMEOUT, 0xffffffff);	415	A10_MMC_WRITE_4(sc, A10_MMC_TIMEOUT, 0xffffffff);
222
223	/* Clear pending interrupts. */
224	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff);	416	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, 0xffffffff);
		417	A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff) ;
225	/* Unmask interrupts. */	418	/* Unmask interrupts. */
226	A10_MMC_WRITE_4(sc, A10_MMC_IMASK,	419	A10_MMC_WRITE_4(sc, A10_MMC_IMASK,
227	A10_MMC_CMD_DONE \| A10_MMC_INT_ERR_BIT \|	420	A10_MMC_CMD_DONE \| A10_MMC_INT_ERR_BIT \|
228	A10_MMC_DATA_OVER \| A10_MMC_AUTOCMD_DONE \|	421	A10_MMC_DATA_OVER \| A10_MMC_AUTOCMD_DONE \|
229	A10_MMC_RX_DATA_REQ \| A10_MMC_TX_DATA_REQ);	422	A10_MMC_RX_DATA_REQ \| A10_MMC_TX_DATA_REQ);
		423	uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) \| A10_MMC_INT_ENABLE \| A10_MMC_ACCESS_BY_AHB ;
		424	temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ;
230	/* Enable interrupts and AHB access. */	425	/* Enable interrupts and AHB access. */
231	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,	426	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL,temp_val) ;
232	A10_MMC_READ_4(sc, A10_MMC_GCTRL) \|
233	A10_MMC_INT_ENABLE \| A10_MMC_ACCESS_BY_AHB);
234
235	return (0);	427	return (0);
236	}	428	}
237		429
Lines 256-262 Link Here
256	sc->a10_req = NULL;	448	sc->a10_req = NULL;
257	sc->a10_intr = 0;	449	sc->a10_intr = 0;
258	sc->a10_resid = 0;	450	sc->a10_resid = 0;
		451	sc->a10_idst = 0 ;
259	sc->a10_intr_wait = 0;	452	sc->a10_intr_wait = 0;
		453	sc->a10_dma_nsegs = 0 ;
260	req->done(req);	454	req->done(req);
261	}	455	}
262		456
Lines 295-301 Link Here
295	a10_mmc_req_done(sc);	489	a10_mmc_req_done(sc);
296	}	490	}
297		491
298	static void	492	static void
299	a10_mmc_timeout(void *arg)	493	a10_mmc_timeout(void *arg)
300	{	494	{
301	struct a10_mmc_softc *sc;	495	struct a10_mmc_softc *sc;
Lines 337-384 Link Here
337	{	531	{
338	struct a10_mmc_softc *sc;	532	struct a10_mmc_softc *sc;
339	struct mmc_data *data;	533	struct mmc_data *data;
340	uint32_t imask, rint;	534	uint32_t imask, rint,idst;
341		535
342	sc = (struct a10_mmc_softc *)arg;	536	sc = (struct a10_mmc_softc *)arg;
343	A10_MMC_LOCK(sc);	537	A10_MMC_LOCK(sc);
344	rint = A10_MMC_READ_4(sc, A10_MMC_RINTR);	538	rint = A10_MMC_READ_4(sc, A10_MMC_RINTR);
345	imask = A10_MMC_READ_4(sc, A10_MMC_IMASK);	539	imask = A10_MMC_READ_4(sc, A10_MMC_IMASK);
346	if (imask == 0 && rint == 0) {	540	idst = A10_MMC_READ_4(sc, A10_MMC_IDST) ;
		541
		542	if (imask == 0 && rint == 0 && idst == 0 ) {
347	A10_MMC_UNLOCK(sc);	543	A10_MMC_UNLOCK(sc);
348	return;	544	return;
349	}	545	}
350	#ifdef DEBUG	546
351	device_printf(sc->a10_dev, "imask: %#x, rint: %#x\n", imask, rint);	547	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint) ;
352	#endif	548	A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst) ;
		549	A10_MMC_WRITE_4(sc, A10_MMC_IMASK, imask) ;
		550	//device_printf(sc->a10_dev, "imask: %#x, rint: %#x, idst: %#x, gctrl: %#x\n", imask, rint,idst, A10_MMC_READ_4(sc, A10_MMC_GCTRL));
353	if (sc->a10_req == NULL) {	551	if (sc->a10_req == NULL) {
354	device_printf(sc->a10_dev,	552	device_printf(sc->a10_dev,
355	"Spurious interrupt - no active request, rint: 0x%08X\n",	553	"Spurious interrupt - no active request, rint: 0x%08X\n",
356	rint);	554	rint);
357	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
358	A10_MMC_UNLOCK(sc);	555	A10_MMC_UNLOCK(sc);
359	return;	556	return;
360	}	557	}
		558
		559	sc->a10_intr \|= rint;
361	if (rint & A10_MMC_INT_ERR_BIT) {	560	if (rint & A10_MMC_INT_ERR_BIT) {
362	device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint);	561	device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint);
363	if (rint & A10_MMC_RESP_TIMEOUT)	562	if (rint & A10_MMC_RESP_TIMEOUT) {
364	sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;	563	sc->a10_req->cmd->error = MMC_ERR_TIMEOUT;
		564	}
365	else	565	else
366	sc->a10_req->cmd->error = MMC_ERR_FAILED;	566	sc->a10_req->cmd->error = MMC_ERR_FAILED;
367	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
368	a10_mmc_req_done(sc);	567	a10_mmc_req_done(sc);
369	A10_MMC_UNLOCK(sc);	568	A10_MMC_UNLOCK(sc);
370	return;	569	return;
371	}	570	}
372		571
373	sc->a10_intr \|= rint;	572	if (idst & A10_MMC_IDMAC_ERROR) {
		573	device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst) ;
		574	sc->a10_req->cmd->error = MMC_ERR_FAILED ;
		575	a10_mmc_req_done(sc) ;
		576	A10_MMC_UNLOCK(sc) ;
		577	return ;
		578	}
		579
		580	if ((idst & A10_MMC_IDMAC_COMPLETE) && ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)) {
		581	if (sc->a10_req->cmd->data->flags & MMC_DATA_WRITE)
		582	bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_POSTWRITE) ;
		583	else
		584	bus_dmamap_sync(sc->a10_dma_buff_tag, sc->a10_dma_buff_map, BUS_DMASYNC_POSTREAD) ;
		585	bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_POSTWRITE) ;
		586	bus_dmamap_unload(sc->a10_dma_buff_tag, sc->a10_dma_buff_map) ;
		587	a10_mmc_req_ok(sc) ;
		588	A10_MMC_UNLOCK(sc) ;
		589	return ;
		590	}
		591
		592	if ((idst)&&(!(idst & A10_MMC_IDMAC_COMPLETE))) {
		593	device_printf(sc->a10_dev, "DMA timeout error!\n") ;
		594	sc->a10_req->cmd->error = MMC_ERR_TIMEOUT ;
		595	a10_mmc_req_done(sc) ;
		596	A10_MMC_UNLOCK(sc) ;
		597	return ;
		598	}
		599
374	data = sc->a10_req->cmd->data;	600	data = sc->a10_req->cmd->data;
		601
375	if (data != NULL && (rint & (A10_MMC_DATA_OVER \|	602	if (data != NULL && (rint & (A10_MMC_DATA_OVER \|
376	A10_MMC_RX_DATA_REQ \| A10_MMC_TX_DATA_REQ)) != 0)	603	A10_MMC_RX_DATA_REQ \| A10_MMC_TX_DATA_REQ)) != 0)
377	a10_mmc_pio_transfer(sc, data);	604	a10_mmc_pio_transfer(sc, data);
378	if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)	605	if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait)
379	a10_mmc_req_ok(sc);	606	a10_mmc_req_ok(sc);
380		607
381	A10_MMC_WRITE_4(sc, A10_MMC_RINTR, rint);
382	A10_MMC_UNLOCK(sc);	608	A10_MMC_UNLOCK(sc);
383	}	609	}
384		610
Lines 388-394 Link Here
388	int blksz;	614	int blksz;
389	struct a10_mmc_softc *sc;	615	struct a10_mmc_softc *sc;
390	struct mmc_command *cmd;	616	struct mmc_command *cmd;
391	uint32_t cmdreg;	617	uint32_t cmdreg ;
392		618
393	sc = device_get_softc(bus);	619	sc = device_get_softc(bus);
394	A10_MMC_LOCK(sc);	620	A10_MMC_LOCK(sc);
Lines 396-401 Link Here
396	A10_MMC_UNLOCK(sc);	622	A10_MMC_UNLOCK(sc);
397	return (EBUSY);	623	return (EBUSY);
398	}	624	}
		625
399	sc->a10_req = req;	626	sc->a10_req = req;
400	cmd = req->cmd;	627	cmd = req->cmd;
401	cmdreg = A10_MMC_START;	628	cmdreg = A10_MMC_START;
Lines 410-417 Link Here
410		637
411	sc->a10_intr = 0;	638	sc->a10_intr = 0;
412	sc->a10_resid = 0;	639	sc->a10_resid = 0;
		640	sc->a10_idst = 0 ;
413	sc->a10_intr_wait = A10_MMC_CMD_DONE;	641	sc->a10_intr_wait = A10_MMC_CMD_DONE;
414	cmd->error = MMC_ERR_NONE;	642	cmd->error = MMC_ERR_NONE;
		643
415	if (cmd->data != NULL) {	644	if (cmd->data != NULL) {
416	sc->a10_intr_wait \|= A10_MMC_DATA_OVER;	645	sc->a10_intr_wait \|= A10_MMC_DATA_OVER;
417	cmdreg \|= A10_MMC_DATA_EXP \| A10_MMC_WAIT_PREOVER;	646	cmdreg \|= A10_MMC_DATA_EXP \| A10_MMC_WAIT_PREOVER;
Lines 419-430 Link Here
419	cmdreg \|= A10_MMC_SEND_AUTOSTOP;	648	cmdreg \|= A10_MMC_SEND_AUTOSTOP;
420	sc->a10_intr_wait \|= A10_MMC_AUTOCMD_DONE;	649	sc->a10_intr_wait \|= A10_MMC_AUTOCMD_DONE;
421	}	650	}
422	if (cmd->data->flags & MMC_DATA_WRITE)	651	if (cmd->data->flags & MMC_DATA_WRITE) {
423	cmdreg \|= A10_MMC_WRITE;	652	cmdreg \|= A10_MMC_WRITE;
		653	}
		654
424	blksz = min(cmd->data->len, MMC_SECTOR_SIZE);	655	blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
425	A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz);	656	A10_MMC_WRITE_4(sc, A10_MMC_BLKSZ, blksz);
426	A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len);	657	A10_MMC_WRITE_4(sc, A10_MMC_BCNTR, cmd->data->len);
		658
		659	if ((sc->a10_use_dma == 1)&&(a10_mmc_can_do_dma(req))) {
		660	uint32_t error = a10_mmc_prepare_dma(sc) ;
		661	if (error == 0) {
		662	A10_MMC_WRITE_4(sc, A10_MMC_IMASK, A10_MMC_READ_4(sc, A10_MMC_IMASK) \| (A10_MMC_TX_DATA_REQ \| A10_MMC_RX_DATA_REQ)) ;
		663	}
		664	else {
		665	uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) \| A10_MMC_INT_ENABLE \| A10_MMC_ACCESS_BY_AHB ;
		666	temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ;
		667	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ;
		668	}
		669	}
		670	else
		671	{
		672	uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) \| A10_MMC_INT_ENABLE \| A10_MMC_ACCESS_BY_AHB ;
		673	temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ;
		674	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ;
		675	}
		676
427	}	677	}
		678	else
		679	{
		680	uint32_t temp_val = A10_MMC_READ_4(sc, A10_MMC_GCTRL) \| A10_MMC_INT_ENABLE \| A10_MMC_ACCESS_BY_AHB ;
		681	temp_val = temp_val & (~A10_MMC_DMA_ENABLE) ;
		682	A10_MMC_WRITE_4(sc, A10_MMC_GCTRL, temp_val) ;
		683	}
428		684
429	A10_MMC_WRITE_4(sc, A10_MMC_CARG, cmd->arg);	685	A10_MMC_WRITE_4(sc, A10_MMC_CARG, cmd->arg);
430	A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg \| cmd->opcode);	686	A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg \| cmd->opcode);
Lines 436-442 Link Here
436	}	692	}
437		693
438	static int	694	static int
439	a10_mmc_read_ivar(device_t bus, device_t child, int which,	695	a10_mmc_read_ivar(device_t bus, device_t child, int which,
440	uintptr_t *result)	696	uintptr_t *result)
441	{	697	{
442	struct a10_mmc_softc *sc;	698	struct a10_mmc_softc *sc;