Attachment #174487 for bug #211699





	sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
	sc->pcie_slot_ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);

	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
		return;

	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
		return;

	/*
	 * A read from the PCIEM_SLOT_CTL_PCC bit (among others) should return
	 * the last value written; however, some chips behave differently,
	 * apparently returning the actual power state.  Save the last value
	 * written and use that saved value instead of reading the register.
	 * Do not save the PCIEM_SLOT_CTL_EIC bit: it is a transient command;
	 * a read should always return zero.
	 */
	ctl = sc->pcie_slot_ctl;
	new = (ctl & ~mask) | val;
	if (new == ctl)
		return;
	if (bootverbose)
		device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
	sc->pcie_slot_ctl = (new & ~PCIEM_SLOT_CTL_EIC);
	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
	    (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
		sc->flags |= PCIB_HOTPLUG_CMD_PENDING;

Lines 132-137 struct pcib_softc Link Here

(-)b/sys/dev/pci/pcib_private.h (+1 lines)
132	uint16_t bridgectl; /* bridge control register */	132	uint16_t bridgectl; /* bridge control register */
133	uint16_t pcie_link_sta;	133	uint16_t pcie_link_sta;
134	uint16_t pcie_slot_sta;	134	uint16_t pcie_slot_sta;
		135	uint16_t pcie_slot_ctl; /* last value written to SLOT_CTL register */
135	uint32_t pcie_link_cap;	136	uint32_t pcie_link_cap;
136	uint32_t pcie_slot_cap;	137	uint32_t pcie_slot_cap;
137	struct resource *pcie_irq;	138	struct resource *pcie_irq;

Return to bug 211699

Lines 932-937 pcib_probe_hotplug(struct pcib_softc *sc) Link Here

(-)b/sys/dev/pci/pci_pci.c (-1 / +11 lines)
932		932
933	sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);	933	sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
934	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);	934	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
		935	sc->pcie_slot_ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
935		936
936	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)	937	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
937	return;	938	return;
Lines 977-989 pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask) Link Here
977	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)	978	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
978	return;	979	return;
979		980
980	ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);	981	/*
		982	* A read from the PCIEM_SLOT_CTL_PCC bit (among others) should return
		983	* the last value written; however, some chips behave differently,
		984	* apparently returning the actual power state. Save the last value
		985	* written and use that saved value instead of reading the register.
		986	* Do not save the PCIEM_SLOT_CTL_EIC bit: it is a transient command;
		987	* a read should always return zero.
		988	*/
		989	ctl = sc->pcie_slot_ctl;
981	new = (ctl & ~mask) \| val;	990	new = (ctl & ~mask) \| val;
982	if (new == ctl)	991	if (new == ctl)
983	return;	992	return;
984	if (bootverbose)	993	if (bootverbose)
985	device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);	994	device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
986	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);	995	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
		996	sc->pcie_slot_ctl = (new & ~PCIEM_SLOT_CTL_EIC);
987	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&	997	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
988	(ctl & new) & PCIEM_SLOT_CTL_CCIE) {	998	(ctl & new) & PCIEM_SLOT_CTL_CCIE) {
989	sc->flags \|= PCIB_HOTPLUG_CMD_PENDING;	999	sc->flags \|= PCIB_HOTPLUG_CMD_PENDING;