Attachment #185729 for bug #221777

Lines 85-90 ig4iic_acpi_attach(device_t dev) Link Here

(-)b/sys/dev/ichiic/ig4_acpi.c (+2 lines)
85	sc = device_get_softc(dev);	85	sc = device_get_softc(dev);
86		86
87	sc->dev = dev;	87	sc->dev = dev;
		88	/* All the HIDs matched are Atom SOCs. */
		89	sc->version = IG4_ATOM;
88	sc->regs_rid = 0;	90	sc->regs_rid = 0;
89	sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,	91	sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
90	&sc->regs_rid, RF_ACTIVE);	92	&sc->regs_rid, RF_ACTIVE);

Lines 117-124 set_controller(ig4iic_softc_t *sc, uint32_t ctl) Link Here

(-)b/sys/dev/ichiic/ig4_iic.c (-21 / +69 lines)
117	reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET \|	117	reg_write(sc, IG4_REG_INTR_MASK, IG4_INTR_STOP_DET \|
118	IG4_INTR_RX_FULL);	118	IG4_INTR_RX_FULL);
119	reg_read(sc, IG4_REG_CLR_INTR);	119	reg_read(sc, IG4_REG_CLR_INTR);
120	} else	120	} else {
121	reg_write(sc, IG4_REG_INTR_MASK, 0);	121	reg_write(sc, IG4_REG_INTR_MASK, 0);
		122	}
122		123
123	reg_write(sc, IG4_REG_I2C_EN, ctl);	124	reg_write(sc, IG4_REG_I2C_EN, ctl);
124	error = IIC_ETIMEOUT;	125	error = IIC_ETIMEOUT;
Lines 134-139 set_controller(ig4iic_softc_t *sc, uint32_t ctl) Link Here
134	else	135	else
135	mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);	136	mtx_sleep(sc, &sc->io_lock, 0, "i2cslv", 1);
136	}	137	}
		138
		139
137	return (error);	140	return (error);
138	}	141	}
139		142
Lines 525-547 ig4iic_attach(ig4iic_softc_t *sc) Link Here
525	mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF);	528	mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF);
526	sx_init(&sc->call_lock, "IG4 call lock");	529	sx_init(&sc->call_lock, "IG4 call lock");
527		530
		531	v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
		532	if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) {
		533	reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE \| IG4_RESTORE_REQUIRED);
		534	reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
		535
		536	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
		537	reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
		538	DELAY(1000);
		539	}
		540
528	v = reg_read(sc, IG4_REG_COMP_TYPE);	541	v = reg_read(sc, IG4_REG_COMP_TYPE);
529	v = reg_read(sc, IG4_REG_COMP_PARAM1);	542	v = reg_read(sc, IG4_REG_COMP_PARAM1);
530	v = reg_read(sc, IG4_REG_GENERAL);	543	v = reg_read(sc, IG4_REG_GENERAL);
531	if ((v & IG4_GENERAL_SWMODE) == 0) {	544	if (sc->version == IG4_ATOM) {
532	v \|= IG4_GENERAL_SWMODE;	545	v = reg_read(sc, IG4_REG_COMP_TYPE);
533	reg_write(sc, IG4_REG_GENERAL, v);	546	}
534	v = reg_read(sc, IG4_REG_GENERAL);	547	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
		548	v = reg_read(sc, IG4_REG_COMP_PARAM1);
		549	v = reg_read(sc, IG4_REG_GENERAL);
		550	/*
		551	* The content of IG4_REG_GENERAL is different for each
		552	* controller version.
		553	*/
		554	if (sc->version == IG4_HASWELL &&
		555	(v & IG4_GENERAL_SWMODE) == 0) {
		556	v \|= IG4_GENERAL_SWMODE;
		557	reg_write(sc, IG4_REG_GENERAL, v);
		558	v = reg_read(sc, IG4_REG_GENERAL);
		559	}
535	}	560	}
536		561
537	v = reg_read(sc, IG4_REG_SW_LTR_VALUE);	562	if (sc->version == IG4_HASWELL) {
538	v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);	563	v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
		564	v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
		565	} else if (sc->version == IG4_SKYLAKE) {
		566	v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
		567	v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
		568	}
539		569
540	v = reg_read(sc, IG4_REG_COMP_VER);	570	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
541	if (v != IG4_COMP_VER) {	571	v = reg_read(sc, IG4_REG_COMP_VER);
542	error = ENXIO;	572	if (v != IG4_COMP_VER) {
543	goto done;	573	error = ENXIO;
		574	goto done;
		575	}
544	}	576	}
		577
545	v = reg_read(sc, IG4_REG_SS_SCL_HCNT);	578	v = reg_read(sc, IG4_REG_SS_SCL_HCNT);
546	v = reg_read(sc, IG4_REG_SS_SCL_LCNT);	579	v = reg_read(sc, IG4_REG_SS_SCL_LCNT);
547	v = reg_read(sc, IG4_REG_FS_SCL_HCNT);	580	v = reg_read(sc, IG4_REG_FS_SCL_HCNT);
Lines 591-598 ig4iic_attach(ig4iic_softc_t *sc) Link Here
591	/*	624	/*
592	* Don't do this, it blows up the PCI config	625	* Don't do this, it blows up the PCI config
593	*/	626	*/
594	reg_write(sc, IG4_REG_RESETS, IG4_RESETS_ASSERT);	627	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
595	reg_write(sc, IG4_REG_RESETS, IG4_RESETS_DEASSERT);	628	reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
		629	reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
		630	}
596	#endif	631	#endif
597		632
598	mtx_lock(&sc->io_lock);	633	mtx_lock(&sc->io_lock);
Lines 727-740 ig4iic_dump(ig4iic_softc_t *sc) Link Here
727	REGDUMP(sc, IG4_REG_DMA_RDLR);	762	REGDUMP(sc, IG4_REG_DMA_RDLR);
728	REGDUMP(sc, IG4_REG_SDA_SETUP);	763	REGDUMP(sc, IG4_REG_SDA_SETUP);
729	REGDUMP(sc, IG4_REG_ENABLE_STATUS);	764	REGDUMP(sc, IG4_REG_ENABLE_STATUS);
730	REGDUMP(sc, IG4_REG_COMP_PARAM1);	765	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
731	REGDUMP(sc, IG4_REG_COMP_VER);	766	REGDUMP(sc, IG4_REG_COMP_PARAM1);
732	REGDUMP(sc, IG4_REG_COMP_TYPE);	767	REGDUMP(sc, IG4_REG_COMP_VER);
733	REGDUMP(sc, IG4_REG_CLK_PARMS);	768	}
734	REGDUMP(sc, IG4_REG_RESETS);	769	if (sc->version == IG4_ATOM) {
735	REGDUMP(sc, IG4_REG_GENERAL);	770	REGDUMP(sc, IG4_REG_COMP_TYPE);
736	REGDUMP(sc, IG4_REG_SW_LTR_VALUE);	771	REGDUMP(sc, IG4_REG_CLK_PARMS);
737	REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);	772	}
		773	if (sc->version == IG4_HASWELL \|\| sc->version == IG4_ATOM) {
		774	REGDUMP(sc, IG4_REG_RESETS_HSW);
		775	REGDUMP(sc, IG4_REG_GENERAL);
		776	} else if (sc->version == IG4_SKYLAKE) {
		777	REGDUMP(sc, IG4_REG_RESETS_SKL);
		778	}
		779	if (sc->version == IG4_HASWELL) {
		780	REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
		781	REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
		782	} else if (sc->version == IG4_SKYLAKE) {
		783	REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
		784	REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
		785	}
738	}	786	}
739	#undef REGDUMP	787	#undef REGDUMP
740		788





static int ig4iic_pci_detach(device_t dev);

#ifndef NELEM
#define NELEM(ary)	(sizeof(ary) / sizeof((ary)[0]))
#endif

static struct {
	uint32_t id;
	char *name;
	enum ig4_vers version;
} intel_i2c_ids[] = {
	/* Haswell */
	{ 0x9c618086, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL },
	{ 0x9c628086, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL },

	/* Braswell */
	{ 0x22c18086, "Intel Braswell Serial I/O I2C Port 1", IG4_HASWELL },
	{ 0x22c28086, "Intel Braswell Serial I/O I2C Port 2", IG4_HASWELL },
	{ 0x22c38086, "Intel Braswell Serial I/O I2C Port 3", IG4_HASWELL },
	{ 0x22c58086, "Intel Braswell Serial I/O I2C Port 4", IG4_HASWELL },
	{ 0x22c68086, "Intel Braswell Serial I/O I2C Port 6", IG4_HASWELL },
	{ 0x22c78086, "Intel Braswell Serial I/O I2C Port 7", IG4_HASWELL },

	/* Skylake-U/Y and Kaby Lake-U/Y CPUs */
	{ 0x9d608086, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE },
	{ 0x9d618086, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE },
	{ 0x9d628086, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE },
	{ 0x9d638086, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE },
	{ 0x9d648086, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE },
	{ 0x9d658086, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE },

	/* Kabylake-H CPUs*/
	{ 0xa1608086, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE },
	{ 0xa1618086, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE },
};

static int
ig4iic_pci_probe(device_t dev)
{
	int i;
	uint32_t device_id;
	const char *name = NULL;

	device_id = pci_get_devid(dev);
	for (i = 0; i < NELEM(intel_i2c_ids); i++) {
		if (intel_i2c_ids[i].id == device_id) {
			name = intel_i2c_ids[i].name;
			device_printf(dev, "found %s\n", name);
			break;
		}
	}

	if (name != NULL) {
		device_set_desc(dev, name);
	} else {
	case PCI_CHIP_BRASWELL_I2C_5:
		device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5");
		break;
	case PCI_CHIP_BRASWELL_I2C_6:
		device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6");
		break;
	case PCI_CHIP_BRASWELL_I2C_7:
		device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7");
		break;
	default:
		return (ENXIO);
	}

	return (BUS_PROBE_DEFAULT);
}


ig4iic_pci_attach(device_t dev)
{
	ig4iic_softc_t *sc = device_get_softc(dev);
	int error, i;
	uint32_t device_id;

	device_id = pci_get_devid(dev);
	for (i = 0; i < NELEM(intel_i2c_ids); i++) {
		if (intel_i2c_ids[i].id == device_id) {
			sc->version = intel_i2c_ids[i].version;
			break;
		}
	}

	sc->dev = dev;
	sc->regs_rid = PCIR_BAR(0);


static devclass_t ig4iic_pci_devclass;

DRIVER_MODULE(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0);
    SI_ORDER_ANY);
MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1);
MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
MODULE_VERSION(ig4iic_pci, 1);





#define IG4_REG_CTL		0x0000	/* RW	Control Register */
#define IG4_REG_TAR_ADD		0x0004	/* RW	Target Address */
#define IG4_REG_HS_MADDR	0x000C	/* RW	High Speed Master Mode Code Address*/
#define IG4_REG_DATA_CMD	0x0010	/* RW	Data Buffer and Command */
#define IG4_REG_SS_SCL_HCNT	0x0014	/* RW	Std Speed clock High Count */
#define IG4_REG_SS_SCL_LCNT	0x0018	/* RW	Std Speed clock Low Count */

#define IG4_REG_CLR_INTR	0x0040	/* RO	Clear Interrupt */
#define IG4_REG_CLR_RX_UNDER	0x0044	/* RO	Clear RX_Under Interrupt */
#define IG4_REG_CLR_RX_OVER	0x0048	/* RO	Clear RX_Over Interrupt */
#define IG4_REG_CLR_TX_OVER	0x004C	/* RO	Clear TX_Over Interrupt */i
#define IG4_REG_CLR_RD_REQ	0x0050	/* RO	Clear RD_Req Interrupt */
#define IG4_REG_CLR_TX_ABORT	0x0054	/* RO	Clear TX_Abort Interrupt */
#define IG4_REG_CLR_RX_DONE	0x0058	/* RO	Clear RX_Done Interrupt */
#define IG4_REG_CLR_ACTIVITY	0x005C	/* RO	Clear Activity Interrupt */
#define IG4_REG_CLR_STOP_DET	0x0060	/* RO	Clear STOP Detection Int */
#define IG4_REG_CLR_START_DET	0x0064	/* RO	Clear START Detection Int */

#define IG4_REG_DMA_TDLR	0x008C	/* RW	DMA Transmit Data Level */
#define IG4_REG_DMA_RDLR	0x0090	/* RW	DMA Receive Data Level */
#define IG4_REG_SDA_SETUP	0x0094	/* RW	SDA Setup */
#define IG4_REG_ACK_GENERAL_CALL 0x0098	/* RW	I2C ACK General Call */
#define IG4_REG_ENABLE_STATUS	0x009C	/* RO	Enable Status */
/* Available at least on Atom SoCs and Haswell mobile. */
#define IG4_REG_COMP_PARAM1	0x00F4	/* RO	Component Parameter */
#define IG4_REG_COMP_VER	0x00F8	/* RO	Component Version */
/* Available at least on Atom SoCs */
#define IG4_REG_COMP_TYPE	0x00FC	/* RO	Probe width/endian? (linux) */
/* Available on Skylake-U/Y and Kaby Lake-U/Y */
#define IG4_REG_RESETS_SKL	0x0204	/* RW	Reset Register */
#define IG4_REG_ACTIVE_LTR_VALUE 0x0210	/* RW	Active LTR Value */
#define IG4_REG_IDLE_LTR_VALUE	0x0214	/* RW	Idle LTR Value */
#define IG4_REG_TX_ACK_COUNT	0x0218	/* RO	TX ACK Count */
#define IG4_REG_RX_BYTE_COUNT	0x021C	/* RO	RX ACK Count */
#define IG4_REG_DEVIDLE_CTRL	0x024C	/* RW	Device Control */
/* Available at least on Atom SoCs */
#define IG4_REG_CLK_PARMS	0x0800	/* RW	Clock Parameters */
/* Available at least on Atom SoCs and Haswell mobile */
#define IG4_REG_RESETS_HSW	0x0804	/* RW	Reset Register */
#define IG4_REG_GENERAL		0x0808	/* RW	General Register */
/* These LTR config registers are at least available on Haswell mobile. */
#define IG4_REG_SW_LTR_VALUE	0x0810	/* RW	SW LTR Value */
#define IG4_REG_AUTO_LTR_VALUE	0x0814	/* RW	Auto LTR Value */


 *	10	(reserved)
 *	11	I2C host controller is in reset.
 */
#define IG4_RESETS_ASSERT_HSW	0x0003
#define IG4_RESETS_DEASSERT_HSW	0x0000

/* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */
#define IG4_RESETS_DEASSERT_SKL	0x0003
#define IG4_RESETS_ASSERT_SKL	0x0000

/* Newer versions of the I2C controller allow to check whether
 * the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL
 * register.
 * 
 * the RESTORE_REQUIRED bit can be cleared by writing 1
 * the DEVICE_IDLE status can be set to put the controller in an idle state
 * */

#define IG4_RESTORE_REQUIRED	0x0008
#define IG4_DEVICE_IDLE		0x0004

/*
 * GENERAL - (RW) General Reigster				22.2.38

Lines 48-53 Link Here

(-)b/sys/dev/ichiic/ig4_var.h (+7 lines)
48		48
49	enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE };	49	enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE };
50		50
		51	enum ig4_vers {
		52	IG4_HASWELL = 0,
		53	IG4_ATOM,
		54	IG4_SKYLAKE,
		55	};
		56
51	struct ig4iic_softc {	57	struct ig4iic_softc {
52	device_t dev;	58	device_t dev;
53	struct intr_config_hook enum_hook;	59	struct intr_config_hook enum_hook;
Lines 58-63 struct ig4iic_softc { Link Here
58	int intr_rid;	64	int intr_rid;
59	void *intr_handle;	65	void *intr_handle;
60	int intr_type;	66	int intr_type;
		67	enum ig4_vers version;
61	enum ig4_op op;	68	enum ig4_op op;
62	int cmd;	69	int cmd;
63	int rnext;	70	int rnext;

Return to bug 221777

Lines 66-111 __FBSDID("$FreeBSD$"); Link Here

(-)b/sys/dev/ichiic/ig4_pci.c (-37 / +61 lines)
66		66
67	static int ig4iic_pci_detach(device_t dev);	67	static int ig4iic_pci_detach(device_t dev);
68		68
69	#define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086	69	#ifndef NELEM
70	#define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086	70	#define NELEM(ary) (sizeof(ary) / sizeof((ary)[0]))
71	#define PCI_CHIP_BRASWELL_I2C_1 0x22c18086	71	#endif
72	#define PCI_CHIP_BRASWELL_I2C_2 0x22c28086	72
73	#define PCI_CHIP_BRASWELL_I2C_3 0x22c38086	73	static struct {
74	#define PCI_CHIP_BRASWELL_I2C_5 0x22c58086	74	uint32_t id;
75	#define PCI_CHIP_BRASWELL_I2C_6 0x22c68086	75	char *name;
76	#define PCI_CHIP_BRASWELL_I2C_7 0x22c78086	76	enum ig4_vers version;
		77	} intel_i2c_ids[] = {
		78	/* Haswell */
		79	{ 0x9c618086, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL },
		80	{ 0x9c628086, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL },
		81
		82	/* Braswell */
		83	{ 0x22c18086, "Intel Braswell Serial I/O I2C Port 1", IG4_HASWELL },
		84	{ 0x22c28086, "Intel Braswell Serial I/O I2C Port 2", IG4_HASWELL },
		85	{ 0x22c38086, "Intel Braswell Serial I/O I2C Port 3", IG4_HASWELL },
		86	{ 0x22c58086, "Intel Braswell Serial I/O I2C Port 4", IG4_HASWELL },
		87	{ 0x22c68086, "Intel Braswell Serial I/O I2C Port 6", IG4_HASWELL },
		88	{ 0x22c78086, "Intel Braswell Serial I/O I2C Port 7", IG4_HASWELL },
		89
		90	/* Skylake-U/Y and Kaby Lake-U/Y CPUs */
		91	{ 0x9d608086, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE },
		92	{ 0x9d618086, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE },
		93	{ 0x9d628086, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE },
		94	{ 0x9d638086, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE },
		95	{ 0x9d648086, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE },
		96	{ 0x9d658086, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE },
		97
		98	/* Kabylake-H CPUs*/
		99	{ 0xa1608086, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE },
		100	{ 0xa1618086, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE },
		101	};
77		102
78	static int	103	static int
79	ig4iic_pci_probe(device_t dev)	104	ig4iic_pci_probe(device_t dev)
80	{	105	{
81	switch(pci_get_devid(dev)) {	106	int i;
82	case PCI_CHIP_LYNXPT_LP_I2C_1:	107	uint32_t device_id;
83	device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-1");	108	const char *name = NULL;
84	break;	109
85	case PCI_CHIP_LYNXPT_LP_I2C_2:	110	device_id = pci_get_devid(dev);
86	device_set_desc(dev, "Intel Lynx Point-LP I2C Controller-2");	111	for (i = 0; i < NELEM(intel_i2c_ids); i++) {
87	break;	112	if (intel_i2c_ids[i].id == device_id) {
88	case PCI_CHIP_BRASWELL_I2C_1:	113	name = intel_i2c_ids[i].name;
89	device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 1");	114	device_printf(dev, "found %s\n", name);
90	break;	115	break;
91	case PCI_CHIP_BRASWELL_I2C_2:	116	}
92	device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 2");	117	}
93	break;	118
94	case PCI_CHIP_BRASWELL_I2C_3:	119	if (name != NULL) {
95	device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 3");	120	device_set_desc(dev, name);
96	break;	121	} else {
97	case PCI_CHIP_BRASWELL_I2C_5:
98	device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 5");
99	break;
100	case PCI_CHIP_BRASWELL_I2C_6:
101	device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 6");
102	break;
103	case PCI_CHIP_BRASWELL_I2C_7:
104	device_set_desc(dev, "Intel Braswell Serial I/O I2C Port 7");
105	break;
106	default:
107	return (ENXIO);	122	return (ENXIO);
108	}	123	}
		124
109	return (BUS_PROBE_DEFAULT);	125	return (BUS_PROBE_DEFAULT);
110	}	126	}
111		127
Lines 113-119 static int Link Here
113	ig4iic_pci_attach(device_t dev)	129	ig4iic_pci_attach(device_t dev)
114	{	130	{
115	ig4iic_softc_t *sc = device_get_softc(dev);	131	ig4iic_softc_t *sc = device_get_softc(dev);
116	int error;	132	int error, i;
		133	uint32_t device_id;
		134
		135	device_id = pci_get_devid(dev);
		136	for (i = 0; i < NELEM(intel_i2c_ids); i++) {
		137	if (intel_i2c_ids[i].id == device_id) {
		138	sc->version = intel_i2c_ids[i].version;
		139	break;
		140	}
		141	}
117		142
118	sc->dev = dev;	143	sc->dev = dev;
119	sc->regs_rid = PCIR_BAR(0);	144	sc->regs_rid = PCIR_BAR(0);
Lines 194-201 static driver_t ig4iic_pci_driver = { Link Here
194		219
195	static devclass_t ig4iic_pci_devclass;	220	static devclass_t ig4iic_pci_devclass;
196		221
197	DRIVER_MODULE_ORDERED(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0,	222	DRIVER_MODULE(ig4iic_pci, pci, ig4iic_pci_driver, ig4iic_pci_devclass, 0, 0);
198	SI_ORDER_ANY);
199	MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1);	223	MODULE_DEPEND(ig4iic_pci, pci, 1, 1, 1);
200	MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);	224	MODULE_DEPEND(ig4iic_pci, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
201	MODULE_VERSION(ig4iic_pci, 1);	225	MODULE_VERSION(ig4iic_pci, 1);

Lines 78-83 Link Here

(-)b/sys/dev/ichiic/ig4_reg.h (-4 / +35 lines)
78		78
79	#define IG4_REG_CTL 0x0000 /* RW Control Register */	79	#define IG4_REG_CTL 0x0000 /* RW Control Register */
80	#define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */	80	#define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */
		81	#define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/
81	#define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */	82	#define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */
82	#define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */	83	#define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */
83	#define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */	84	#define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */
Lines 91-98 Link Here
91	#define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */	92	#define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */
92	#define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */	93	#define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */
93	#define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */	94	#define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */
94	#define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */	95	#define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */i
		96	#define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */
95	#define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */	97	#define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */
		98	#define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */
96	#define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */	99	#define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */
97	#define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */	100	#define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */
98	#define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */	101	#define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */
Lines 108-120 Link Here
108	#define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */	111	#define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */
109	#define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */	112	#define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */
110	#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */	113	#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */
		114	#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */
111	#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */	115	#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */
		116	/* Available at least on Atom SoCs and Haswell mobile. */
112	#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */	117	#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */
113	#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */	118	#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */
		119	/* Available at least on Atom SoCs */
114	#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */	120	#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */
		121	/* Available on Skylake-U/Y and Kaby Lake-U/Y */
		122	#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */
		123	#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */
		124	#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */
		125	#define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */
		126	#define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */
		127	#define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */
		128	/* Available at least on Atom SoCs */
115	#define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */	129	#define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */
116	#define IG4_REG_RESETS 0x0804 /* RW Reset Register */	130	/* Available at least on Atom SoCs and Haswell mobile */
		131	#define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */
117	#define IG4_REG_GENERAL 0x0808 /* RW General Register */	132	#define IG4_REG_GENERAL 0x0808 /* RW General Register */
		133	/* These LTR config registers are at least available on Haswell mobile. */
118	#define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */	134	#define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */
119	#define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */	135	#define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */
120		136
Lines 566-573 Link Here
566	* 10 (reserved)	582	* 10 (reserved)
567	* 11 I2C host controller is in reset.	583	* 11 I2C host controller is in reset.
568	*/	584	*/
569	#define IG4_RESETS_ASSERT 0x0003	585	#define IG4_RESETS_ASSERT_HSW 0x0003
570	#define IG4_RESETS_DEASSERT 0x0000	586	#define IG4_RESETS_DEASSERT_HSW 0x0000
		587
		588	/* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */
		589	#define IG4_RESETS_DEASSERT_SKL 0x0003
		590	#define IG4_RESETS_ASSERT_SKL 0x0000
		591
		592	/* Newer versions of the I2C controller allow to check whether
		593	* the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL
		594	* register.
		595	*
		596	* the RESTORE_REQUIRED bit can be cleared by writing 1
		597	* the DEVICE_IDLE status can be set to put the controller in an idle state
		598	* */
		599
		600	#define IG4_RESTORE_REQUIRED 0x0008
		601	#define IG4_DEVICE_IDLE 0x0004
571		602
572	/*	603	/*
573	* GENERAL - (RW) General Reigster 22.2.38	604	* GENERAL - (RW) General Reigster 22.2.38