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Lines 755-768
ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
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| 755 |
int error, nsegs; |
755 |
int error, nsegs; |
| 756 |
struct bus_dma_segment seg; |
756 |
struct bus_dma_segment seg; |
| 757 |
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757 |
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| 758 |
/* |
758 |
if ((sc->fectype & FECFLAG_AVB) == 0) { |
| 759 |
* We need to leave at least ETHER_ALIGN bytes free at the beginning of |
759 |
/* |
| 760 |
* the buffer to allow the data to be re-aligned after receiving it (by |
760 |
* The RACC[SHIFT16] feature is not used. So, we need to leave |
| 761 |
* copying it backwards ETHER_ALIGN bytes in the same buffer). We also |
761 |
* at least ETHER_ALIGN bytes free at the beginning of the |
| 762 |
* have to ensure that the beginning of the buffer is aligned to the |
762 |
* buffer to allow the data to be re-aligned after receiving it |
| 763 |
* hardware's requirements. |
763 |
* (by copying it backwards ETHER_ALIGN bytes in the same |
| 764 |
*/ |
764 |
* buffer). We also have to ensure that the beginning of the |
| 765 |
m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); |
765 |
* buffer is aligned to the hardware's requirements. |
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766 |
*/ |
| 767 |
m_adj(m, roundup(ETHER_ALIGN, sc->rxbuf_align)); |
| 768 |
} |
| 766 |
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769 |
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| 767 |
error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
770 |
error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, |
| 768 |
m, &seg, &nsegs, 0); |
771 |
m, &seg, &nsegs, 0); |
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Lines 795-801
ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
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| 795 |
{ |
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{ |
| 796 |
struct mbuf *m, *newmbuf; |
799 |
struct mbuf *m, *newmbuf; |
| 797 |
struct ffec_bufmap *bmap; |
800 |
struct ffec_bufmap *bmap; |
| 798 |
uint8_t *dst, *src; |
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| 799 |
int error; |
801 |
int error; |
| 800 |
|
802 |
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| 801 |
/* |
803 |
/* |
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Lines 839-848
ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
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| 839 |
m->m_pkthdr.len = len; |
841 |
m->m_pkthdr.len = len; |
| 840 |
m->m_pkthdr.rcvif = sc->ifp; |
842 |
m->m_pkthdr.rcvif = sc->ifp; |
| 841 |
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843 |
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| 842 |
src = mtod(m, uint8_t*); |
844 |
if ((sc->fectype & FECFLAG_AVB)) { |
| 843 |
dst = src - ETHER_ALIGN; |
845 |
/* We use the RACC[SHIFT16] feature */ |
| 844 |
bcopy(src, dst, len); |
846 |
m->m_data = mtod(m, uint8_t *) + 2; |
| 845 |
m->m_data = dst; |
847 |
} else { |
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|
848 |
uint8_t *dst, *src; |
| 849 |
|
| 850 |
src = mtod(m, uint8_t*); |
| 851 |
dst = src - ETHER_ALIGN; |
| 852 |
bcopy(src, dst, len); |
| 853 |
m->m_data = dst; |
| 854 |
} |
| 846 |
sc->ifp->if_input(sc->ifp, m); |
855 |
sc->ifp->if_input(sc->ifp, m); |
| 847 |
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856 |
|
| 848 |
FFEC_LOCK(sc); |
857 |
FFEC_LOCK(sc); |
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Lines 1216-1221
ffec_init_locked(struct ffec_softc *sc)
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| 1216 |
ffec_clear_stats(sc); |
1225 |
ffec_clear_stats(sc); |
| 1217 |
WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); |
1226 |
WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS); |
| 1218 |
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1227 |
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|
1228 |
if ((sc->fectype & FECFLAG_AVB) != 0) { |
| 1229 |
/* |
| 1230 |
* RACC - Receive Accelerator Function Configuration. |
| 1231 |
*/ |
| 1232 |
regval = RD4(sc, FEC_RACC_REG); |
| 1233 |
WR4(sc, FEC_RACC_REG, regval | FEC_RACC_SHIFT16); |
| 1234 |
} |
| 1235 |
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| 1219 |
/* |
1236 |
/* |
| 1220 |
* ECR - Ethernet control register. |
1237 |
* ECR - Ethernet control register. |
| 1221 |
* |
1238 |
* |
| 1222 |
- |
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