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Lines 80-85
static int ig4iic_pci_detach(device_t dev);
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| 80 |
#define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 |
80 |
#define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 |
| 81 |
#define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 |
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#define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 |
| 82 |
#define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 |
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#define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 |
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83 |
#define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 |
| 84 |
#define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 |
| 83 |
#define PCI_CHIP_APL_I2C_0 0x5aac8086 |
85 |
#define PCI_CHIP_APL_I2C_0 0x5aac8086 |
| 84 |
#define PCI_CHIP_APL_I2C_1 0x5aae8086 |
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#define PCI_CHIP_APL_I2C_1 0x5aae8086 |
| 85 |
#define PCI_CHIP_APL_I2C_2 0x5ab08086 |
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#define PCI_CHIP_APL_I2C_2 0x5ab08086 |
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Lines 110-115
static struct ig4iic_pci_device ig4iic_pci_devices[] = {
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| 110 |
{ PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, |
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{ PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, |
| 111 |
{ PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, |
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{ PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, |
| 112 |
{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, |
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{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, |
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115 |
{ PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, |
| 116 |
{ PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, |
| 113 |
{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, |
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{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, |
| 114 |
{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, |
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{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, |
| 115 |
{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, |
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{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, |