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(-)sys/dev/ichwd/ichwd.c (-4 / +62 lines)
Lines 76-81 __FBSDID("$FreeBSD$"); Link Here
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#include <dev/ichwd/ichwd.h>
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#include <dev/ichwd/ichwd.h>
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#include <x86/pci_cfgreg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pci_private.h>
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static struct ichwd_device ichwd_devices[] = {
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static struct ichwd_device ichwd_devices[] = {
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	{ DEVICEID_82801AA,  "Intel 82801AA watchdog timer",	1, 1 },
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	{ DEVICEID_82801AA,  "Intel 82801AA watchdog timer",	1, 1 },
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	{ DEVICEID_82801AB,  "Intel 82801AB watchdog timer",	1, 1 },
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	{ DEVICEID_82801AB,  "Intel 82801AB watchdog timer",	1, 1 },
Lines 291-296 static struct ichwd_device ichwd_devices[] = { Link Here
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static struct ichwd_device ichwd_smb_devices[] = {
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static struct ichwd_device ichwd_smb_devices[] = {
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	{ DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer",		10, 4 },
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	{ DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer",		10, 4 },
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	{ DEVICEID_SRPTLP_SMB,    "Sunrise Point-LP watchdog timer",	10, 4 },
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	{ 0, NULL, 0, 0 },
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	{ 0, NULL, 0, 0 },
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};
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};
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Lines 309-314 static devclass_t ichwd_devclass; Link Here
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/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
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/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
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#define ichwd_read_pmc_4(sc, off) \
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#define ichwd_read_pmc_4(sc, off) \
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	bus_read_4((sc)->gcs_res, (off))
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	bus_read_4((sc)->gcs_res, (off))
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#define ichwd_read_gc_4(sc, off) \
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	bus_read_4((sc)->gc_res, (off))
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#define ichwd_write_tco_1(sc, off, val) \
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#define ichwd_write_tco_1(sc, off, val) \
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	bus_write_1((sc)->tco_res, (off), (val))
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	bus_write_1((sc)->tco_res, (off), (val))
Lines 323-328 static devclass_t ichwd_devclass; Link Here
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/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
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/* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */
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#define ichwd_write_pmc_4(sc, off, val) \
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#define ichwd_write_pmc_4(sc, off, val) \
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	bus_write_4((sc)->gcs_res, (off), (val))
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	bus_write_4((sc)->gcs_res, (off), (val))
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#define ichwd_write_gc_4(sc, off, val) \
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	bus_write_4((sc)->gc_res, (off), (val))
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#define ichwd_verbose_printf(dev, ...) \
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#define ichwd_verbose_printf(dev, ...) \
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	do {						\
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	do {						\
Lines 495-503 ichwd_clear_noreboot(struct ichwd_softc *sc) Link Here
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			rc = EIO;
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			rc = EIO;
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		break;
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		break;
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	case 4:
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	case 4:
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		/*
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		status = ichwd_read_gc_4(sc, 0);
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		 * TODO.  This needs access to a hidden PCI device at 31:1.
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		status &= ~SMB_GC_NO_REBOOT;
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		 */
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		ichwd_write_gc_4(sc, 0, status);
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		status = ichwd_read_gc_4(sc, 0);
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		if (status & SMB_GC_NO_REBOOT)
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			rc = EIO;
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		break;
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		break;
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	default:
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	default:
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		ichwd_verbose_printf(sc->device,
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		ichwd_verbose_printf(sc->device,
Lines 611-616 ichwd_identify(driver_t *driver, device_t parent) Link Here
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	struct ichwd_device *id_p;
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	struct ichwd_device *id_p;
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	device_t ich, smb;
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	device_t ich, smb;
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	device_t dev;
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	device_t dev;
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	uint64_t base_address64;
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	uint32_t base_address;
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	uint32_t base_address;
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	uint32_t ctl;
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	uint32_t ctl;
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	int rc;
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	int rc;
Lines 671-676 ichwd_identify(driver_t *driver, device_t parent) Link Here
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			    "Can not set TCO v%d I/O resource (err = %d)\n",
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			    "Can not set TCO v%d I/O resource (err = %d)\n",
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			    id_p->tco_version, rc);
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			    id_p->tco_version, rc);
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		}
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		}
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		/*
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		 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that
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		 * we can discover the base address of Private Configuration
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		 * Space via the bridge's BAR.
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		 * Then hide back the bridge.
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		 */
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		pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1);
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		base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4);
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		base_address64 <<= 32;
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		base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4);
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		base_address64 &= ~0xfull;
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		pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1);
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		/*
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		 * No Reboot bit is in General Control register, offset 0xc,
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		 * within the SMBus target port, ID 0xc6.
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		 */
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		base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG);
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		rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64,
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		    SMB_GC_SIZE);
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		if (rc != 0) {
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			ichwd_verbose_printf(dev,
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			    "Can not set TCO v%d PCR I/O resource (err = %d)\n",
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			    id_p->tco_version, rc);
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		}
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		break;
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		break;
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	default:
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	default:
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		ichwd_verbose_printf(dev,
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		ichwd_verbose_printf(dev,
Lines 723-728 ichwd_smb_attach(device_t dev) Link Here
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		return (ENXIO);
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		return (ENXIO);
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	}
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	}
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	/*
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	 * Allocate General Control I/O register in PCH
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	 * Private Configuration Space (PCR).
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	 */
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	sc->gc_rid = 1;
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	sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid,
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	    RF_ACTIVE | RF_SHAREABLE);
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	if (sc->gc_res == NULL) {
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		device_printf(dev, "unable to reserve hidden P2SB registers\n");
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		return (ENXIO);
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	}
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	/* Get ACPI base address. */
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	/* Get ACPI base address. */
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	isab = device_get_parent(device_get_parent(dev));
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	isab = device_get_parent(device_get_parent(dev));
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	pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2);
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	pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2);
Lines 737-743 ichwd_smb_attach(device_t dev) Link Here
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	}
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	}
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	/* Allocate SMI control I/O register space. */
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	/* Allocate SMI control I/O register space. */
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	sc->smi_rid = 1;
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	sc->smi_rid = 2;
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	sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
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	sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
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	    acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN,
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	    acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN,
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	    RF_ACTIVE | RF_SHAREABLE);
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	    RF_ACTIVE | RF_SHAREABLE);
Lines 854-859 ichwd_attach(device_t dev) Link Here
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	if (sc->gcs_res != NULL)
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	if (sc->gcs_res != NULL)
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		bus_release_resource(sc->ich, SYS_RES_MEMORY,
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		bus_release_resource(sc->ich, SYS_RES_MEMORY,
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		    sc->gcs_rid, sc->gcs_res);
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		    sc->gcs_rid, sc->gcs_res);
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	if (sc->gc_res != NULL)
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		bus_release_resource(dev, SYS_RES_MEMORY,
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		    sc->gc_rid, sc->gc_res);
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	return (ENXIO);
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	return (ENXIO);
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}
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}
Lines 889-894 ichwd_detach(device_t dev) Link Here
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	if (sc->gcs_res)
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	if (sc->gcs_res)
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		bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid,
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		bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid,
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		    sc->gcs_res);
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		    sc->gcs_res);
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	if (sc->gc_res)
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		bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid,
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		    sc->gc_res);
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	return (0);
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	return (0);
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}
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}
(-)sys/dev/ichwd/ichwd.h (+16 lines)
Lines 59-64 struct ichwd_softc { Link Here
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	int			 gcs_rid;
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	int			 gcs_rid;
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	struct resource		*gcs_res;
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	struct resource		*gcs_res;
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	int			 gc_rid;
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	struct resource		*gc_res;
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	eventhandler_tag	 ev_tag;
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	eventhandler_tag	 ev_tag;
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};
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};
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Lines 273-278 struct ichwd_softc { Link Here
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#define	DEVICEID_WCPT_LP7	0x9cc7
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#define	DEVICEID_WCPT_LP7	0x9cc7
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#define	DEVICEID_WCPT_LP9	0x9cc9
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#define	DEVICEID_WCPT_LP9	0x9cc9
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#define	DEVICEID_LEWISBURG_SMB	0xa1a3
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#define	DEVICEID_LEWISBURG_SMB	0xa1a3
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#define	DEVICEID_SRPTLP_SMB	0x9d23
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/* ICH LPC Interface Bridge Registers (ICH5 and older) */
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/* ICH LPC Interface Bridge Registers (ICH5 and older) */
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#define	ICH_GEN_STA		0xd4
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#define	ICH_GEN_STA		0xd4
Lines 300-305 struct ichwd_softc { Link Here
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#define	ICH_TCOCTL_TCO_BASE_EN		0x0100  /* TCO Base decoding enabled */
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#define	ICH_TCOCTL_TCO_BASE_EN		0x0100  /* TCO Base decoding enabled */
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#define	ICH_TCOCTL_TCO_BASE_LOCK	0x0001  /* TCOBASE is locked */
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#define	ICH_TCOCTL_TCO_BASE_LOCK	0x0001  /* TCOBASE is locked */
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/*
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 * Configuration registers in Sunrise Point and Lewisburg PCH Sideband Interface
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 * and Private Configuration Space.
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 */
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#define	SBREG_BAR		0x10
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#define	SMB_GC_REG		0xc
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#define	SMB_GC_SIZE		4
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#define	SMB_GC_NO_REBOOT	0x2
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#define	SMB_PORT_ID		0xc6
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#define	PCR_PORTID_SHIFT	16
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#define	PCR_REG_OFF(pid, reg)	(((pid) << PCR_PORTID_SHIFT) | (reg))
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/* register names and locations (relative to PMBASE) */
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/* register names and locations (relative to PMBASE) */
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#define	SMI_BASE		0x30 /* base address for SMI registers */
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#define	SMI_BASE		0x30 /* base address for SMI registers */
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#define	SMI_LEN			0x08
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#define	SMI_LEN			0x08

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