Attachment #205289 for bug #238769

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# $FreeBSD: head/devel/psptoolchain-gcc-stage1/Makefile 499897 2019-04-24 19:15:05Z jbeich $

PORTNAME=		gcc
PORTVERSION=		4.9.3
PORTREVISION?=		0
CATEGORIES=		devel
MASTER_SITES=		GCC
PKGNAMEPREFIX=		psptoolchain-
PKGNAMESUFFIX?=		-stage1

MAINTAINER=		tphilipp@potion-studios.com
COMMENT=		PlayStation Portable development toolchain ${PORTNAME}

LICENSE=		GPLv3

ONLY_FOR_ARCHS=		amd64 i386 powerpc64

LIB_DEPENDS=		libgmp.so:math/gmp \

			psp-strings:devel/psptoolchain-binutils \
			psp-strip:devel/psptoolchain-binutils

USES+=			gmake libtool tar:bzip2

MAKE_ENV+=		PATH=${LOCALBASE}/${PSP_GCC_STAGE_PREFIX}/bin:${PREFIX}/bin:${PATH}
HAS_CONFIGURE=		yes

			--with-ld=${LOCALBASE}/bin/psp-ld \
			--with-as=${LOCALBASE}/bin/psp-as \
			--mandir=${PREFIX}/man
CFLAGS+=		-Wno-reserved-user-defined-literal
SSP_CFLAGS?=		-fstack-protector # XXX -strong isn't supported by GCC < 4.9

# make sure xgcc doesn't get any -march=... from env C(XX)?FLAGS (e.g. set by CPUTYPE in make.conf); also "disable" info file gen
CONFIGURE_ENV+=		CFLAGS_FOR_TARGET="${CFLAGS:C/(^|[[:space:]])-march=[^[:space:]]*//g} ${XGCC_FLAGS}" \
			CXXFLAGS_FOR_TARGET="${CXXFLAGS:C/(^|[[:space:]])-march=[^[:space:]]*//g} ${XGCC_FLAGS}" \
			MAKEINFO=true

# Don't install any documentation for psptoolchain's gcc stage 1 - makes no sense.

Lines 1-2 Link Here

(-)devel/psptoolchain-gcc-stage1/distinfo (-2 / +3 lines)
1	SHA256 (gcc-4.6.2.tar.bz2) = 60b05463dfe18d40d68fb8a71b25b408a01f86cc6ceaf5e6b22238b6b0f450c2	1	TIMESTAMP = 1559855654
2	SIZE (gcc-4.6.2.tar.bz2) = 71995338	2	SHA256 (gcc-4.9.3.tar.bz2) = 2332b2a5a321b57508b9031354a8503af6fdfb868b8c1748d33028d100a8b67e
		3	SIZE (gcc-4.9.3.tar.bz2) = 90006707




--- config.sub.orig	2013-10-01 16:50:56 UTC
+++ config.sub
@@ -289,6 +289,7 @@ case $basic_machine in
 	| mipsisa64sb1 | mipsisa64sb1el \
 	| mipsisa64sr71k | mipsisa64sr71kel \
 	| mipsr5900 | mipsr5900el \
 	| mipstx39 | mipstx39el \
+	| mipsallegrex | mipsallegrexel \
 	| mn10200 | mn10300 \
 	| moxie \
 	| mt \
@@ -408,6 +409,7 @@ case $basic_machine in
 	| mipsisa64sb1-* | mipsisa64sb1el-* \
 	| mipsisa64sr71k-* | mipsisa64sr71kel-* \
 	| mipsr5900-* | mipsr5900el-* \
 	| mipstx39-* | mipstx39el-* \
+	| mipsallegrex-* | mipsallegrexel-* \
 	| mmix-* \
 	| mt-* \
 	| msp430-* \
@@ -809,6 +811,10 @@ case $basic_machine in
 	*mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*)
 		basic_machine=m68k-atari
 		os=-mint
+		;;
+	psp)
+		basic_machine=mipsallegrexel-psp
+		os=-elf
 		;;
 	mips3*-*)
 		basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
 		;;




--- ./gcc/config/mips/allegrex.md.orig	2012-01-21 14:11:18.000000000 +0000
+++ ./gcc/config/mips/allegrex.md	2012-01-21 14:11:18.000000000 +0000
@@ -0,0 +1,191 @@
+;; Sony ALLEGREX instructions.
+;; Copyright (C) 2005 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+(define_c_enum "unspec" [
+  UNSPEC_WSBH
+  UNSPEC_CLO
+  UNSPEC_CTO
+  UNSPEC_CACHE
+  UNSPEC_CEIL_W_S
+  UNSPEC_FLOOR_W_S
+  UNSPEC_ROUND_W_S
+])
+
+;; Multiply Add and Subtract.
+;; Note: removed clobbering for madd and msub (testing needed)
+
+(define_insn "allegrex_madd"
+  [(set (match_operand:SI 0 "register_operand" "+l")
+       (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+             (match_operand:SI 2 "register_operand" "d"))
+        (match_dup 0)))]
+  "TARGET_ALLEGREX"
+  "madd\t%1,%2"
+  [(set_attr "type"    "imadd")
+   (set_attr "mode"    "SI")])
+
+(define_insn "allegrex_msub"
+  [(set (match_operand:SI 0 "register_operand" "+l")
+       (minus:SI (match_dup 0)
+         (mult:SI (match_operand:SI 1 "register_operand" "d")
+              (match_operand:SI 2 "register_operand" "d"))))]
+  "TARGET_ALLEGREX"
+  "msub\t%1,%2"
+  [(set_attr "type"    "imadd")
+   (set_attr "mode"    "SI")])
+
+
+;; Min and max.
+
+(define_insn "sminsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (smin:SI (match_operand:SI 1 "register_operand" "d")
+                 (match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_ALLEGREX"
+  "min\t%0,%1,%2"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+(define_insn "smaxsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (smax:SI (match_operand:SI 1 "register_operand" "d")
+                 (match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_ALLEGREX"
+  "max\t%0,%1,%2"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+
+;; Extended shift instructions.
+
+(define_insn "allegrex_bitrev"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+   (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+          UNSPEC_BITREV))]
+  "TARGET_ALLEGREX"
+  "bitrev\t%0,%1"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+(define_insn "allegrex_wsbh"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+   (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+          UNSPEC_WSBH))]
+  "TARGET_ALLEGREX"
+  "wsbh\t%0,%1"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+(define_insn "bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+   (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
+  "TARGET_ALLEGREX"
+  "wsbw\t%0,%1"
+  [(set_attr "type"    "shift")
+   (set_attr "mode"    "SI")])
+
+
+;; Count leading ones, count trailing zeros, and count trailing ones (clz is
+;; already defined).
+
+(define_insn "allegrex_clo"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+       (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+          UNSPEC_CLO))]
+  "TARGET_ALLEGREX"
+  "clo\t%0,%1"
+  [(set_attr "type"    "clz")
+   (set_attr "mode"    "SI")])
+
+(define_expand "ctzsi2"
+  [(set (match_operand:SI 0 "register_operand")
+       (ctz:SI (match_operand:SI 1 "register_operand")))]
+  "TARGET_ALLEGREX"
+{
+  rtx r1;
+
+  r1 = gen_reg_rtx (SImode);
+  emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+  emit_insn (gen_clzsi2 (operands[0], r1));
+  DONE;
+})
+
+(define_expand "allegrex_cto"
+  [(set (match_operand:SI 0 "register_operand")
+       (unspec:SI [(match_operand:SI 1 "register_operand")]
+          UNSPEC_CTO))]
+  "TARGET_ALLEGREX"
+{
+  rtx r1;
+
+  r1 = gen_reg_rtx (SImode);
+  emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+  emit_insn (gen_allegrex_clo (operands[0], r1));
+  DONE;
+})
+
+
+;; Misc.
+
+(define_insn "allegrex_sync"
+  [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+  "TARGET_ALLEGREX"
+  "sync"
+  [(set_attr "type"    "unknown")
+   (set_attr "mode"    "none")])
+
+(define_insn "allegrex_cache"
+  [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
+            (match_operand:SI 1 "register_operand" "d")]
+           UNSPEC_CACHE)]
+  "TARGET_ALLEGREX"
+  "cache\t%0,0(%1)"
+  [(set_attr "type"    "unknown")
+   (set_attr "mode"    "none")])
+
+
+;; Floating-point builtins.
+
+(define_insn "allegrex_ceil_w_s"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+          UNSPEC_CEIL_W_S))]
+  "TARGET_ALLEGREX"
+  "ceil.w.s\t%0,%1"
+  [(set_attr "type"    "fcvt")
+   (set_attr "mode"    "SF")])
+
+(define_insn "allegrex_floor_w_s"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+          UNSPEC_FLOOR_W_S))]
+  "TARGET_ALLEGREX"
+  "floor.w.s\t%0,%1"
+  [(set_attr "type"    "fcvt")
+   (set_attr "mode"    "SF")])
+
+(define_insn "allegrex_round_w_s"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+          UNSPEC_ROUND_W_S))]
+  "TARGET_ALLEGREX"
+  "round.w.s\t%0,%1"
+  [(set_attr "type"    "fcvt")
+   (set_attr "mode"    "SF")])




--- ./gcc/config/mips/mips-ftypes.def.orig	2009-02-20 15:20:38.000000000 +0000
+++ ./gcc/config/mips/mips-ftypes.def	2012-01-21 14:11:18.000000000 +0000
@@ -53,9 +53,12 @@
 
 DEF_MIPS_FTYPE (2, (SI, DI, SI))
 DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
+DEF_MIPS_FTYPE (1, (SI, HI))
+DEF_MIPS_FTYPE (1, (SI, SF))
 DEF_MIPS_FTYPE (1, (SI, SI))
 DEF_MIPS_FTYPE (2, (SI, SI, SI))
 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
+DEF_MIPS_FTYPE (1, (SI, QI))
 DEF_MIPS_FTYPE (1, (SI, V2HI))
 DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
 DEF_MIPS_FTYPE (1, (SI, V4QI))
@@ -124,3 +127,4 @@
 DEF_MIPS_FTYPE (2, (VOID, SI, SI))
 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
+DEF_MIPS_FTYPE (1, (VOID, VOID))




--- ./gcc/config/mips/mips.c.orig	2011-05-29 17:48:14.000000000 +0000
+++ ./gcc/config/mips/mips.c	2012-01-21 14:11:18.000000000 +0000
@@ -239,7 +239,12 @@
   MIPS_BUILTIN_CMP_SINGLE,
 
   /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
-  MIPS_BUILTIN_BPOSGE32
+  MIPS_BUILTIN_BPOSGE32,
+
+  /* The builtin corresponds to the ALLEGREX cache instruction.  Operand 0
+     is the function code (must be less than 32) and operand 1 is the base
+     address.  */
+  MIPS_BUILTIN_CACHE
 };
 
 /* Invoke MACRO (COND) for each C.cond.fmt condition.  */
@@ -516,6 +521,10 @@
    normal branch.  */
 static bool mips_branch_likely;
 
+/* Preferred stack boundary for proper stack vars alignment */
+unsigned int mips_preferred_stack_boundary;
+unsigned int mips_preferred_stack_align;
+
 /* The current instruction-set architecture.  */
 enum processor mips_arch;
 const struct mips_cpu_info *mips_arch_info;
@@ -691,6 +700,7 @@
 
   /* MIPS II processors.  */
   { "r6000", PROCESSOR_R6000, 2, 0 },
+  { "allegrex", PROCESSOR_ALLEGREX, 2, 0 },
 
   /* MIPS III processors.  */
   { "r4000", PROCESSOR_R4000, 3, 0 },
@@ -969,6 +979,9 @@
 		     1,           /* branch_cost */
 		     4            /* memory_latency */
   },
+  { /* Allegrex */
+    DEFAULT_COSTS
+  },
   { /* Loongson-2E */
     DEFAULT_COSTS
   },
@@ -12605,6 +12618,7 @@
 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
+AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
 
 /* Construct a mips_builtin_description from the given arguments.
 
@@ -12701,6 +12715,30 @@
   MIPS_BUILTIN (bposge, f, "bposge" #VALUE,				\
 		MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
 
+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
+   FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields.  */
+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,        \
+    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
+/* Same as the above, but mapped to an instruction that doesn't share the
+   NAME.  NAME is the name of the builtin without the builtin prefix.  */
+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+  { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME,             \
+    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
+   CODE_FOR_allegrex_<INSN>.  FUNCTION_TYPE and TARGET_FLAGS are
+   builtin_description fields.  */
+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)   \
+  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
+    MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
+/* Define a builtin with a specific function TYPE.  */
+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS)  \
+  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
+    MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
    for instruction CODE_FOR_loongson_<INSN>.  FUNCTION_TYPE is a
    builtin_description field.  */
@@ -12945,6 +12983,40 @@
   DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
   DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
 
+/* Builtin functions for the Sony ALLEGREX processor.
+
+   These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
+   to maintain compatibility with Sony's ALLEGREX GCC port.
+
+   Some of the builtins may seem redundant, but they are the same as the
+   builtins defined in the Sony compiler.  I chose to map redundant and
+   trivial builtins to the original instruction instead of creating
+   duplicate patterns specifically for the ALLEGREX (as Sony does).  */
+
+  DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+  DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+  DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
+  SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
+
+  DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
+
   /* Builtin functions for ST Microelectronics Loongson-2E/2F cores.  */
   LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
   LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
@@ -13096,6 +13168,8 @@
 /* Standard mode-based argument types.  */
 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
 #define MIPS_ATYPE_SI intSI_type_node
+#define MIPS_ATYPE_HI intHI_type_node
+#define MIPS_ATYPE_QI intQI_type_node
 #define MIPS_ATYPE_USI unsigned_intSI_type_node
 #define MIPS_ATYPE_DI intDI_type_node
 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
@@ -13270,6 +13344,9 @@
 
   switch (opno)
     {
+    case 0:
+      emit_insn (GEN_FCN (icode) (0));
+      break;
     case 2:
       emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
       break;
@@ -13439,6 +13516,28 @@
 				       const1_rtx, const0_rtx);
 }
 
+/* Expand a __builtin_allegrex_cache() function.  Make sure the passed
+   cache function code is less than 32.  */
+
+static rtx
+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
+{
+  rtx op0, op1;
+
+  op0 = mips_prepare_builtin_arg (icode, 0, exp, 0);
+  op1 = mips_prepare_builtin_arg (icode, 1, exp, 1);
+
+  if (GET_CODE (op0) == CONST_INT)
+    if (INTVAL (op0) < 0 || INTVAL (op0) > 0x1f)
+      {
+   error ("invalid function code '%d'", INTVAL (op0));
+   return const0_rtx;
+      }
+
+  emit_insn (GEN_FCN (icode) (op0, op1));
+  return target;
+}
+
 /* Implement TARGET_EXPAND_BUILTIN.  */
 
 static rtx
@@ -13484,6 +13583,9 @@
 
     case MIPS_BUILTIN_BPOSGE32:
       return mips_expand_builtin_bposge (d->builtin_type, target);
+
+    case MIPS_BUILTIN_CACHE:
+      return mips_expand_builtin_cache (d->icode, target, exp);
     }
   gcc_unreachable ();
 }
@@ -15918,6 +16020,22 @@
      Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
      MIPS16 mode afterwards if need be.  */
   mips_set_mips16_mode (false);
+
+  /* Validate -mpreferred-stack-boundary= value, or provide default.
+     The default of 128-bit is for newABI else 64-bit.  */
+  mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
+  mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
+  if (mips_preferred_stack_boundary_string)
+    {
+      i = atoi (mips_preferred_stack_boundary_string);
+      if (i < 2 || i > 12)
+       error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
+      else
+        {
+          mips_preferred_stack_align = (1 << i);
+          mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
+        }
+    }
 }
 
 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE.  */




--- ./gcc/config/mips/mips.h.orig	2011-03-08 20:51:11.000000000 +0000
+++ ./gcc/config/mips/mips.h	2012-01-21 14:11:18.000000000 +0000
@@ -231,6 +231,7 @@
 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1		\
 				     || mips_arch == PROCESSOR_SB1A)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
+#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)
 
 /* Scheduling target defines.  */
 #define TUNE_20KC		    (mips_tune == PROCESSOR_20KC)
@@ -258,6 +259,7 @@
 #define TUNE_OCTEON		    (mips_tune == PROCESSOR_OCTEON)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1		\
 				     || mips_tune == PROCESSOR_SB1A)
+#define TUNE_ALLEGREX               (mips_tune == PROCESSOR_ALLEGREX)
 
 /* Whether vector modes and intrinsics for ST Microelectronics
    Loongson-2E/2F processors should be enabled.  In o32 pairs of
@@ -852,6 +854,9 @@
 /* ISA has LDC1 and SDC1.  */
 #define ISA_HAS_LDC1_SDC1	(!ISA_MIPS1 && !TARGET_MIPS16)
 
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE   (TARGET_ALLEGREX)
+
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */
 #define ISA_HAS_8CC		(ISA_MIPS4				\
@@ -874,6 +879,7 @@
 
 /* ISA has conditional trap instructions.  */
 #define ISA_HAS_COND_TRAP	(!ISA_MIPS1				\
+				 && !TARGET_ALLEGREX				\
 				 && !TARGET_MIPS16)
 
 /* ISA has integer multiply-accumulate instructions, madd and msub.  */
@@ -910,6 +916,7 @@
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		((ISA_MIPS32				\
 				  || ISA_MIPS32R2			\
+				  || TARGET_ALLEGREX		\
 				  || ISA_MIPS64				\
 				  || ISA_MIPS64R2)			\
 				 && !TARGET_MIPS16)
@@ -955,6 +962,7 @@
 				  || TARGET_MIPS5400			\
 				  || TARGET_MIPS5500			\
 				  || TARGET_SR71K			\
+				  || TARGET_ALLEGREX			\
 				  || TARGET_SMARTMIPS)			\
 				 && !TARGET_MIPS16)
 
@@ -984,11 +992,13 @@
 
 /* ISA includes the MIPS32r2 seb and seh instructions.  */
 #define ISA_HAS_SEB_SEH		((ISA_MIPS32R2		\
+				  || TARGET_ALLEGREX	\
 				  || ISA_MIPS64R2)	\
 				 && !TARGET_MIPS16)
 
 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
 #define ISA_HAS_EXT_INS		((ISA_MIPS32R2		\
+				  || TARGET_ALLEGREX	\
 				  || ISA_MIPS64R2)	\
 				 && !TARGET_MIPS16)
 
@@ -1038,7 +1048,8 @@
 				 || ISA_MIPS64				\
 				 || ISA_MIPS64R2			\
 				 || TARGET_MIPS5500			\
-				 || TARGET_LOONGSON_2EF)
+				 || TARGET_LOONGSON_2EF		\
+				 || TARGET_ALLEGREX)
 
 /* ISA includes synci, jr.hb and jalr.hb.  */
 #define ISA_HAS_SYNCI ((ISA_MIPS32R2		\
@@ -2133,7 +2144,7 @@
    `crtl->outgoing_args_size'.  */
 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 
-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
 
 /* Symbolic macros for the registers used to return integer and floating
    point values.  */
@@ -2259,7 +2270,7 @@
 /* Treat LOC as a byte offset from the stack pointer and round it up
    to the next fully-aligned offset.  */
 #define MIPS_STACK_ALIGN(LOC) \
-  (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
+  (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
 
 
 /* Output assembler code to FILE to increment profiler label # LABELNO
@@ -2911,6 +2922,9 @@
 #endif
 #endif
 
+extern unsigned int mips_preferred_stack_boundary;
+extern unsigned int mips_preferred_stack_align;
+
 #ifndef HAVE_AS_TLS
 #define HAVE_AS_TLS 0
 #endif




--- ./gcc/config/mips/mips.md.orig	2011-03-03 21:56:58.000000000 +0000
+++ ./gcc/config/mips/mips.md	2012-01-21 14:11:19.000000000 +0000
@@ -37,6 +37,7 @@
   74kf2_1
   74kf1_1
   74kf3_2
+  allegrex
   loongson_2e
   loongson_2f
   loongson_3a
@@ -598,7 +599,7 @@
 ;; This mode iterator allows :MOVECC to be used anywhere that a
 ;; conditional-move-type condition is needed.
 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
-                              (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
+                              (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF && !TARGET_ALLEGREX")])
 
 ;; 32-bit integer moves for which we provide move patterns.
 (define_mode_iterator IMOVE32
@@ -1885,11 +1886,11 @@
 	   (mult:DI
 	      (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	      (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
-  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
+  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
 {
   if (ISA_HAS_DSP_MULT)
     return "msub<u>\t%q0,%1,%2";
-  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
+  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
     return "msub<u>\t%1,%2";
   else
     return "msac<u>\t$0,%1,%2";
@@ -2066,14 +2067,14 @@
 	 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 		  (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
 	 (match_operand:DI 3 "register_operand" "0")))]
-  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
+  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
    && !TARGET_64BIT"
 {
   if (TARGET_MAD)
     return "mad<u>\t%1,%2";
   else if (ISA_HAS_DSP_MULT)
     return "madd<u>\t%q0,%1,%2";
-  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
+  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
     return "madd<u>\t%1,%2";
   else
     /* See comment in *macc.  */
@@ -2500,6 +2501,33 @@
 ;;
 ;;  ....................
 ;;
+;; FIND FIRST BIT INSTRUCTION
+;;
+;;  ....................
+;;
+
+(define_expand "ffs<mode>2"
+  [(set (match_operand:GPR 0 "register_operand" "")
+   (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+  "ISA_HAS_CLZ_CLO"
+{
+  rtx r1, r2, r3, r4;
+  
+  r1 = gen_reg_rtx (<MODE>mode);
+  r2 = gen_reg_rtx (<MODE>mode);
+  r3 = gen_reg_rtx (<MODE>mode);
+  r4 = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_neg<mode>2 (r1, operands[1]));
+  emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+  emit_insn (gen_clz<mode>2 (r3, r2));
+  emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+  emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+  DONE;
+})
+
+;;
+;;  ....................
+;;
 ;;	NEGATION and ONE'S COMPLEMENT
 ;;
 ;;  ....................
@@ -2550,6 +2578,25 @@
   [(set_attr "alu_type" "not")
    (set_attr "mode" "<MODE>")])
 
+(define_expand "rotl<mode>3"
+  [(set (match_operand:GPR 0 "register_operand")
+       (rotate:GPR (match_operand:GPR 1 "register_operand")
+           (match_operand:SI 2 "arith_operand")))]
+  "ISA_HAS_ROR"
+{
+  rtx temp;
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
+  else
+    {
+      temp = gen_reg_rtx (<MODE>mode);
+      emit_insn (gen_neg<mode>2 (temp, operands[2]));
+    }
+  emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
+  DONE;
+})
+
 ;;
 ;;  ....................
 ;;
@@ -6301,7 +6348,7 @@
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
 	 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%T4\t%0,%z2,%1
     mov%t4\t%0,%z3,%1"
@@ -6331,8 +6378,12 @@
 	(if_then_else:GPR (match_dup 5)
 			  (match_operand:GPR 2 "reg_or_0_operand")
 			  (match_operand:GPR 3 "reg_or_0_operand")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
 {
+  if (ISA_HAS_INT_CONDMOVE
+      && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
+    FAIL;
+
   mips_expand_conditional_move (operands);
   DONE;
 })
@@ -6481,6 +6532,9 @@
 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
 (include "loongson.md")
 
+; Sony ALLEGREX instructions.
+(include "allegrex.md")
+
 (define_c_enum "unspec" [
   UNSPEC_ADDRESS_FIRST
 ])




--- ./gcc/config/mips/mips.opt.orig	2011-02-17 01:59:04.000000000 +0000
+++ ./gcc/config/mips/mips.opt	2012-01-21 14:11:19.000000000 +0000
@@ -306,5 +306,9 @@
 Target Report Var(TARGET_XGOT)
 Lift restrictions on GOT size
 
+mpreferred-stack-boundary=
+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
+Attempt to keep stack aligned to this power of 2
+
 noasmopt
 Driver




--- ./gcc/config/mips/psp.h.orig	2012-01-21 14:11:19.000000000 +0000
+++ ./gcc/config/mips/psp.h	2012-01-21 14:11:19.000000000 +0000
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+   Copyright (C) 2005 Free Software Foundation, Inc.
+   Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"




--- ./gcc/config/mips/t-allegrex.orig	2012-01-21 14:11:19.000000000 +0000
+++ ./gcc/config/mips/t-allegrex	2012-01-21 14:11:19.000000000 +0000
@@ -0,0 +1,29 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = 
+MULTILIB_DIRNAMES = 
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib




--- ./gcc/config.gcc.orig	2011-07-22 16:44:50.000000000 +0000
+++ ./gcc/config.gcc	2012-01-21 14:11:19.000000000 +0000
@@ -2033,6 +2033,18 @@
 	tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
 	tmake_file="mips/t-r3900 mips/t-libgcc-mips16"
 	;;
+mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
+   tm_file="elfos.h ${tm_file} mips/elf.h"
+   tmake_file=mips/t-allegrex
+   target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+   tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
+   case ${target} in
+   mipsallegrex*-psp-elf*) 
+       tm_file="${tm_file} mips/psp.h"
+       ;;
+   esac
+   use_fixproto=yes
+   ;;
 mmix-knuth-mmixware)
 	tm_file="${tm_file} newlib-stdint.h"
 	need_64bit_hwint=yes




--- gcc/config.gcc.orig	2015-05-21 20:50:59 UTC
+++ gcc/config.gcc
@@ -2118,6 +2118,18 @@ mipstx39-*-elf* | mipstx39el-*-elf*)
 	tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
 	tmake_file="mips/t-r3900"
 	;;
+mipsallegrex-*-elf* | mipsallegrexel-*-elf*)
+   tm_file="elfos.h ${tm_file} mips/elf.h"
+   tmake_file=mips/t-allegrex
+   target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+   tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
+   case ${target} in
+   mipsallegrex*-psp-elf*) 
+       tm_file="${tm_file} mips/psp.h"
+       ;;
+   esac
+   use_fixproto=yes
+   ;;
 mmix-knuth-mmixware)
 	tm_file="${tm_file} newlib-stdint.h"
 	need_64bit_hwint=yes




--- gcc/config/mips/allegrex.md.orig	2019-06-06 21:32:32 UTC
+++ gcc/config/mips/allegrex.md
@@ -0,0 +1,172 @@
+;; Sony ALLEGREX instructions.
+;; Copyright (C) 2005 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
+
+(define_c_enum "unspec" [
+  UNSPEC_CLO
+  UNSPEC_CTO
+  UNSPEC_CACHE
+  UNSPEC_CEIL_W_S
+  UNSPEC_FLOOR_W_S
+  UNSPEC_ROUND_W_S
+])
+
+;; Multiply Add and Subtract.
+;; Note: removed clobbering for madd and msub (testing needed)
+
+(define_insn "allegrex_madd"
+  [(set (match_operand:SI 0 "register_operand" "+l")
+       (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
+             (match_operand:SI 2 "register_operand" "d"))
+        (match_dup 0)))]
+  "TARGET_ALLEGREX"
+  "madd\t%1,%2"
+  [(set_attr "type"    "imadd")
+   (set_attr "mode"    "SI")])
+
+(define_insn "allegrex_msub"
+  [(set (match_operand:SI 0 "register_operand" "+l")
+       (minus:SI (match_dup 0)
+         (mult:SI (match_operand:SI 1 "register_operand" "d")
+              (match_operand:SI 2 "register_operand" "d"))))]
+  "TARGET_ALLEGREX"
+  "msub\t%1,%2"
+  [(set_attr "type"    "imadd")
+   (set_attr "mode"    "SI")])
+
+
+;; Min and max.
+
+(define_insn "sminsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (smin:SI (match_operand:SI 1 "register_operand" "d")
+                 (match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_ALLEGREX"
+  "min\t%0,%1,%2"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+(define_insn "smaxsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (smax:SI (match_operand:SI 1 "register_operand" "d")
+                 (match_operand:SI 2 "register_operand" "d")))]
+  "TARGET_ALLEGREX"
+  "max\t%0,%1,%2"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+
+;; Extended shift instructions.
+
+(define_insn "allegrex_bitrev"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+   (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+          UNSPEC_BITREV))]
+  "TARGET_ALLEGREX"
+  "bitrev\t%0,%1"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+;; Count leading ones, count trailing zeros, and count trailing ones (clz is
+;; already defined).
+
+(define_insn "allegrex_clo"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+       (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
+          UNSPEC_CLO))]
+  "TARGET_ALLEGREX"
+  "clo\t%0,%1"
+  [(set_attr "type"    "clz")
+   (set_attr "mode"    "SI")])
+
+(define_expand "ctzsi2"
+  [(set (match_operand:SI 0 "register_operand")
+       (ctz:SI (match_operand:SI 1 "register_operand")))]
+  "TARGET_ALLEGREX"
+{
+  rtx r1;
+
+  r1 = gen_reg_rtx (SImode);
+  emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+  emit_insn (gen_clzsi2 (operands[0], r1));
+  DONE;
+})
+
+(define_expand "allegrex_cto"
+  [(set (match_operand:SI 0 "register_operand")
+       (unspec:SI [(match_operand:SI 1 "register_operand")]
+          UNSPEC_CTO))]
+  "TARGET_ALLEGREX"
+{
+  rtx r1;
+
+  r1 = gen_reg_rtx (SImode);
+  emit_insn (gen_allegrex_bitrev (r1, operands[1]));
+  emit_insn (gen_allegrex_clo (operands[0], r1));
+  DONE;
+})
+
+
+;; Misc.
+
+(define_insn "allegrex_sync"
+  [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
+  "TARGET_ALLEGREX"
+  "sync"
+  [(set_attr "type"    "unknown")
+   (set_attr "mode"    "none")])
+
+(define_insn "allegrex_cache"
+  [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
+            (match_operand:SI 1 "register_operand" "d")]
+           UNSPEC_CACHE)]
+  "TARGET_ALLEGREX"
+  "cache\t%0,0(%1)"
+  [(set_attr "type"    "unknown")
+   (set_attr "mode"    "none")])
+
+
+;; Floating-point builtins.
+
+(define_insn "allegrex_ceil_w_s"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+          UNSPEC_CEIL_W_S))]
+  "TARGET_ALLEGREX"
+  "ceil.w.s\t%0,%1"
+  [(set_attr "type"    "fcvt")
+   (set_attr "mode"    "SF")])
+
+(define_insn "allegrex_floor_w_s"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+          UNSPEC_FLOOR_W_S))]
+  "TARGET_ALLEGREX"
+  "floor.w.s\t%0,%1"
+  [(set_attr "type"    "fcvt")
+   (set_attr "mode"    "SF")])
+
+(define_insn "allegrex_round_w_s"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+       (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
+          UNSPEC_ROUND_W_S))]
+  "TARGET_ALLEGREX"
+  "round.w.s\t%0,%1"
+  [(set_attr "type"    "fcvt")
+   (set_attr "mode"    "SF")])

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_mips-cpus.def (+10 lines)
	1	--- gcc/config/mips/mips-cpus.def.orig 2014-03-04 21:39:50 UTC
	2	+++ gcc/config/mips/mips-cpus.def
	3	@@ -55,6 +55,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
	4
	5	/* MIPS II processors. */
	6	MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
	7	+MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, 2, 0)
	8
	9	/* MIPS III processors. */
	10	MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)




--- gcc/config/mips/mips-ftypes.def.orig	2014-02-02 16:05:09 UTC
+++ gcc/config/mips/mips-ftypes.def
@@ -53,9 +53,12 @@ DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF))
 DEF_MIPS_FTYPE (2, (SI, DI, SI))
 DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
 DEF_MIPS_FTYPE (2, (DI, POINTER, SI))
+DEF_MIPS_FTYPE (1, (SI, HI))
+DEF_MIPS_FTYPE (1, (SI, SF))
 DEF_MIPS_FTYPE (1, (SI, SI))
 DEF_MIPS_FTYPE (2, (SI, SI, SI))
 DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
+DEF_MIPS_FTYPE (1, (SI, QI))
 DEF_MIPS_FTYPE (1, (SI, V2HI))
 DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
 DEF_MIPS_FTYPE (1, (SI, V4QI))
@@ -127,3 +130,4 @@ DEF_MIPS_FTYPE (2, (VOID, SI, SI))
 DEF_MIPS_FTYPE (1, (VOID, USI))
 DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
 DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
+DEF_MIPS_FTYPE (1, (VOID, VOID))




--- gcc/config/mips/mips.c.orig	2014-03-08 09:27:23 UTC
+++ gcc/config/mips/mips.c
@@ -248,7 +248,12 @@ enum mips_builtin_type {
   MIPS_BUILTIN_CMP_SINGLE,
 
   /* For generating bposge32 branch instructions in MIPS32 DSP ASE.  */
-  MIPS_BUILTIN_BPOSGE32
+  MIPS_BUILTIN_BPOSGE32,
+
+  /* The builtin corresponds to the ALLEGREX cache instruction.  Operand 0
+     is the function code (must be less than 32) and operand 1 is the base
+     address.  */
+  MIPS_BUILTIN_CACHE
 };
 
 /* Invoke MACRO (COND) for each C.cond.fmt condition.  */
@@ -574,6 +579,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
    normal branch.  */
 static bool mips_branch_likely;
 
+/* Preferred stack boundary for proper stack vars alignment */
+unsigned int mips_preferred_stack_boundary;
+unsigned int mips_preferred_stack_align;
+
 /* The current instruction-set architecture.  */
 enum processor mips_arch;
 const struct mips_cpu_info *mips_arch_info;
@@ -919,6 +928,9 @@ static const struct mips_rtx_cost_data
 		     1,           /* branch_cost */
 		     4            /* memory_latency */
   },
+  { /* Allegrex */
+    DEFAULT_COSTS
+  },
   { /* Loongson-2E */
     DEFAULT_COSTS
   },
@@ -13780,6 +13792,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
 AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
 AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
 AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
+AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
 
 /* Construct a mips_builtin_description from the given arguments.
 
@@ -13876,6 +13889,30 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
   MIPS_BUILTIN (bposge, f, "bposge" #VALUE,				\
 		MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
 
+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
+   FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields.  */
+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,        \
+    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
+/* Same as the above, but mapped to an instruction that doesn't share the
+   NAME.  NAME is the name of the builtin without the builtin prefix.  */
+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
+  { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME,             \
+    MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
+   CODE_FOR_allegrex_<INSN>.  FUNCTION_TYPE and TARGET_FLAGS are
+   builtin_description fields.  */
+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS)   \
+  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
+    MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
+/* Define a builtin with a specific function TYPE.  */
+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS)  \
+  { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN,            \
+    MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
+
 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
    for instruction CODE_FOR_loongson_<INSN>.  FUNCTION_TYPE is a
    builtin_description field.  */
@@ -14122,6 +14159,38 @@ static const struct mips_builtin_description mips_buil
   DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
   DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
 
+/* Builtin functions for the Sony ALLEGREX processor.
+
+   These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
+   to maintain compatibility with Sony's ALLEGREX GCC port.
+
+   Some of the builtins may seem redundant, but they are the same as the
+   builtins defined in the Sony compiler.  I chose to map redundant and
+   trivial builtins to the original instruction instead of creating
+   duplicate patterns specifically for the ALLEGREX (as Sony does).  */
+
+  DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+  DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
+
+  DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
+  SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
+
+  DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
+  DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
+
   /* Builtin functions for ST Microelectronics Loongson-2E/2F cores.  */
   LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
   LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
@@ -14273,6 +14342,8 @@ mips_build_cvpointer_type (void)
 /* Standard mode-based argument types.  */
 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
 #define MIPS_ATYPE_SI intSI_type_node
+#define MIPS_ATYPE_HI intHI_type_node
+#define MIPS_ATYPE_QI intQI_type_node
 #define MIPS_ATYPE_USI unsigned_intSI_type_node
 #define MIPS_ATYPE_DI intDI_type_node
 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
@@ -14575,6 +14646,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type bui
 				       const1_rtx, const0_rtx);
 }
 
+/* Expand a __builtin_allegrex_cache() function.  Make sure the passed
+   cache function code is less than 32.  */
+
+static rtx
+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
+{
+  int argno;
+  struct expand_operand ops[2];
+
+  for (argno = 0; argno < 2; argno++)
+    mips_prepare_builtin_arg (&ops[argno], exp, argno);
+
+  if (GET_CODE(ops[0].value) != CONST_INT ||
+      INTVAL(ops[0].value) < 0 || INTVAL(ops[0].value) > 0x1f)
+    error("Invalid first argument for cache builtin (0 <= arg <= 31)");
+
+  emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
+  return target;
+}
+
 /* Implement TARGET_EXPAND_BUILTIN.  */
 
 static rtx
@@ -14620,6 +14711,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarg
 
     case MIPS_BUILTIN_BPOSGE32:
       return mips_expand_builtin_bposge (d->builtin_type, target);
+
+    case MIPS_BUILTIN_CACHE:
+      return mips_expand_builtin_cache (d->icode, target, exp);
     }
   gcc_unreachable ();
 }
@@ -17376,6 +17470,22 @@ mips_option_override (void)
 
   if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
     REAL_MODE_FORMAT (SFmode) = &spu_single_format;
+
+  /* Validate -mpreferred-stack-boundary= value, or provide default.
+     The default of 128-bit is for newABI else 64-bit.  */
+  mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
+  mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
+  if (mips_preferred_stack_boundary_string)
+    {
+      i = atoi (mips_preferred_stack_boundary_string);
+      if (i < 2 || i > 12)
+       error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
+      else
+        {
+          mips_preferred_stack_align = (1 << i);
+          mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
+        }
+    }
 }
 
 /* Swap the register information for registers I and I + 1, which




--- gcc/config/mips/mips.h.orig	2015-02-26 10:40:06 UTC
+++ gcc/config/mips/mips.h
@@ -231,6 +231,7 @@ struct mips_cpu_info {
 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1		\
 				     || mips_arch == PROCESSOR_SB1A)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
+#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)
 #define TARGET_XLP                  (mips_arch == PROCESSOR_XLP)
 
 /* Scheduling target defines.  */
@@ -260,6 +261,7 @@ struct mips_cpu_info {
 				     || mips_tune == PROCESSOR_OCTEON2)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1		\
 				     || mips_tune == PROCESSOR_SB1A)
+#define TUNE_ALLEGREX               (mips_tune == PROCESSOR_ALLEGREX)
 
 /* Whether vector modes and intrinsics for ST Microelectronics
    Loongson-2E/2F processors should be enabled.  In o32 pairs of
@@ -868,6 +870,9 @@ struct mips_cpu_info {
 				 && !TARGET_MIPS5900			\
 				 && !TARGET_MIPS16)
 
+/* ISA has just the integer condition move instructions (movn,movz) */
+#define ISA_HAS_INT_CONDMOVE   (TARGET_ALLEGREX)
+
 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
    branch on CC, and move (both FP and non-FP) on CC.  */
 #define ISA_HAS_8CC		(ISA_MIPS4				\
@@ -895,6 +900,7 @@ struct mips_cpu_info {
 
 /* ISA has conditional trap instructions.  */
 #define ISA_HAS_COND_TRAP	(!ISA_MIPS1				\
+				 && !TARGET_ALLEGREX				\
 				 && !TARGET_MIPS16)
 
 /* ISA has integer multiply-accumulate instructions, madd and msub.  */
@@ -938,6 +944,7 @@ struct mips_cpu_info {
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
 #define ISA_HAS_CLZ_CLO		((ISA_MIPS32				\
 				  || ISA_MIPS32R2			\
+				  || TARGET_ALLEGREX		\
 				  || ISA_MIPS64				\
 				  || ISA_MIPS64R2)			\
 				 && !TARGET_MIPS16)
@@ -983,6 +990,7 @@ struct mips_cpu_info {
 				  || TARGET_MIPS5400			\
 				  || TARGET_MIPS5500			\
 				  || TARGET_SR71K			\
+				  || TARGET_ALLEGREX			\
 				  || TARGET_SMARTMIPS)			\
 				 && !TARGET_MIPS16)
 
@@ -1014,11 +1022,13 @@ struct mips_cpu_info {
 
 /* ISA includes the MIPS32r2 seb and seh instructions.  */
 #define ISA_HAS_SEB_SEH		((ISA_MIPS32R2		\
+				  || TARGET_ALLEGREX	\
 				  || ISA_MIPS64R2)	\
 				 && !TARGET_MIPS16)
 
 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
 #define ISA_HAS_EXT_INS		((ISA_MIPS32R2		\
+				  || TARGET_ALLEGREX	\
 				  || ISA_MIPS64R2)	\
 				 && !TARGET_MIPS16)
 
@@ -1084,7 +1094,8 @@ struct mips_cpu_info {
 				 || ISA_MIPS64R2			\
 				 || TARGET_MIPS5500			\
 				 || TARGET_MIPS5900			\
-				 || TARGET_LOONGSON_2EF)
+				 || TARGET_LOONGSON_2EF		\
+				 || TARGET_ALLEGREX)
 
 /* ISA includes synci, jr.hb and jalr.hb.  */
 #define ISA_HAS_SYNCI ((ISA_MIPS32R2		\
@@ -2209,7 +2220,7 @@ enum reg_class
    `crtl->outgoing_args_size'.  */
 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 
-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
 
 /* Symbolic macros for the registers used to return integer and floating
    point values.  */
@@ -2321,7 +2332,7 @@ typedef struct mips_args {
 /* Treat LOC as a byte offset from the stack pointer and round it up
    to the next fully-aligned offset.  */
 #define MIPS_STACK_ALIGN(LOC) \
-  (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
+  (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
 
 
 /* Output assembler code to FILE to increment profiler label # LABELNO
@@ -2936,6 +2947,9 @@ while (0)
 	.set pop\n\
 	" TEXT_SECTION_ASM_OP);
 #endif
+
+extern unsigned int mips_preferred_stack_boundary;
+extern unsigned int mips_preferred_stack_align;
 
 #ifndef HAVE_AS_TLS
 #define HAVE_AS_TLS 0




--- gcc/config/mips/mips.md.orig	2014-02-02 16:05:09 UTC
+++ gcc/config/mips/mips.md
@@ -35,6 +35,7 @@
   74kf2_1
   74kf1_1
   74kf3_2
+  allegrex
   loongson_2e
   loongson_2f
   loongson_3a
@@ -756,6 +757,7 @@
 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
                               (CC "TARGET_HARD_FLOAT
 				   && !TARGET_LOONGSON_2EF
+				   && !TARGET_ALLEGREX
 				   && !TARGET_MIPS5900")])
 
 ;; 32-bit integer moves for which we provide move patterns.
@@ -2070,11 +2072,11 @@
 	   (mult:DI
 	      (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	      (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
-  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP)"
+  "!TARGET_64BIT && (ISA_HAS_MSAC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)"
 {
   if (ISA_HAS_DSP_MULT)
     return "msub<u>\t%q0,%1,%2";
-  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB)
+  else if (TARGET_MIPS5500 || GENERATE_MADD_MSUB || TARGET_ALLEGREX)
     return "msub<u>\t%1,%2";
   else
     return "msac<u>\t$0,%1,%2";
@@ -2312,14 +2314,14 @@
 	 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
 		  (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
 	 (match_operand:DI 3 "muldiv_target_operand" "0")))]
-  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP)
+  "(TARGET_MAD || ISA_HAS_MACC || GENERATE_MADD_MSUB || ISA_HAS_DSP || TARGET_ALLEGREX)
    && !TARGET_64BIT"
 {
   if (TARGET_MAD)
     return "mad<u>\t%1,%2";
   else if (ISA_HAS_DSP_MULT)
     return "madd<u>\t%q0,%1,%2";
-  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500)
+  else if (GENERATE_MADD_MSUB || TARGET_MIPS5500 || TARGET_ALLEGREX)
     return "madd<u>\t%1,%2";
   else
     /* See comment in *macc.  */
@@ -2857,6 +2859,33 @@
 ;;
 ;;  ....................
 ;;
+;; FIND FIRST BIT INSTRUCTION
+;;
+;;  ....................
+;;
+
+(define_expand "ffs<mode>2"
+  [(set (match_operand:GPR 0 "register_operand" "")
+   (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
+  "ISA_HAS_CLZ_CLO"
+{
+  rtx r1, r2, r3, r4;
+  
+  r1 = gen_reg_rtx (<MODE>mode);
+  r2 = gen_reg_rtx (<MODE>mode);
+  r3 = gen_reg_rtx (<MODE>mode);
+  r4 = gen_reg_rtx (<MODE>mode);
+  emit_insn (gen_neg<mode>2 (r1, operands[1]));
+  emit_insn (gen_and<mode>3 (r2, operands[1], r1));
+  emit_insn (gen_clz<mode>2 (r3, r2));
+  emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
+  emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
+  DONE;
+})
+
+;;
+;;  ....................
+;;
 ;;	NEGATION and ONE'S COMPLEMENT
 ;;
 ;;  ....................
@@ -2909,6 +2938,25 @@
    (set_attr "compression" "micromips,*")
    (set_attr "mode" "<MODE>")])
 
+(define_expand "rotl<mode>3"
+  [(set (match_operand:GPR 0 "register_operand")
+       (rotate:GPR (match_operand:GPR 1 "register_operand")
+           (match_operand:SI 2 "arith_operand")))]
+  "ISA_HAS_ROR"
+{
+  rtx temp;
+
+  if (GET_CODE (operands[2]) == CONST_INT)
+    temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
+  else
+    {
+      temp = gen_reg_rtx (<MODE>mode);
+      emit_insn (gen_neg<mode>2 (temp, operands[2]));
+    }
+  emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
+  DONE;
+})
+
 ;;
 ;;  ....................
 ;;
@@ -6869,7 +6917,7 @@
 		 (const_int 0)])
 	 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
 	 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
     mov%T4\t%0,%z2,%1
     mov%t4\t%0,%z3,%1"
@@ -6912,8 +6960,12 @@
 	(if_then_else:GPR (match_dup 5)
 			  (match_operand:GPR 2 "reg_or_0_operand")
 			  (match_operand:GPR 3 "reg_or_0_operand")))]
-  "ISA_HAS_CONDMOVE"
+  "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
 {
+  if (ISA_HAS_INT_CONDMOVE
+      && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
+    FAIL;
+
   mips_expand_conditional_move (operands);
   DONE;
 })
@@ -7184,6 +7236,9 @@
 
 ; ST-Microelectronics Loongson-2E/2F-specific patterns.
 (include "loongson.md")
+
+; Sony ALLEGREX instructions.
+(include "allegrex.md")
 
 (define_c_enum "unspec" [
   UNSPEC_ADDRESS_FIRST




--- gcc/config/mips/mips.opt.orig	2014-02-21 13:30:47 UTC
+++ gcc/config/mips/mips.opt
@@ -400,5 +400,9 @@ mxgot
 Target Report Var(TARGET_XGOT)
 Lift restrictions on GOT size
 
+mpreferred-stack-boundary=
+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
+Attempt to keep stack aligned to this power of 2
+
 noasmopt
 Driver




--- gcc/config/mips/psp.h.orig	2019-06-06 21:32:32 UTC
+++ gcc/config/mips/psp.h
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+   Copyright (C) 2005 Free Software Foundation, Inc.
+   Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"




--- gcc/config/mips/t-allegrex.orig	2019-06-06 21:32:32 UTC
+++ gcc/config/mips/t-allegrex
@@ -0,0 +1,29 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# Assemble startup files.
+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
+
+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = 
+MULTILIB_DIRNAMES = 
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib




--- gcc/gengtype.c.orig	2010-11-25 19:03:27.000000000 +0000
+++ gcc/gengtype.c
@@ -3594,14 +3594,13 @@ write_field_root (outf_p f, pair_p v, ty
 		  int has_length, struct fileloc *line, const char *if_marked,
 		  bool emit_pch, type_p field_type, const char *field_name)
 {
+  struct pair newv;
   /* If the field reference is relative to V, rather than to some
      subcomponent of V, we can mark any subarrays with a single stride.
      We're effectively treating the field as a global variable in its
      own right.  */
   if (v && type == v->type)
     {
-      struct pair newv;
-
       newv = *v;
       newv.type = field_type;
       newv.name = ACONCAT ((v->name, ".", field_name, NULL));

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_system.h (+10 lines)
	1	--- gcc/system.h.orig 2014-01-02 22:23:26 UTC
	2	+++ gcc/system.h
	3	@@ -203,6 +203,7 @@ extern int errno;
	4
	5	#ifdef __cplusplus
	6	# include <cstring>
	7	+# include <new>
	8	#endif
	9
	10	/* Some of glibc's string inlines cause warnings. Plus we'd rather




--- libcpp/Makefile.in.orig	2015-06-26 17:59:14 UTC
+++ libcpp/Makefile.in
@@ -208,8 +208,8 @@ ifeq ($(DEPMODE),depmode=gcc3)
 # Note that we put the dependencies into a .Tpo file, then move them
 # into place if the compile succeeds.  We need this because gcc does
 # not atomically write the dependency output file.
-COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
-POSTCOMPILE = @mv $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po
+COMPILE = $(COMPILE.base) -o $@
+POSTCOMPILE =
 else
 COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
 	  $(depcomp) $(COMPILE.base)

Lines 1-11 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc-config.host (-11 lines)
1	--- ./libgcc/config.host.orig 2011-03-14 06:06:23.000000000 +0000
2	+++ ./libgcc/config.host 2012-01-21 14:11:19.000000000 +0000
3	@@ -445,6 +445,8 @@
4	;;
5	mipstx39--elf \| mipstx39el--elf)
6	;;
7	+mips*-psp-elf)
8	+ ;;
9	mmix-knuth-mmixware)
10	extra_parts="crti.o crtn.o crtbegin.o crtend.o"
11	tmake_file="${tmake_file} ${cpu_type}/t-${cpu_type}"




--- libgcc/config.host.orig	2014-03-27 15:40:31 UTC
+++ libgcc/config.host
@@ -140,11 +140,15 @@ microblaze*-*-*)
 	cpu_type=microblaze
 	;;
 mips*-*-*)
-	# All MIPS targets provide a full set of FP routines.
 	cpu_type=mips
 	tmake_file="mips/t-mips"
 	if test "${libgcc_cv_mips_hard_float}" = yes; then
-		tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
+		if test "${libgcc_cv_mips_single_float}" = yes; then
+			tmake_file="${tmake_file} t-hardfp-sf"
+		else
+			tmake_file="${tmake_file} t-hardfp-sfdf"
+		fi
+		tmake_file="${tmake_file} t-hardfp"
 	else
 		tmake_file="${tmake_file} t-softfp-sfdf"
 	fi
@@ -859,6 +863,14 @@ mips-wrs-vxworks)
 	;;
 mipstx39-*-elf* | mipstx39el-*-elf*)
 	tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
+	;;
+mips*-psp*)
+    tmake_file="${tmake_file} mips/t-allegrex"
+    target_cpu_default="MASK_SINGLE_FLOAT|MASK_DIVIDE_BREAKS"
+    tm_file="${tm_file} mips/psp.h"
+	 extra_parts="$extra_parts crti.o crtn.o"
+    use_fixproto=yes
+    tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
 	;;
 mmix-knuth-mmixware)
 	extra_parts="crti.o crtn.o crtbegin.o crtend.o"




--- libgcc/config/mips/psp.h.orig	2019-06-06 21:32:32 UTC
+++ libgcc/config/mips/psp.h
@@ -0,0 +1,31 @@
+/* Support for Sony's Playstation Portable (PSP).
+   Copyright (C) 2005 Free Software Foundation, Inc.
+   Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Override the startfile spec to include crt0.o. */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
+
+#undef SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
+
+/* Get rid of the .pdr section. */
+#undef SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC "-mno-pdr"




--- libgcc/config/mips/t-allegrex.orig	2019-06-06 21:32:32 UTC
+++ libgcc/config/mips/t-allegrex
@@ -0,0 +1,20 @@
+# Suppress building libgcc1.a, since the MIPS compiler port is complete
+# and does not need anything from libgcc1.a.
+LIBGCC1 =
+CROSS_LIBGCC1 =
+
+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
+# Don't let CTOR_LIST end up in sdata section.
+CRTSTUFF_T_CFLAGS = -G 0
+
+# We must build libgcc2.a with -G 0, in case the user wants to link
+# without the $gp register.
+TARGET_LIBGCC2_CFLAGS = -G 0
+
+# Build the libraries for both hard and soft floating point
+
+MULTILIB_OPTIONS = 
+MULTILIB_DIRNAMES = 
+
+LIBGCC = stmp-multilib
+INSTALL_LIBGCC = install-multilib




--- libgcc/config/t-hardfp.orig	2014-02-07 07:46:34 UTC
+++ libgcc/config/t-hardfp
@@ -50,12 +50,16 @@ hardfp_func_list += $(foreach pair, $(hardfp_extension
 hardfp_func_list += $(foreach pair, $(hardfp_truncations), \
 		    	      $(subst M,$(pair),truncM2))
 
+hardfp_suffixes := $(hardfp_int_modes) 2 3
+
 # Regexp for matching a floating-point mode.
 hardfp_mode_regexp := $(shell echo $(hardfp_float_modes) | sed 's/ /\\|/g')
+hardfp_mode_regexp_awk := $(shell echo $(hardfp_float_modes) | sed 's/ /|/g')
 
 # Regexp for matching the end of a function name, after the last
 # floating-point mode.
-hardfp_suffix_regexp := $(shell echo $(hardfp_int_modes) 2 3 | sed 's/ /\\|/g')
+hardfp_suffix_regexp := $(shell echo $(hardfp_suffixes) | sed 's/ /\\|/g')
+hardfp_suffix_regexp_awk := $(shell echo $(hardfp_suffixes) | sed 's/ /|/g')
 
 # Add -D options to define:
 #   FUNC: the function name (e.g. __addsf3)
@@ -64,12 +68,20 @@ hardfp_suffix_regexp := $(shell echo $(hardfp_int_mode
 #   TYPE: the last floating-point mode (e.g. sf)
 hardfp_defines_for = \
   $(shell echo $1 | \
-    sed 's/\(.*\)\($(hardfp_mode_regexp)\)\($(hardfp_suffix_regexp)\|\)$$/-DFUNC=__& -DOP_\1\3 -DTYPE=\2/')
+    $(AWK) 'BEGIN{split("$(hardfp_mode_regexp_awk)",mode,"|"); \
+                  split("$(hardfp_suffix_regexp_awk)",suffix,"|")} \
+            { sfx=""; for (s in suffix) if (match($$0, suffix[s]"$$")) { sfx=suffix[s]; break; } \
+              o=substr($$0,0,length($$0)-length(sfx)); \
+              for (m in mode) { if (match(o, mode[m]"$$")) { \
+                op=substr(o,0,length(o)-length(mode[m])); \
+                print"-DFUNC=__"$$0" -DOP_" op sfx" -DTYPE="mode[m];exit; }}}')
 
 hardfp-o = $(patsubst %,%$(objext),$(hardfp_func_list))
 $(hardfp-o): %$(objext): $(srcdir)/config/hardfp.c
 	@echo "Mode = $(hardfp_mode_regexp)"
 	@echo "Suffix = $(hardfp_suffix_regexp)"
+	$(info $(call hardfp_defines_for, $*))
+	$(info $$*=$*)
 	$(gcc_compile) $(call hardfp_defines_for, $*) -c $< $(vis_hide) -Wno-missing-prototypes
 libgcc-objects += $(hardfp-o)
 




--- libgcc/config/t-hardfp-sf.orig	2019-06-06 21:40:23 UTC
+++ libgcc/config/t-hardfp-sf
@@ -0,0 +1,32 @@
+# Copyright (C) 2014 Free Software Foundation, Inc.
+
+# This file is part of GCC.
+
+# GCC is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+
+# GCC is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3.  If not see
+# <http://www.gnu.org/licenses/>.
+
+hardfp_float_modes := sf
+# di and ti are provided by libgcc2.c where needed.
+hardfp_int_modes := si
+hardfp_extensions := 
+hardfp_truncations := 
+
+# Emulate 64 bit float:
+FPBIT = true
+DPBIT = true
+# Don't build functions handled by 32 bit hardware:
+LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
+    _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
+    _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
+    _thenan_sf _sf_to_usi _usi_to_sf




--- libgcc/configure.orig	2014-02-07 07:46:34 UTC
+++ libgcc/configure
@@ -4352,6 +4352,26 @@ rm -f core conftest.err conftest.$ac_objext conftest.$
 fi
 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
 $as_echo "$libgcc_cv_mips_hard_float" >&6; }
+  { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
+$as_echo_n "checking whether the target is single-float... " >&6; }
+if test "${libgcc_cv_mips_single_float+set}" = set; then :
+  $as_echo_n "(cached) " >&6
+else
+  cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#ifndef __mips_single_float
+     #error FOO
+     #endif
+_ACEOF
+if ac_fn_c_try_compile "$LINENO"; then :
+  libgcc_cv_mips_single_float=yes
+else
+  libgcc_cv_mips_single_float=no
+fi
+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
+$as_echo "$libgcc_cv_mips_single_float" >&6; }
 esac
 
 # Collect host-machine-specific information.




--- libgcc/configure.ac.orig	2014-02-07 07:46:34 UTC
+++ libgcc/configure.ac
@@ -302,6 +302,14 @@ mips*-*-*)
      #endif],
     [libgcc_cv_mips_hard_float=yes],
     [libgcc_cv_mips_hard_float=no])])
+  AC_CACHE_CHECK([whether the target is single-float],
+		 [libgcc_cv_mips_single_float],
+		 [AC_COMPILE_IFELSE(
+    [#ifndef __mips_single_float
+     #error FOO
+     #endif],
+    [libgcc_cv_mips_single_float=yes],
+    [libgcc_cv_mips_single_float=no])])
 esac
 
 # Collect host-machine-specific information.

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_crtstuff.c (+11 lines)
	1	--- libgcc/crtstuff.c.orig 2014-03-10 18:31:20 UTC
	2	+++ libgcc/crtstuff.c
	3	@@ -47,7 +47,7 @@ see the files COPYING3 and COPYING.RUNTIME respectivel
	4
	5	/* Target machine header files require this define. */
	6	#define IN_LIBGCC2
	7	-
	8	+#define USED_FOR_TARGET
	9	/* FIXME: Including auto-host is incorrect, but until we have
	10	identified the set of defines that need to go into auto-target.h,
	11	this will have to do. */

Lines 1-11 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-libobjc-Makefile.in (-11 lines)
1	--- ./libobjc/Makefile.in.orig 2010-12-23 11:26:14.000000000 +0000
2	+++ ./libobjc/Makefile.in 2012-01-21 14:11:19.000000000 +0000
3	@@ -74,7 +74,7 @@
4	RANLIB = @RANLIB@
5
6	CC = @CC@
7	-CFLAGS = @CFLAGS@
8	+CFLAGS = -G 0 -G0 @CFLAGS@
9	WARN_CFLAGS = -W -Wall -Wwrite-strings -Wstrict-prototypes
10	ALL_CFLAGS = -I. -I$(srcdir) $(CPPFLAGS) $(DEFS) $(CFLAGS) $(WARN_CFLAGS) \
11	-DIN_GCC -DIN_TARGET_LIBS -fno-strict-aliasing -fexceptions




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%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/emit-rtl.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/except.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/filenames.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/fixed-value.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/flag-types.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/flags.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/fold-const.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/function.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gcc-plugin.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gcc-symtab.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/genrtl.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ggc.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-builder.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-expr.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-fold.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-iterator.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-low.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-pretty-print.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-ssa.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple-walk.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimple.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimplify-me.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gimplify.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gsstruct.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gtm-builtins.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/gtype-desc.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/hard-reg-set.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/hash-table.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/hashtab.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/highlev-plugin-common.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/hwint.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/incpath.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/input.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/insn-codes.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/insn-constants.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/insn-flags.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/insn-modes.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/insn-notes.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/internal-fn.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/internal-fn.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/intl.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ipa-prop.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ipa-ref-inline.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ipa-ref.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ipa-reference.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ipa-utils.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/is-a.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/java/java-tree.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/langhooks.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/libiberty.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/line-map.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/machmode.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/md5.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/mode-classes.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/objc/objc-tree.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/obstack.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/omp-builtins.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/options.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/opts.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/output.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/params.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/params.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/pass-instances.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/pass_manager.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/plugin-api.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/plugin-version.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/plugin.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/plugin.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/pointer-set.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/predict.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/predict.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/prefix.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/pretty-print.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/print-rtl.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/print-tree.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/real.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/realmpfr.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/reg-notes.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/regset.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/resource.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/rtl.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/rtl.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/safe-ctype.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/sanitizer.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/sbitmap.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/splay-tree.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/ssa-iterators.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/statistics.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/stmt.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/stor-layout.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/stringpool.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/symtab.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/sync-builtins.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/system.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/target-hooks-macros.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/target.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/target.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/timevar.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/timevar.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tm-preds.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tm.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tm_p.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/toplev.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-cfg.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-cfgcleanup.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-check.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-core.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-dfa.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-dump.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-eh.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-hasher.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-inline.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-into-ssa.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-iterator.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-nested.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-object-size.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-outof-ssa.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-parloops.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-pass.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-phinodes.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-pretty-print.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-address.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-alias.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-coalesce.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-dom.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-loop-ivopts.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-loop-manip.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-loop-niter.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-loop.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-operands.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-sccvn.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-ter.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-threadedge.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa-threadupdate.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssa.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree-ssanames.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/tree.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/treestruct.def
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/varasm.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/vec.h
%%PSP_GCC_STAGE_PREFIX%%/lib/gcc/psp/4.9.3/plugin/include/version.h
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/cc1
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/collect2
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/install-tools/fixinc.sh
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/install-tools/fixincl
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/install-tools/mkheaders
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/install-tools/mkinstalldirs
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/liblto_plugin.so
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/liblto_plugin.so.0
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/liblto_plugin.so.0.0.0
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/lto-wrapper
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/lto1
%%PSP_GCC_STAGE_PREFIX%%/libexec/gcc/psp/4.9.3/plugin/gengtype
@dir %%PSP_GCC_STAGE_PREFIX%%/include
@dir %%PSP_GCC_STAGE_PREFIX%%/psp/lib
@dir %%PSP_GCC_STAGE_PREFIX%%/share

Return to bug 238769

Lines 2-17 Link Here

(-)devel/psptoolchain-gcc-stage1/Makefile (-6 / +9 lines)
2	# $FreeBSD: head/devel/psptoolchain-gcc-stage1/Makefile 499897 2019-04-24 19:15:05Z jbeich $	2	# $FreeBSD: head/devel/psptoolchain-gcc-stage1/Makefile 499897 2019-04-24 19:15:05Z jbeich $
3		3
4	PORTNAME= gcc	4	PORTNAME= gcc
5	PORTVERSION= 4.6.2	5	PORTVERSION= 4.9.3
6	PORTREVISION?= 5	6	PORTREVISION?= 0
7	CATEGORIES= devel	7	CATEGORIES= devel
8	MASTER_SITES= GCC/releases/${DISTNAME}	8	MASTER_SITES= GCC
9	PKGNAMEPREFIX= psptoolchain-	9	PKGNAMEPREFIX= psptoolchain-
10	PKGNAMESUFFIX?= -stage1	10	PKGNAMESUFFIX?= -stage1
11		11
12	MAINTAINER= tphilipp@potion-studios.com	12	MAINTAINER= tphilipp@potion-studios.com
13	COMMENT= PlayStation Portable development toolchain ${PORTNAME}	13	COMMENT= PlayStation Portable development toolchain ${PORTNAME}
14		14
		15	LICENSE= GPLv3
		16
15	ONLY_FOR_ARCHS= amd64 i386 powerpc64	17	ONLY_FOR_ARCHS= amd64 i386 powerpc64
16		18
17	LIB_DEPENDS= libgmp.so:math/gmp \	19	LIB_DEPENDS= libgmp.so:math/gmp \
Lines 34-40 Link Here
34	psp-strings:devel/psptoolchain-binutils \	36	psp-strings:devel/psptoolchain-binutils \
35	psp-strip:devel/psptoolchain-binutils	37	psp-strip:devel/psptoolchain-binutils
36		38
37	USES= gmake libtool tar:bzip2	39	USES+= gmake libtool tar:bzip2
38		40
39	MAKE_ENV+= PATH=${LOCALBASE}/${PSP_GCC_STAGE_PREFIX}/bin:${PREFIX}/bin:${PATH}	41	MAKE_ENV+= PATH=${LOCALBASE}/${PSP_GCC_STAGE_PREFIX}/bin:${PREFIX}/bin:${PATH}
40	HAS_CONFIGURE= yes	42	HAS_CONFIGURE= yes
Lines 52-62 Link Here
52	--with-ld=${LOCALBASE}/bin/psp-ld \	54	--with-ld=${LOCALBASE}/bin/psp-ld \
53	--with-as=${LOCALBASE}/bin/psp-as \	55	--with-as=${LOCALBASE}/bin/psp-as \
54	--mandir=${PREFIX}/man	56	--mandir=${PREFIX}/man
		57	CFLAGS+= -Wno-reserved-user-defined-literal
55	SSP_CFLAGS?= -fstack-protector # XXX -strong isn't supported by GCC < 4.9	58	SSP_CFLAGS?= -fstack-protector # XXX -strong isn't supported by GCC < 4.9
56		59
57	# make sure xgcc doesn't get any -march=... from env C(XX)?FLAGS (e.g. set by CPUTYPE in make.conf); also "disable" info file gen	60	# make sure xgcc doesn't get any -march=... from env C(XX)?FLAGS (e.g. set by CPUTYPE in make.conf); also "disable" info file gen
58	CONFIGURE_ENV+= CFLAGS_FOR_TARGET="${CFLAGS:C/(^\|[[:space:]])-march=[^[:space:]]*//g}" \	61	CONFIGURE_ENV+= CFLAGS_FOR_TARGET="${CFLAGS:C/(^\|[[:space:]])-march=[^[:space:]]*//g} ${XGCC_FLAGS}" \
59	CXXFLAGS_FOR_TARGET="${CXXFLAGS:C/(^\|[[:space:]])-march=[^[:space:]]*//g}" \	62	CXXFLAGS_FOR_TARGET="${CXXFLAGS:C/(^\|[[:space:]])-march=[^[:space:]]*//g} ${XGCC_FLAGS}" \
60	MAKEINFO=true	63	MAKEINFO=true
61		64
62	# Don't install any documentation for psptoolchain's gcc stage 1 - makes no sense.	65	# Don't install any documentation for psptoolchain's gcc stage 1 - makes no sense.

Lines 1-29 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-config.sub (-10 / +10 lines)
1	--- ./config.sub.orig 2010-05-25 13:22:07.000000000 +0000	1	--- config.sub.orig 2013-10-01 16:50:56 UTC
2	+++ ./config.sub 2012-01-21 14:11:18.000000000 +0000	2	+++ config.sub
3	@@ -279,6 +279,7 @@	3	@@ -289,6 +289,7 @@ case $basic_machine in
4	\| mipsisa64sb1 \| mipsisa64sb1el \
5	\| mipsisa64sr71k \| mipsisa64sr71kel \	4	\| mipsisa64sr71k \| mipsisa64sr71kel \
		5	\| mipsr5900 \| mipsr5900el \
6	\| mipstx39 \| mipstx39el \	6	\| mipstx39 \| mipstx39el \
7	+ \| mipsallegrex \| mipsallegrexel \	7	+ \| mipsallegrex \| mipsallegrexel \
8	\| mn10200 \| mn10300 \	8	\| mn10200 \| mn10300 \
9	\| moxie \	9	\| moxie \
10	\| mt \	10	\| mt \
11	@@ -375,6 +376,7 @@	11	@@ -408,6 +409,7 @@ case $basic_machine in
12	\| mipsisa64sb1-* \| mipsisa64sb1el-* \
13	\| mipsisa64sr71k-* \| mipsisa64sr71kel-* \	12	\| mipsisa64sr71k-* \| mipsisa64sr71kel-* \
		13	\| mipsr5900-* \| mipsr5900el-* \
14	\| mipstx39-* \| mipstx39el-* \	14	\| mipstx39-* \| mipstx39el-* \
15	+ \| mipsallegrex-* \| mipsallegrexel-* \	15	+ \| mipsallegrex-* \| mipsallegrexel-* \
16	\| mmix-* \	16	\| mmix-* \
17	\| mt-* \	17	\| mt-* \
18	\| msp430-* \	18	\| msp430-* \
19	@@ -771,6 +773,10 @@	19	@@ -809,6 +811,10 @@ case $basic_machine in
		20	mint \| -mint[0-9] \| MiNT \| MiNT[0-9]*)
20	basic_machine=m68k-atari	21	basic_machine=m68k-atari
21	os=-mint	22	os=-mint
22	;;	23	+ ;;
23	+ psp)	24	+ psp)
24	+ basic_machine=mipsallegrexel-psp	25	+ basic_machine=mipsallegrexel-psp
25	+ os=-elf	26	+ os=-elf
26	+ ;;	27	;;
27	mips3-)	28	mips3-)
28	basic_machine=`echo $basic_machine \| sed -e 's/mips3/mips64/'`	29	basic_machine=`echo $basic_machine \| sed -e 's/mips3/mips64/'`
29	;;

Lines 1-194 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-allegrex.md (-194 lines)
1	--- ./gcc/config/mips/allegrex.md.orig 2012-01-21 14:11:18.000000000 +0000
2	+++ ./gcc/config/mips/allegrex.md 2012-01-21 14:11:18.000000000 +0000
3	@@ -0,0 +1,191 @@
4	+;; Sony ALLEGREX instructions.
5	+;; Copyright (C) 2005 Free Software Foundation, Inc.
6	+;;
7	+;; This file is part of GCC.
8	+;;
9	+;; GCC is free software; you can redistribute it and/or modify
10	+;; it under the terms of the GNU General Public License as published by
11	+;; the Free Software Foundation; either version 2, or (at your option)
12	+;; any later version.
13	+;;
14	+;; GCC is distributed in the hope that it will be useful,
15	+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16	+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	+;; GNU General Public License for more details.
18	+;;
19	+;; You should have received a copy of the GNU General Public License
20	+;; along with GCC; see the file COPYING. If not, write to
21	+;; the Free Software Foundation, 59 Temple Place - Suite 330,
22	+;; Boston, MA 02111-1307, USA.
23	+
24	+(define_c_enum "unspec" [
25	+ UNSPEC_WSBH
26	+ UNSPEC_CLO
27	+ UNSPEC_CTO
28	+ UNSPEC_CACHE
29	+ UNSPEC_CEIL_W_S
30	+ UNSPEC_FLOOR_W_S
31	+ UNSPEC_ROUND_W_S
32	+])
33	+
34	+;; Multiply Add and Subtract.
35	+;; Note: removed clobbering for madd and msub (testing needed)
36	+
37	+(define_insn "allegrex_madd"
38	+ [(set (match_operand:SI 0 "register_operand" "+l")
39	+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
40	+ (match_operand:SI 2 "register_operand" "d"))
41	+ (match_dup 0)))]
42	+ "TARGET_ALLEGREX"
43	+ "madd\t%1,%2"
44	+ [(set_attr "type" "imadd")
45	+ (set_attr "mode" "SI")])
46	+
47	+(define_insn "allegrex_msub"
48	+ [(set (match_operand:SI 0 "register_operand" "+l")
49	+ (minus:SI (match_dup 0)
50	+ (mult:SI (match_operand:SI 1 "register_operand" "d")
51	+ (match_operand:SI 2 "register_operand" "d"))))]
52	+ "TARGET_ALLEGREX"
53	+ "msub\t%1,%2"
54	+ [(set_attr "type" "imadd")
55	+ (set_attr "mode" "SI")])
56	+
57	+
58	+;; Min and max.
59	+
60	+(define_insn "sminsi3"
61	+ [(set (match_operand:SI 0 "register_operand" "=d")
62	+ (smin:SI (match_operand:SI 1 "register_operand" "d")
63	+ (match_operand:SI 2 "register_operand" "d")))]
64	+ "TARGET_ALLEGREX"
65	+ "min\t%0,%1,%2"
66	+ [(set_attr "type" "arith")
67	+ (set_attr "mode" "SI")])
68	+
69	+(define_insn "smaxsi3"
70	+ [(set (match_operand:SI 0 "register_operand" "=d")
71	+ (smax:SI (match_operand:SI 1 "register_operand" "d")
72	+ (match_operand:SI 2 "register_operand" "d")))]
73	+ "TARGET_ALLEGREX"
74	+ "max\t%0,%1,%2"
75	+ [(set_attr "type" "arith")
76	+ (set_attr "mode" "SI")])
77	+
78	+
79	+;; Extended shift instructions.
80	+
81	+(define_insn "allegrex_bitrev"
82	+ [(set (match_operand:SI 0 "register_operand" "=d")
83	+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
84	+ UNSPEC_BITREV))]
85	+ "TARGET_ALLEGREX"
86	+ "bitrev\t%0,%1"
87	+ [(set_attr "type" "arith")
88	+ (set_attr "mode" "SI")])
89	+
90	+(define_insn "allegrex_wsbh"
91	+ [(set (match_operand:SI 0 "register_operand" "=d")
92	+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
93	+ UNSPEC_WSBH))]
94	+ "TARGET_ALLEGREX"
95	+ "wsbh\t%0,%1"
96	+ [(set_attr "type" "arith")
97	+ (set_attr "mode" "SI")])
98	+
99	+(define_insn "bswapsi2"
100	+ [(set (match_operand:SI 0 "register_operand" "=d")
101	+ (bswap:SI (match_operand:SI 1 "register_operand" "d")))]
102	+ "TARGET_ALLEGREX"
103	+ "wsbw\t%0,%1"
104	+ [(set_attr "type" "shift")
105	+ (set_attr "mode" "SI")])
106	+
107	+
108	+;; Count leading ones, count trailing zeros, and count trailing ones (clz is
109	+;; already defined).
110	+
111	+(define_insn "allegrex_clo"
112	+ [(set (match_operand:SI 0 "register_operand" "=d")
113	+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
114	+ UNSPEC_CLO))]
115	+ "TARGET_ALLEGREX"
116	+ "clo\t%0,%1"
117	+ [(set_attr "type" "clz")
118	+ (set_attr "mode" "SI")])
119	+
120	+(define_expand "ctzsi2"
121	+ [(set (match_operand:SI 0 "register_operand")
122	+ (ctz:SI (match_operand:SI 1 "register_operand")))]
123	+ "TARGET_ALLEGREX"
124	+{
125	+ rtx r1;
126	+
127	+ r1 = gen_reg_rtx (SImode);
128	+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
129	+ emit_insn (gen_clzsi2 (operands[0], r1));
130	+ DONE;
131	+})
132	+
133	+(define_expand "allegrex_cto"
134	+ [(set (match_operand:SI 0 "register_operand")
135	+ (unspec:SI [(match_operand:SI 1 "register_operand")]
136	+ UNSPEC_CTO))]
137	+ "TARGET_ALLEGREX"
138	+{
139	+ rtx r1;
140	+
141	+ r1 = gen_reg_rtx (SImode);
142	+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
143	+ emit_insn (gen_allegrex_clo (operands[0], r1));
144	+ DONE;
145	+})
146	+
147	+
148	+;; Misc.
149	+
150	+(define_insn "allegrex_sync"
151	+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
152	+ "TARGET_ALLEGREX"
153	+ "sync"
154	+ [(set_attr "type" "unknown")
155	+ (set_attr "mode" "none")])
156	+
157	+(define_insn "allegrex_cache"
158	+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
159	+ (match_operand:SI 1 "register_operand" "d")]
160	+ UNSPEC_CACHE)]
161	+ "TARGET_ALLEGREX"
162	+ "cache\t%0,0(%1)"
163	+ [(set_attr "type" "unknown")
164	+ (set_attr "mode" "none")])
165	+
166	+
167	+;; Floating-point builtins.
168	+
169	+(define_insn "allegrex_ceil_w_s"
170	+ [(set (match_operand:SI 0 "register_operand" "=f")
171	+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
172	+ UNSPEC_CEIL_W_S))]
173	+ "TARGET_ALLEGREX"
174	+ "ceil.w.s\t%0,%1"
175	+ [(set_attr "type" "fcvt")
176	+ (set_attr "mode" "SF")])
177	+
178	+(define_insn "allegrex_floor_w_s"
179	+ [(set (match_operand:SI 0 "register_operand" "=f")
180	+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
181	+ UNSPEC_FLOOR_W_S))]
182	+ "TARGET_ALLEGREX"
183	+ "floor.w.s\t%0,%1"
184	+ [(set_attr "type" "fcvt")
185	+ (set_attr "mode" "SF")])
186	+
187	+(define_insn "allegrex_round_w_s"
188	+ [(set (match_operand:SI 0 "register_operand" "=f")
189	+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
190	+ UNSPEC_ROUND_W_S))]
191	+ "TARGET_ALLEGREX"
192	+ "round.w.s\t%0,%1"
193	+ [(set_attr "type" "fcvt")
194	+ (set_attr "mode" "SF")])

Lines 1-20 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips-ftypes.def (-20 lines)
1	--- ./gcc/config/mips/mips-ftypes.def.orig 2009-02-20 15:20:38.000000000 +0000
2	+++ ./gcc/config/mips/mips-ftypes.def 2012-01-21 14:11:18.000000000 +0000
3	@@ -53,9 +53,12 @@
4
5	DEF_MIPS_FTYPE (2, (SI, DI, SI))
6	DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
7	+DEF_MIPS_FTYPE (1, (SI, HI))
8	+DEF_MIPS_FTYPE (1, (SI, SF))
9	DEF_MIPS_FTYPE (1, (SI, SI))
10	DEF_MIPS_FTYPE (2, (SI, SI, SI))
11	DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
12	+DEF_MIPS_FTYPE (1, (SI, QI))
13	DEF_MIPS_FTYPE (1, (SI, V2HI))
14	DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
15	DEF_MIPS_FTYPE (1, (SI, V4QI))
16	@@ -124,3 +127,4 @@
17	DEF_MIPS_FTYPE (2, (VOID, SI, SI))
18	DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
19	DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
20	+DEF_MIPS_FTYPE (1, (VOID, VOID))

Lines 1-206 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.c (-206 lines)
1	--- ./gcc/config/mips/mips.c.orig 2011-05-29 17:48:14.000000000 +0000
2	+++ ./gcc/config/mips/mips.c 2012-01-21 14:11:18.000000000 +0000
3	@@ -239,7 +239,12 @@
4	MIPS_BUILTIN_CMP_SINGLE,
5
6	/* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
7	- MIPS_BUILTIN_BPOSGE32
8	+ MIPS_BUILTIN_BPOSGE32,
9	+
10	+ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
11	+ is the function code (must be less than 32) and operand 1 is the base
12	+ address. */
13	+ MIPS_BUILTIN_CACHE
14	};
15
16	/* Invoke MACRO (COND) for each C.cond.fmt condition. */
17	@@ -516,6 +521,10 @@
18	normal branch. */
19	static bool mips_branch_likely;
20
21	+/* Preferred stack boundary for proper stack vars alignment */
22	+unsigned int mips_preferred_stack_boundary;
23	+unsigned int mips_preferred_stack_align;
24	+
25	/* The current instruction-set architecture. */
26	enum processor mips_arch;
27	const struct mips_cpu_info *mips_arch_info;
28	@@ -691,6 +700,7 @@
29
30	/* MIPS II processors. */
31	{ "r6000", PROCESSOR_R6000, 2, 0 },
32	+ { "allegrex", PROCESSOR_ALLEGREX, 2, 0 },
33
34	/* MIPS III processors. */
35	{ "r4000", PROCESSOR_R4000, 3, 0 },
36	@@ -969,6 +979,9 @@
37	1, /* branch_cost */
38	4 /* memory_latency */
39	},
40	+ { /* Allegrex */
41	+ DEFAULT_COSTS
42	+ },
43	{ /* Loongson-2E */
44	DEFAULT_COSTS
45	},
46	@@ -12605,6 +12618,7 @@
47	AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
48	AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
49	AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
50	+AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
51
52	/* Construct a mips_builtin_description from the given arguments.
53
54	@@ -12701,6 +12715,30 @@
55	MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
56	MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
57
58	+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
59	+ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
60	+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
61	+ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
62	+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
63	+
64	+/* Same as the above, but mapped to an instruction that doesn't share the
65	+ NAME. NAME is the name of the builtin without the builtin prefix. */
66	+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
67	+ { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
68	+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
69	+
70	+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
71	+ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
72	+ builtin_description fields. */
73	+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
74	+ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
75	+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
76	+
77	+/* Define a builtin with a specific function TYPE. */
78	+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
79	+ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
80	+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
81	+
82	/* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
83	for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
84	builtin_description field. */
85	@@ -12945,6 +12983,40 @@
86	DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
87	DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
88
89	+/* Builtin functions for the Sony ALLEGREX processor.
90	+
91	+ These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
92	+ to maintain compatibility with Sony's ALLEGREX GCC port.
93	+
94	+ Some of the builtins may seem redundant, but they are the same as the
95	+ builtins defined in the Sony compiler. I chose to map redundant and
96	+ trivial builtins to the original instruction instead of creating
97	+ duplicate patterns specifically for the ALLEGREX (as Sony does). */
98	+
99	+ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
100	+ DIRECT_ALLEGREX_BUILTIN(wsbh, MIPS_SI_FTYPE_SI, 0),
101	+ DIRECT_ALLEGREX_NAMED_BUILTIN(wsbw, bswapsi2, MIPS_SI_FTYPE_SI, 0),
102	+ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
103	+ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
104	+ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
105	+ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
106	+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
107	+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
108	+
109	+ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
110	+ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
111	+ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
112	+ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
113	+
114	+ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
115	+ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
116	+
117	+ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
118	+ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
119	+ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
120	+ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
121	+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
122	+
123	/* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
124	LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
125	LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
126	@@ -13096,6 +13168,8 @@
127	/* Standard mode-based argument types. */
128	#define MIPS_ATYPE_UQI unsigned_intQI_type_node
129	#define MIPS_ATYPE_SI intSI_type_node
130	+#define MIPS_ATYPE_HI intHI_type_node
131	+#define MIPS_ATYPE_QI intQI_type_node
132	#define MIPS_ATYPE_USI unsigned_intSI_type_node
133	#define MIPS_ATYPE_DI intDI_type_node
134	#define MIPS_ATYPE_UDI unsigned_intDI_type_node
135	@@ -13270,6 +13344,9 @@
136
137	switch (opno)
138	{
139	+ case 0:
140	+ emit_insn (GEN_FCN (icode) (0));
141	+ break;
142	case 2:
143	emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
144	break;
145	@@ -13439,6 +13516,28 @@
146	const1_rtx, const0_rtx);
147	}
148
149	+/* Expand a __builtin_allegrex_cache() function. Make sure the passed
150	+ cache function code is less than 32. */
151	+
152	+static rtx
153	+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
154	+{
155	+ rtx op0, op1;
156	+
157	+ op0 = mips_prepare_builtin_arg (icode, 0, exp, 0);
158	+ op1 = mips_prepare_builtin_arg (icode, 1, exp, 1);
159	+
160	+ if (GET_CODE (op0) == CONST_INT)
161	+ if (INTVAL (op0) < 0 \|\| INTVAL (op0) > 0x1f)
162	+ {
163	+ error ("invalid function code '%d'", INTVAL (op0));
164	+ return const0_rtx;
165	+ }
166	+
167	+ emit_insn (GEN_FCN (icode) (op0, op1));
168	+ return target;
169	+}
170	+
171	/* Implement TARGET_EXPAND_BUILTIN. */
172
173	static rtx
174	@@ -13484,6 +13583,9 @@
175
176	case MIPS_BUILTIN_BPOSGE32:
177	return mips_expand_builtin_bposge (d->builtin_type, target);
178	+
179	+ case MIPS_BUILTIN_CACHE:
180	+ return mips_expand_builtin_cache (d->icode, target, exp);
181	}
182	gcc_unreachable ();
183	}
184	@@ -15918,6 +16020,22 @@
185	Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
186	MIPS16 mode afterwards if need be. */
187	mips_set_mips16_mode (false);
188	+
189	+ /* Validate -mpreferred-stack-boundary= value, or provide default.
190	+ The default of 128-bit is for newABI else 64-bit. */
191	+ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
192	+ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
193	+ if (mips_preferred_stack_boundary_string)
194	+ {
195	+ i = atoi (mips_preferred_stack_boundary_string);
196	+ if (i < 2 \|\| i > 12)
197	+ error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
198	+ else
199	+ {
200	+ mips_preferred_stack_align = (1 << i);
201	+ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
202	+ }
203	+ }
204	}
205
206	/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */

Lines 1-104 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.h (-104 lines)
1	--- ./gcc/config/mips/mips.h.orig 2011-03-08 20:51:11.000000000 +0000
2	+++ ./gcc/config/mips/mips.h 2012-01-21 14:11:18.000000000 +0000
3	@@ -231,6 +231,7 @@
4	#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
5	\|\| mips_arch == PROCESSOR_SB1A)
6	#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
7	+#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
8
9	/* Scheduling target defines. */
10	#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
11	@@ -258,6 +259,7 @@
12	#define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
13	#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
14	\|\| mips_tune == PROCESSOR_SB1A)
15	+#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
16
17	/* Whether vector modes and intrinsics for ST Microelectronics
18	Loongson-2E/2F processors should be enabled. In o32 pairs of
19	@@ -852,6 +854,9 @@
20	/* ISA has LDC1 and SDC1. */
21	#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
22
23	+/* ISA has just the integer condition move instructions (movn,movz) */
24	+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
25	+
26	/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
27	branch on CC, and move (both FP and non-FP) on CC. */
28	#define ISA_HAS_8CC (ISA_MIPS4 \
29	@@ -874,6 +879,7 @@
30
31	/* ISA has conditional trap instructions. */
32	#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
33	+ && !TARGET_ALLEGREX \
34	&& !TARGET_MIPS16)
35
36	/* ISA has integer multiply-accumulate instructions, madd and msub. */
37	@@ -910,6 +916,7 @@
38	/* ISA has count leading zeroes/ones instruction (not implemented). */
39	#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
40	\|\| ISA_MIPS32R2 \
41	+ \|\| TARGET_ALLEGREX \
42	\|\| ISA_MIPS64 \
43	\|\| ISA_MIPS64R2) \
44	&& !TARGET_MIPS16)
45	@@ -955,6 +962,7 @@
46	\|\| TARGET_MIPS5400 \
47	\|\| TARGET_MIPS5500 \
48	\|\| TARGET_SR71K \
49	+ \|\| TARGET_ALLEGREX \
50	\|\| TARGET_SMARTMIPS) \
51	&& !TARGET_MIPS16)
52
53	@@ -984,11 +992,13 @@
54
55	/* ISA includes the MIPS32r2 seb and seh instructions. */
56	#define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
57	+ \|\| TARGET_ALLEGREX \
58	\|\| ISA_MIPS64R2) \
59	&& !TARGET_MIPS16)
60
61	/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
62	#define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
63	+ \|\| TARGET_ALLEGREX \
64	\|\| ISA_MIPS64R2) \
65	&& !TARGET_MIPS16)
66
67	@@ -1038,7 +1048,8 @@
68	\|\| ISA_MIPS64 \
69	\|\| ISA_MIPS64R2 \
70	\|\| TARGET_MIPS5500 \
71	- \|\| TARGET_LOONGSON_2EF)
72	+ \|\| TARGET_LOONGSON_2EF \
73	+ \|\| TARGET_ALLEGREX)
74
75	/* ISA includes synci, jr.hb and jalr.hb. */
76	#define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
77	@@ -2133,7 +2144,7 @@
78	`crtl->outgoing_args_size'. */
79	#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
80
81	-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
82	+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
83
84	/* Symbolic macros for the registers used to return integer and floating
85	point values. */
86	@@ -2259,7 +2270,7 @@
87	/* Treat LOC as a byte offset from the stack pointer and round it up
88	to the next fully-aligned offset. */
89	#define MIPS_STACK_ALIGN(LOC) \
90	- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
91	+ (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
92
93
94	/* Output assembler code to FILE to increment profiler label # LABELNO
95	@@ -2911,6 +2922,9 @@
96	#endif
97	#endif
98
99	+extern unsigned int mips_preferred_stack_boundary;
100	+extern unsigned int mips_preferred_stack_align;
101	+
102	#ifndef HAVE_AS_TLS
103	#define HAVE_AS_TLS 0
104	#endif

Lines 1-143 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.md (-143 lines)
1	--- ./gcc/config/mips/mips.md.orig 2011-03-03 21:56:58.000000000 +0000
2	+++ ./gcc/config/mips/mips.md 2012-01-21 14:11:19.000000000 +0000
3	@@ -37,6 +37,7 @@
4	74kf2_1
5	74kf1_1
6	74kf3_2
7	+ allegrex
8	loongson_2e
9	loongson_2f
10	loongson_3a
11	@@ -598,7 +599,7 @@
12	;; This mode iterator allows :MOVECC to be used anywhere that a
13	;; conditional-move-type condition is needed.
14	(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
15	- (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")])
16	+ (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF && !TARGET_ALLEGREX")])
17
18	;; 32-bit integer moves for which we provide move patterns.
19	(define_mode_iterator IMOVE32
20	@@ -1885,11 +1886,11 @@
21	(mult:DI
22	(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
23	(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
24	- "!TARGET_64BIT && (ISA_HAS_MSAC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP)"
25	+ "!TARGET_64BIT && (ISA_HAS_MSAC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP \|\| TARGET_ALLEGREX)"
26	{
27	if (ISA_HAS_DSP_MULT)
28	return "msub<u>\t%q0,%1,%2";
29	- else if (TARGET_MIPS5500 \|\| GENERATE_MADD_MSUB)
30	+ else if (TARGET_MIPS5500 \|\| GENERATE_MADD_MSUB \|\| TARGET_ALLEGREX)
31	return "msub<u>\t%1,%2";
32	else
33	return "msac<u>\t$0,%1,%2";
34	@@ -2066,14 +2067,14 @@
35	(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
36	(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
37	(match_operand:DI 3 "register_operand" "0")))]
38	- "(TARGET_MAD \|\| ISA_HAS_MACC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP)
39	+ "(TARGET_MAD \|\| ISA_HAS_MACC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP \|\| TARGET_ALLEGREX)
40	&& !TARGET_64BIT"
41	{
42	if (TARGET_MAD)
43	return "mad<u>\t%1,%2";
44	else if (ISA_HAS_DSP_MULT)
45	return "madd<u>\t%q0,%1,%2";
46	- else if (GENERATE_MADD_MSUB \|\| TARGET_MIPS5500)
47	+ else if (GENERATE_MADD_MSUB \|\| TARGET_MIPS5500 \|\| TARGET_ALLEGREX)
48	return "madd<u>\t%1,%2";
49	else
50	/* See comment in macc. /
51	@@ -2500,6 +2501,33 @@
52	;;
53	;; ....................
54	;;
55	+;; FIND FIRST BIT INSTRUCTION
56	+;;
57	+;; ....................
58	+;;
59	+
60	+(define_expand "ffs<mode>2"
61	+ [(set (match_operand:GPR 0 "register_operand" "")
62	+ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
63	+ "ISA_HAS_CLZ_CLO"
64	+{
65	+ rtx r1, r2, r3, r4;
66	+
67	+ r1 = gen_reg_rtx (<MODE>mode);
68	+ r2 = gen_reg_rtx (<MODE>mode);
69	+ r3 = gen_reg_rtx (<MODE>mode);
70	+ r4 = gen_reg_rtx (<MODE>mode);
71	+ emit_insn (gen_neg<mode>2 (r1, operands[1]));
72	+ emit_insn (gen_and<mode>3 (r2, operands[1], r1));
73	+ emit_insn (gen_clz<mode>2 (r3, r2));
74	+ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
75	+ emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
76	+ DONE;
77	+})
78	+
79	+;;
80	+;; ....................
81	+;;
82	;; NEGATION and ONE'S COMPLEMENT
83	;;
84	;; ....................
85	@@ -2550,6 +2578,25 @@
86	[(set_attr "alu_type" "not")
87	(set_attr "mode" "<MODE>")])
88
89	+(define_expand "rotl<mode>3"
90	+ [(set (match_operand:GPR 0 "register_operand")
91	+ (rotate:GPR (match_operand:GPR 1 "register_operand")
92	+ (match_operand:SI 2 "arith_operand")))]
93	+ "ISA_HAS_ROR"
94	+{
95	+ rtx temp;
96	+
97	+ if (GET_CODE (operands[2]) == CONST_INT)
98	+ temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
99	+ else
100	+ {
101	+ temp = gen_reg_rtx (<MODE>mode);
102	+ emit_insn (gen_neg<mode>2 (temp, operands[2]));
103	+ }
104	+ emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
105	+ DONE;
106	+})
107	+
108	;;
109	;; ....................
110	;;
111	@@ -6301,7 +6348,7 @@
112	(const_int 0)])
113	(match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
114	(match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
115	- "ISA_HAS_CONDMOVE"
116	+ "ISA_HAS_CONDMOVE \|\| ISA_HAS_INT_CONDMOVE"
117	"@
118	mov%T4\t%0,%z2,%1
119	mov%t4\t%0,%z3,%1"
120	@@ -6331,8 +6378,12 @@
121	(if_then_else:GPR (match_dup 5)
122	(match_operand:GPR 2 "reg_or_0_operand")
123	(match_operand:GPR 3 "reg_or_0_operand")))]
124	- "ISA_HAS_CONDMOVE"
125	+ "ISA_HAS_CONDMOVE \|\| ISA_HAS_INT_CONDMOVE"
126	{
127	+ if (ISA_HAS_INT_CONDMOVE
128	+ && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
129	+ FAIL;
130	+
131	mips_expand_conditional_move (operands);
132	DONE;
133	})
134	@@ -6481,6 +6532,9 @@
135	; ST-Microelectronics Loongson-2E/2F-specific patterns.
136	(include "loongson.md")
137
138	+; Sony ALLEGREX instructions.
139	+(include "allegrex.md")
140	+
141	(define_c_enum "unspec" [
142	UNSPEC_ADDRESS_FIRST
143	])

Lines 1-12 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-mips.opt (-12 lines)
1	--- ./gcc/config/mips/mips.opt.orig 2011-02-17 01:59:04.000000000 +0000
2	+++ ./gcc/config/mips/mips.opt 2012-01-21 14:11:19.000000000 +0000
3	@@ -306,5 +306,9 @@
4	Target Report Var(TARGET_XGOT)
5	Lift restrictions on GOT size
6
7	+mpreferred-stack-boundary=
8	+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
9	+Attempt to keep stack aligned to this power of 2
10	+
11	noasmopt
12	Driver

Lines 1-34 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-psp.h (-34 lines)
1	--- ./gcc/config/mips/psp.h.orig 2012-01-21 14:11:19.000000000 +0000
2	+++ ./gcc/config/mips/psp.h 2012-01-21 14:11:19.000000000 +0000
3	@@ -0,0 +1,31 @@
4	+/* Support for Sony's Playstation Portable (PSP).
5	+ Copyright (C) 2005 Free Software Foundation, Inc.
6	+ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
7	+
8	+This file is part of GCC.
9	+
10	+GCC is free software; you can redistribute it and/or modify
11	+it under the terms of the GNU General Public License as published by
12	+the Free Software Foundation; either version 2, or (at your option)
13	+any later version.
14	+
15	+GCC is distributed in the hope that it will be useful,
16	+but WITHOUT ANY WARRANTY; without even the implied warranty of
17	+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18	+GNU General Public License for more details.
19	+
20	+You should have received a copy of the GNU General Public License
21	+along with GCC; see the file COPYING. If not, write to
22	+the Free Software Foundation, 59 Temple Place - Suite 330,
23	+Boston, MA 02111-1307, USA. */
24	+
25	+/* Override the startfile spec to include crt0.o. */
26	+#undef STARTFILE_SPEC
27	+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
28	+
29	+#undef SUBTARGET_CPP_SPEC
30	+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
31	+
32	+/* Get rid of the .pdr section. */
33	+#undef SUBTARGET_ASM_SPEC
34	+#define SUBTARGET_ASM_SPEC "-mno-pdr"

Lines 1-32 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config-mips-t-allegrex (-32 lines)
1	--- ./gcc/config/mips/t-allegrex.orig 2012-01-21 14:11:19.000000000 +0000
2	+++ ./gcc/config/mips/t-allegrex 2012-01-21 14:11:19.000000000 +0000
3	@@ -0,0 +1,29 @@
4	+# Suppress building libgcc1.a, since the MIPS compiler port is complete
5	+# and does not need anything from libgcc1.a.
6	+LIBGCC1 =
7	+CROSS_LIBGCC1 =
8	+
9	+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
10	+# Don't let CTOR_LIST end up in sdata section.
11	+CRTSTUFF_T_CFLAGS = -G 0
12	+
13	+# Assemble startup files.
14	+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
15	+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
16	+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
17	+
18	+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
19	+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
20	+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
21	+
22	+# We must build libgcc2.a with -G 0, in case the user wants to link
23	+# without the $gp register.
24	+TARGET_LIBGCC2_CFLAGS = -G 0
25	+
26	+# Build the libraries for both hard and soft floating point
27	+
28	+MULTILIB_OPTIONS =
29	+MULTILIB_DIRNAMES =
30	+
31	+LIBGCC = stmp-multilib
32	+INSTALL_LIBGCC = install-multilib

Lines 1-21 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc-config.gcc (-21 lines)
1	--- ./gcc/config.gcc.orig 2011-07-22 16:44:50.000000000 +0000
2	+++ ./gcc/config.gcc 2012-01-21 14:11:19.000000000 +0000
3	@@ -2033,6 +2033,18 @@
4	tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
5	tmake_file="mips/t-r3900 mips/t-libgcc-mips16"
6	;;
7	+mipsallegrex--elf \| mipsallegrexel--elf)
8	+ tm_file="elfos.h ${tm_file} mips/elf.h"
9	+ tmake_file=mips/t-allegrex
10	+ target_cpu_default="MASK_SINGLE_FLOAT\|MASK_DIVIDE_BREAKS"
11	+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
12	+ case ${target} in
13	+ mipsallegrex-psp-elf)
14	+ tm_file="${tm_file} mips/psp.h"
15	+ ;;
16	+ esac
17	+ use_fixproto=yes
18	+ ;;
19	mmix-knuth-mmixware)
20	tm_file="${tm_file} newlib-stdint.h"
21	need_64bit_hwint=yes

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config.gcc (+21 lines)
	1	--- gcc/config.gcc.orig 2015-05-21 20:50:59 UTC
	2	+++ gcc/config.gcc
	3	@@ -2118,6 +2118,18 @@ mipstx39--elf \| mipstx39el--elf)
	4	tm_file="elfos.h newlib-stdint.h ${tm_file} mips/r3900.h mips/elf.h"
	5	tmake_file="mips/t-r3900"
	6	;;
	7	+mipsallegrex--elf \| mipsallegrexel--elf)
	8	+ tm_file="elfos.h ${tm_file} mips/elf.h"
	9	+ tmake_file=mips/t-allegrex
	10	+ target_cpu_default="MASK_SINGLE_FLOAT\|MASK_DIVIDE_BREAKS"
	11	+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
	12	+ case ${target} in
	13	+ mipsallegrex-psp-elf)
	14	+ tm_file="${tm_file} mips/psp.h"
	15	+ ;;
	16	+ esac
	17	+ use_fixproto=yes
	18	+ ;;
	19	mmix-knuth-mmixware)
	20	tm_file="${tm_file} newlib-stdint.h"
	21	need_64bit_hwint=yes

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_allegrex.md (+175 lines)
		1	--- gcc/config/mips/allegrex.md.orig 2019-06-06 21:32:32 UTC
		2	+++ gcc/config/mips/allegrex.md
		3	@@ -0,0 +1,172 @@
		4	+;; Sony ALLEGREX instructions.
		5	+;; Copyright (C) 2005 Free Software Foundation, Inc.
		6	+;;
		7	+;; This file is part of GCC.
		8	+;;
		9	+;; GCC is free software; you can redistribute it and/or modify
		10	+;; it under the terms of the GNU General Public License as published by
		11	+;; the Free Software Foundation; either version 2, or (at your option)
		12	+;; any later version.
		13	+;;
		14	+;; GCC is distributed in the hope that it will be useful,
		15	+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
		16	+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		17	+;; GNU General Public License for more details.
		18	+;;
		19	+;; You should have received a copy of the GNU General Public License
		20	+;; along with GCC; see the file COPYING. If not, write to
		21	+;; the Free Software Foundation, 59 Temple Place - Suite 330,
		22	+;; Boston, MA 02111-1307, USA.
		23	+
		24	+(define_c_enum "unspec" [
		25	+ UNSPEC_CLO
		26	+ UNSPEC_CTO
		27	+ UNSPEC_CACHE
		28	+ UNSPEC_CEIL_W_S
		29	+ UNSPEC_FLOOR_W_S
		30	+ UNSPEC_ROUND_W_S
		31	+])
		32	+
		33	+;; Multiply Add and Subtract.
		34	+;; Note: removed clobbering for madd and msub (testing needed)
		35	+
		36	+(define_insn "allegrex_madd"
		37	+ [(set (match_operand:SI 0 "register_operand" "+l")
		38	+ (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
		39	+ (match_operand:SI 2 "register_operand" "d"))
		40	+ (match_dup 0)))]
		41	+ "TARGET_ALLEGREX"
		42	+ "madd\t%1,%2"
		43	+ [(set_attr "type" "imadd")
		44	+ (set_attr "mode" "SI")])
		45	+
		46	+(define_insn "allegrex_msub"
		47	+ [(set (match_operand:SI 0 "register_operand" "+l")
		48	+ (minus:SI (match_dup 0)
		49	+ (mult:SI (match_operand:SI 1 "register_operand" "d")
		50	+ (match_operand:SI 2 "register_operand" "d"))))]
		51	+ "TARGET_ALLEGREX"
		52	+ "msub\t%1,%2"
		53	+ [(set_attr "type" "imadd")
		54	+ (set_attr "mode" "SI")])
		55	+
		56	+
		57	+;; Min and max.
		58	+
		59	+(define_insn "sminsi3"
		60	+ [(set (match_operand:SI 0 "register_operand" "=d")
		61	+ (smin:SI (match_operand:SI 1 "register_operand" "d")
		62	+ (match_operand:SI 2 "register_operand" "d")))]
		63	+ "TARGET_ALLEGREX"
		64	+ "min\t%0,%1,%2"
65	+ [(set_attr "type" "arith")
66	+ (set_attr "mode" "SI")])
67	+
68	+(define_insn "smaxsi3"
69	+ [(set (match_operand:SI 0 "register_operand" "=d")
70	+ (smax:SI (match_operand:SI 1 "register_operand" "d")
71	+ (match_operand:SI 2 "register_operand" "d")))]
72	+ "TARGET_ALLEGREX"
73	+ "max\t%0,%1,%2"
74	+ [(set_attr "type" "arith")
75	+ (set_attr "mode" "SI")])
76	+
77	+
78	+;; Extended shift instructions.
79	+
80	+(define_insn "allegrex_bitrev"
81	+ [(set (match_operand:SI 0 "register_operand" "=d")
82	+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
83	+ UNSPEC_BITREV))]
84	+ "TARGET_ALLEGREX"
85	+ "bitrev\t%0,%1"
86	+ [(set_attr "type" "arith")
87	+ (set_attr "mode" "SI")])
88	+
89	+;; Count leading ones, count trailing zeros, and count trailing ones (clz is
90	+;; already defined).
91	+
92	+(define_insn "allegrex_clo"
93	+ [(set (match_operand:SI 0 "register_operand" "=d")
94	+ (unspec:SI [(match_operand:SI 1 "register_operand" "d")]
95	+ UNSPEC_CLO))]
96	+ "TARGET_ALLEGREX"
97	+ "clo\t%0,%1"
98	+ [(set_attr "type" "clz")
99	+ (set_attr "mode" "SI")])
100	+
101	+(define_expand "ctzsi2"
102	+ [(set (match_operand:SI 0 "register_operand")
103	+ (ctz:SI (match_operand:SI 1 "register_operand")))]
104	+ "TARGET_ALLEGREX"
105	+{
106	+ rtx r1;
107	+
108	+ r1 = gen_reg_rtx (SImode);
109	+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
110	+ emit_insn (gen_clzsi2 (operands[0], r1));
111	+ DONE;
112	+})
113	+
114	+(define_expand "allegrex_cto"
115	+ [(set (match_operand:SI 0 "register_operand")
116	+ (unspec:SI [(match_operand:SI 1 "register_operand")]
117	+ UNSPEC_CTO))]
118	+ "TARGET_ALLEGREX"
119	+{
120	+ rtx r1;
121	+
122	+ r1 = gen_reg_rtx (SImode);
123	+ emit_insn (gen_allegrex_bitrev (r1, operands[1]));
124	+ emit_insn (gen_allegrex_clo (operands[0], r1));
125	+ DONE;
126	+})
127	+
128	+
129	+;; Misc.
130	+
131	+(define_insn "allegrex_sync"
132	+ [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)]
133	+ "TARGET_ALLEGREX"
134	+ "sync"
135	+ [(set_attr "type" "unknown")
136	+ (set_attr "mode" "none")])
137	+
138	+(define_insn "allegrex_cache"
139	+ [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "")
140	+ (match_operand:SI 1 "register_operand" "d")]
141	+ UNSPEC_CACHE)]
142	+ "TARGET_ALLEGREX"
143	+ "cache\t%0,0(%1)"
144	+ [(set_attr "type" "unknown")
145	+ (set_attr "mode" "none")])
146	+
147	+
148	+;; Floating-point builtins.
149	+
150	+(define_insn "allegrex_ceil_w_s"
151	+ [(set (match_operand:SI 0 "register_operand" "=f")
152	+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
153	+ UNSPEC_CEIL_W_S))]
154	+ "TARGET_ALLEGREX"
155	+ "ceil.w.s\t%0,%1"
156	+ [(set_attr "type" "fcvt")
157	+ (set_attr "mode" "SF")])
158	+
159	+(define_insn "allegrex_floor_w_s"
160	+ [(set (match_operand:SI 0 "register_operand" "=f")
161	+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
162	+ UNSPEC_FLOOR_W_S))]
163	+ "TARGET_ALLEGREX"
164	+ "floor.w.s\t%0,%1"
165	+ [(set_attr "type" "fcvt")
166	+ (set_attr "mode" "SF")])
167	+
168	+(define_insn "allegrex_round_w_s"
169	+ [(set (match_operand:SI 0 "register_operand" "=f")
170	+ (unspec:SI [(match_operand:SF 1 "register_operand" "f")]
171	+ UNSPEC_ROUND_W_S))]
172	+ "TARGET_ALLEGREX"
173	+ "round.w.s\t%0,%1"
174	+ [(set_attr "type" "fcvt")
175	+ (set_attr "mode" "SF")])

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_mips-ftypes.def (+20 lines)
	1	--- gcc/config/mips/mips-ftypes.def.orig 2014-02-02 16:05:09 UTC
	2	+++ gcc/config/mips/mips-ftypes.def
	3	@@ -53,9 +53,12 @@ DEF_MIPS_FTYPE (4, (INT, V2SF, V2SF, V2SF, V2SF))
	4	DEF_MIPS_FTYPE (2, (SI, DI, SI))
	5	DEF_MIPS_FTYPE (2, (SI, POINTER, SI))
	6	DEF_MIPS_FTYPE (2, (DI, POINTER, SI))
	7	+DEF_MIPS_FTYPE (1, (SI, HI))
	8	+DEF_MIPS_FTYPE (1, (SI, SF))
	9	DEF_MIPS_FTYPE (1, (SI, SI))
	10	DEF_MIPS_FTYPE (2, (SI, SI, SI))
	11	DEF_MIPS_FTYPE (3, (SI, SI, SI, SI))
	12	+DEF_MIPS_FTYPE (1, (SI, QI))
	13	DEF_MIPS_FTYPE (1, (SI, V2HI))
	14	DEF_MIPS_FTYPE (2, (SI, V2HI, V2HI))
	15	DEF_MIPS_FTYPE (1, (SI, V4QI))
	16	@@ -127,3 +130,4 @@ DEF_MIPS_FTYPE (2, (VOID, SI, SI))
	17	DEF_MIPS_FTYPE (1, (VOID, USI))
	18	DEF_MIPS_FTYPE (2, (VOID, V2HI, V2HI))
	19	DEF_MIPS_FTYPE (2, (VOID, V4QI, V4QI))
	20	+DEF_MIPS_FTYPE (1, (VOID, VOID))

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_mips.c (+184 lines)
		1	--- gcc/config/mips/mips.c.orig 2014-03-08 09:27:23 UTC
		2	+++ gcc/config/mips/mips.c
		3	@@ -248,7 +248,12 @@ enum mips_builtin_type {
		4	MIPS_BUILTIN_CMP_SINGLE,
		5
		6	/* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
		7	- MIPS_BUILTIN_BPOSGE32
		8	+ MIPS_BUILTIN_BPOSGE32,
		9	+
		10	+ /* The builtin corresponds to the ALLEGREX cache instruction. Operand 0
		11	+ is the function code (must be less than 32) and operand 1 is the base
		12	+ address. */
		13	+ MIPS_BUILTIN_CACHE
		14	};
		15
		16	/* Invoke MACRO (COND) for each C.cond.fmt condition. */
		17	@@ -574,6 +579,10 @@ struct mips_asm_switch mips_noat = { "at", 0 };
		18	normal branch. */
		19	static bool mips_branch_likely;
		20
		21	+/* Preferred stack boundary for proper stack vars alignment */
		22	+unsigned int mips_preferred_stack_boundary;
		23	+unsigned int mips_preferred_stack_align;
		24	+
		25	/* The current instruction-set architecture. */
		26	enum processor mips_arch;
		27	const struct mips_cpu_info *mips_arch_info;
		28	@@ -919,6 +928,9 @@ static const struct mips_rtx_cost_data
		29	1, /* branch_cost */
		30	4 /* memory_latency */
		31	},
		32	+ { /* Allegrex */
		33	+ DEFAULT_COSTS
		34	+ },
		35	{ /* Loongson-2E */
		36	DEFAULT_COSTS
		37	},
		38	@@ -13780,6 +13792,7 @@ AVAIL_NON_MIPS16 (dsp_64, TARGET_64BIT && TARGET_DSP)
		39	AVAIL_NON_MIPS16 (dspr2_32, !TARGET_64BIT && TARGET_DSPR2)
		40	AVAIL_NON_MIPS16 (loongson, TARGET_LOONGSON_VECTORS)
		41	AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
		42	+AVAIL_NON_MIPS16 (allegrex, TARGET_ALLEGREX)
		43
		44	/* Construct a mips_builtin_description from the given arguments.
		45
		46	@@ -13876,6 +13889,30 @@ AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BUILTIN)
		47	MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
		48	MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
		49
		50	+/* Define a MIPS_BUILTIN_DIRECT function for instruction CODE_FOR_allegrex_<INSN>.
		51	+ FUNCTION_TYPE and TARGET_FLAGS are builtin_description fields. */
		52	+#define DIRECT_ALLEGREX_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
		53	+ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
		54	+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
		55	+
		56	+/* Same as the above, but mapped to an instruction that doesn't share the
		57	+ NAME. NAME is the name of the builtin without the builtin prefix. */
		58	+#define DIRECT_ALLEGREX_NAMED_BUILTIN(NAME, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
		59	+ { CODE_FOR_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #NAME, \
		60	+ MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, mips_builtin_avail_allegrex }
		61	+
		62	+/* Define a MIPS_BUILTIN_DIRECT_NO_TARGET function for instruction
		63	+ CODE_FOR_allegrex_<INSN>. FUNCTION_TYPE and TARGET_FLAGS are
		64	+ builtin_description fields. */
65	+#define DIRECT_ALLEGREX_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, TARGET_FLAGS) \
66	+ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
67	+ MIPS_BUILTIN_DIRECT_NO_TARGET, FUNCTION_TYPE, mips_builtin_avail_allegrex }
68	+
69	+/* Define a builtin with a specific function TYPE. */
70	+#define SPECIAL_ALLEGREX_BUILTIN(TYPE, INSN, FUNCTION_TYPE, TARGET_FLAGS) \
71	+ { CODE_FOR_allegrex_ ## INSN, MIPS_FP_COND_f, "__builtin_allegrex_" #INSN, \
72	+ MIPS_BUILTIN_ ## TYPE, FUNCTION_TYPE, mips_builtin_avail_allegrex }
73	+
74	/* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
75	for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
76	builtin_description field. */
77	@@ -14122,6 +14159,38 @@ static const struct mips_builtin_description mips_buil
78	DIRECT_BUILTIN (dpsqx_s_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
79	DIRECT_BUILTIN (dpsqx_sa_w_ph, MIPS_DI_FTYPE_DI_V2HI_V2HI, dspr2_32),
80
81	+/* Builtin functions for the Sony ALLEGREX processor.
82	+
83	+ These have the `__builtin_allegrex_' prefix instead of `__builtin_mips_'
84	+ to maintain compatibility with Sony's ALLEGREX GCC port.
85	+
86	+ Some of the builtins may seem redundant, but they are the same as the
87	+ builtins defined in the Sony compiler. I chose to map redundant and
88	+ trivial builtins to the original instruction instead of creating
89	+ duplicate patterns specifically for the ALLEGREX (as Sony does). */
90	+
91	+ DIRECT_ALLEGREX_BUILTIN(bitrev, MIPS_SI_FTYPE_SI, 0),
92	+ DIRECT_ALLEGREX_NAMED_BUILTIN(clz, clzsi2, MIPS_SI_FTYPE_SI, 0),
93	+ DIRECT_ALLEGREX_BUILTIN(clo, MIPS_SI_FTYPE_SI, 0),
94	+ DIRECT_ALLEGREX_NAMED_BUILTIN(ctz, ctzsi2, MIPS_SI_FTYPE_SI, 0),
95	+ DIRECT_ALLEGREX_BUILTIN(cto, MIPS_SI_FTYPE_SI, 0),
96	+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotr, rotrsi3, MIPS_SI_FTYPE_SI_SI, 0),
97	+ DIRECT_ALLEGREX_NAMED_BUILTIN(rotl, rotlsi3, MIPS_SI_FTYPE_SI_SI, 0),
98	+
99	+ DIRECT_ALLEGREX_NAMED_BUILTIN(seb, extendqisi2, MIPS_SI_FTYPE_QI, 0),
100	+ DIRECT_ALLEGREX_NAMED_BUILTIN(seh, extendhisi2, MIPS_SI_FTYPE_HI, 0),
101	+ DIRECT_ALLEGREX_NAMED_BUILTIN(max, smaxsi3, MIPS_SI_FTYPE_SI_SI, 0),
102	+ DIRECT_ALLEGREX_NAMED_BUILTIN(min, sminsi3, MIPS_SI_FTYPE_SI_SI, 0),
103	+
104	+ DIRECT_ALLEGREX_NO_TARGET_BUILTIN(sync, MIPS_VOID_FTYPE_VOID, 0),
105	+ SPECIAL_ALLEGREX_BUILTIN(CACHE, cache, MIPS_VOID_FTYPE_SI_SI, 0),
106	+
107	+ DIRECT_ALLEGREX_NAMED_BUILTIN(sqrt_s, sqrtsf2, MIPS_SF_FTYPE_SF, 0),
108	+ DIRECT_ALLEGREX_BUILTIN(ceil_w_s, MIPS_SI_FTYPE_SF, 0),
109	+ DIRECT_ALLEGREX_BUILTIN(floor_w_s, MIPS_SI_FTYPE_SF, 0),
110	+ DIRECT_ALLEGREX_BUILTIN(round_w_s, MIPS_SI_FTYPE_SF, 0),
111	+ DIRECT_ALLEGREX_NAMED_BUILTIN(trunc_w_s, fix_truncsfsi2_insn, MIPS_SI_FTYPE_SF, 0),
112	+
113	/* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
114	LOONGSON_BUILTIN (packsswh, MIPS_V4HI_FTYPE_V2SI_V2SI),
115	LOONGSON_BUILTIN (packsshb, MIPS_V8QI_FTYPE_V4HI_V4HI),
116	@@ -14273,6 +14342,8 @@ mips_build_cvpointer_type (void)
117	/* Standard mode-based argument types. */
118	#define MIPS_ATYPE_UQI unsigned_intQI_type_node
119	#define MIPS_ATYPE_SI intSI_type_node
120	+#define MIPS_ATYPE_HI intHI_type_node
121	+#define MIPS_ATYPE_QI intQI_type_node
122	#define MIPS_ATYPE_USI unsigned_intSI_type_node
123	#define MIPS_ATYPE_DI intDI_type_node
124	#define MIPS_ATYPE_UDI unsigned_intDI_type_node
125	@@ -14575,6 +14646,26 @@ mips_expand_builtin_bposge (enum mips_builtin_type bui
126	const1_rtx, const0_rtx);
127	}
128
129	+/* Expand a __builtin_allegrex_cache() function. Make sure the passed
130	+ cache function code is less than 32. */
131	+
132	+static rtx
133	+mips_expand_builtin_cache (enum insn_code icode, rtx target, tree exp)
134	+{
135	+ int argno;
136	+ struct expand_operand ops[2];
137	+
138	+ for (argno = 0; argno < 2; argno++)
139	+ mips_prepare_builtin_arg (&ops[argno], exp, argno);
140	+
141	+ if (GET_CODE(ops[0].value) != CONST_INT \|\|
142	+ INTVAL(ops[0].value) < 0 \|\| INTVAL(ops[0].value) > 0x1f)
143	+ error("Invalid first argument for cache builtin (0 <= arg <= 31)");
144	+
145	+ emit_insn(mips_expand_builtin_insn (icode, 2, ops, false));
146	+ return target;
147	+}
148	+
149	/* Implement TARGET_EXPAND_BUILTIN. */
150
151	static rtx
152	@@ -14620,6 +14711,9 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarg
153
154	case MIPS_BUILTIN_BPOSGE32:
155	return mips_expand_builtin_bposge (d->builtin_type, target);
156	+
157	+ case MIPS_BUILTIN_CACHE:
158	+ return mips_expand_builtin_cache (d->icode, target, exp);
159	}
160	gcc_unreachable ();
161	}
162	@@ -17376,6 +17470,22 @@ mips_option_override (void)
163
164	if (TARGET_HARD_FLOAT_ABI && TARGET_MIPS5900)
165	REAL_MODE_FORMAT (SFmode) = &spu_single_format;
166	+
167	+ /* Validate -mpreferred-stack-boundary= value, or provide default.
168	+ The default of 128-bit is for newABI else 64-bit. */
169	+ mips_preferred_stack_boundary = (TARGET_NEWABI ? 128 : 64);
170	+ mips_preferred_stack_align = (TARGET_NEWABI ? 16 : 8);
171	+ if (mips_preferred_stack_boundary_string)
172	+ {
173	+ i = atoi (mips_preferred_stack_boundary_string);
174	+ if (i < 2 \|\| i > 12)
175	+ error ("-mpreferred-stack-boundary=%d is not between 2 and 12", i);
176	+ else
177	+ {
178	+ mips_preferred_stack_align = (1 << i);
179	+ mips_preferred_stack_boundary = mips_preferred_stack_align * 8;
180	+ }
181	+ }
182	}
183
184	/* Swap the register information for registers I and I + 1, which

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_mips.h (+104 lines)
		1	--- gcc/config/mips/mips.h.orig 2015-02-26 10:40:06 UTC
		2	+++ gcc/config/mips/mips.h
		3	@@ -231,6 +231,7 @@ struct mips_cpu_info {
		4	#define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
		5	\|\| mips_arch == PROCESSOR_SB1A)
		6	#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
		7	+#define TARGET_ALLEGREX (mips_arch == PROCESSOR_ALLEGREX)
		8	#define TARGET_XLP (mips_arch == PROCESSOR_XLP)
		9
		10	/* Scheduling target defines. */
		11	@@ -260,6 +261,7 @@ struct mips_cpu_info {
		12	\|\| mips_tune == PROCESSOR_OCTEON2)
		13	#define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
		14	\|\| mips_tune == PROCESSOR_SB1A)
		15	+#define TUNE_ALLEGREX (mips_tune == PROCESSOR_ALLEGREX)
		16
		17	/* Whether vector modes and intrinsics for ST Microelectronics
		18	Loongson-2E/2F processors should be enabled. In o32 pairs of
		19	@@ -868,6 +870,9 @@ struct mips_cpu_info {
		20	&& !TARGET_MIPS5900 \
		21	&& !TARGET_MIPS16)
		22
		23	+/* ISA has just the integer condition move instructions (movn,movz) */
		24	+#define ISA_HAS_INT_CONDMOVE (TARGET_ALLEGREX)
		25	+
		26	/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
		27	branch on CC, and move (both FP and non-FP) on CC. */
		28	#define ISA_HAS_8CC (ISA_MIPS4 \
		29	@@ -895,6 +900,7 @@ struct mips_cpu_info {
		30
		31	/* ISA has conditional trap instructions. */
		32	#define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
		33	+ && !TARGET_ALLEGREX \
		34	&& !TARGET_MIPS16)
		35
		36	/* ISA has integer multiply-accumulate instructions, madd and msub. */
		37	@@ -938,6 +944,7 @@ struct mips_cpu_info {
		38	/* ISA has count leading zeroes/ones instruction (not implemented). */
		39	#define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
		40	\|\| ISA_MIPS32R2 \
		41	+ \|\| TARGET_ALLEGREX \
		42	\|\| ISA_MIPS64 \
		43	\|\| ISA_MIPS64R2) \
		44	&& !TARGET_MIPS16)
		45	@@ -983,6 +990,7 @@ struct mips_cpu_info {
		46	\|\| TARGET_MIPS5400 \
		47	\|\| TARGET_MIPS5500 \
		48	\|\| TARGET_SR71K \
		49	+ \|\| TARGET_ALLEGREX \
		50	\|\| TARGET_SMARTMIPS) \
		51	&& !TARGET_MIPS16)
		52
		53	@@ -1014,11 +1022,13 @@ struct mips_cpu_info {
		54
		55	/* ISA includes the MIPS32r2 seb and seh instructions. */
		56	#define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
		57	+ \|\| TARGET_ALLEGREX \
		58	\|\| ISA_MIPS64R2) \
		59	&& !TARGET_MIPS16)
		60
		61	/* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
		62	#define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
		63	+ \|\| TARGET_ALLEGREX \
		64	\|\| ISA_MIPS64R2) \
65	&& !TARGET_MIPS16)
66
67	@@ -1084,7 +1094,8 @@ struct mips_cpu_info {
68	\|\| ISA_MIPS64R2 \
69	\|\| TARGET_MIPS5500 \
70	\|\| TARGET_MIPS5900 \
71	- \|\| TARGET_LOONGSON_2EF)
72	+ \|\| TARGET_LOONGSON_2EF \
73	+ \|\| TARGET_ALLEGREX)
74
75	/* ISA includes synci, jr.hb and jalr.hb. */
76	#define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
77	@@ -2209,7 +2220,7 @@ enum reg_class
78	`crtl->outgoing_args_size'. */
79	#define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
80
81	-#define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
82	+#define STACK_BOUNDARY (mips_preferred_stack_boundary)
83
84	/* Symbolic macros for the registers used to return integer and floating
85	point values. */
86	@@ -2321,7 +2332,7 @@ typedef struct mips_args {
87	/* Treat LOC as a byte offset from the stack pointer and round it up
88	to the next fully-aligned offset. */
89	#define MIPS_STACK_ALIGN(LOC) \
90	- (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
91	+ (((LOC) + (mips_preferred_stack_align - 1)) & -(mips_preferred_stack_align))
92
93
94	/* Output assembler code to FILE to increment profiler label # LABELNO
95	@@ -2936,6 +2947,9 @@ while (0)
96	.set pop\n\
97	" TEXT_SECTION_ASM_OP);
98	#endif
99	+
100	+extern unsigned int mips_preferred_stack_boundary;
101	+extern unsigned int mips_preferred_stack_align;
102
103	#ifndef HAVE_AS_TLS
104	#define HAVE_AS_TLS 0

Line 0 Link Here

(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_mips.md (+142 lines)
		1	--- gcc/config/mips/mips.md.orig 2014-02-02 16:05:09 UTC
		2	+++ gcc/config/mips/mips.md
		3	@@ -35,6 +35,7 @@
		4	74kf2_1
		5	74kf1_1
		6	74kf3_2
		7	+ allegrex
		8	loongson_2e
		9	loongson_2f
		10	loongson_3a
		11	@@ -756,6 +757,7 @@
		12	(define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
		13	(CC "TARGET_HARD_FLOAT
		14	&& !TARGET_LOONGSON_2EF
		15	+ && !TARGET_ALLEGREX
		16	&& !TARGET_MIPS5900")])
		17
		18	;; 32-bit integer moves for which we provide move patterns.
		19	@@ -2070,11 +2072,11 @@
		20	(mult:DI
		21	(any_extend:DI (match_operand:SI 1 "register_operand" "d"))
		22	(any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
		23	- "!TARGET_64BIT && (ISA_HAS_MSAC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP)"
		24	+ "!TARGET_64BIT && (ISA_HAS_MSAC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP \|\| TARGET_ALLEGREX)"
		25	{
		26	if (ISA_HAS_DSP_MULT)
		27	return "msub<u>\t%q0,%1,%2";
		28	- else if (TARGET_MIPS5500 \|\| GENERATE_MADD_MSUB)
		29	+ else if (TARGET_MIPS5500 \|\| GENERATE_MADD_MSUB \|\| TARGET_ALLEGREX)
		30	return "msub<u>\t%1,%2";
		31	else
		32	return "msac<u>\t$0,%1,%2";
		33	@@ -2312,14 +2314,14 @@
		34	(mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
		35	(any_extend:DI (match_operand:SI 2 "register_operand" "d")))
		36	(match_operand:DI 3 "muldiv_target_operand" "0")))]
		37	- "(TARGET_MAD \|\| ISA_HAS_MACC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP)
		38	+ "(TARGET_MAD \|\| ISA_HAS_MACC \|\| GENERATE_MADD_MSUB \|\| ISA_HAS_DSP \|\| TARGET_ALLEGREX)
		39	&& !TARGET_64BIT"
		40	{
		41	if (TARGET_MAD)
		42	return "mad<u>\t%1,%2";
		43	else if (ISA_HAS_DSP_MULT)
		44	return "madd<u>\t%q0,%1,%2";
		45	- else if (GENERATE_MADD_MSUB \|\| TARGET_MIPS5500)
		46	+ else if (GENERATE_MADD_MSUB \|\| TARGET_MIPS5500 \|\| TARGET_ALLEGREX)
		47	return "madd<u>\t%1,%2";
		48	else
		49	/* See comment in macc. /
		50	@@ -2857,6 +2859,33 @@
		51	;;
		52	;; ....................
		53	;;
		54	+;; FIND FIRST BIT INSTRUCTION
		55	+;;
		56	+;; ....................
		57	+;;
		58	+
		59	+(define_expand "ffs<mode>2"
		60	+ [(set (match_operand:GPR 0 "register_operand" "")
		61	+ (ffs:GPR (match_operand:GPR 1 "register_operand" "")))]
		62	+ "ISA_HAS_CLZ_CLO"
		63	+{
		64	+ rtx r1, r2, r3, r4;
65	+
66	+ r1 = gen_reg_rtx (<MODE>mode);
67	+ r2 = gen_reg_rtx (<MODE>mode);
68	+ r3 = gen_reg_rtx (<MODE>mode);
69	+ r4 = gen_reg_rtx (<MODE>mode);
70	+ emit_insn (gen_neg<mode>2 (r1, operands[1]));
71	+ emit_insn (gen_and<mode>3 (r2, operands[1], r1));
72	+ emit_insn (gen_clz<mode>2 (r3, r2));
73	+ emit_move_insn (r4, GEN_INT (GET_MODE_BITSIZE (<MODE>mode)));
74	+ emit_insn (gen_sub<mode>3 (operands[0], r4, r3));
75	+ DONE;
76	+})
77	+
78	+;;
79	+;; ....................
80	+;;
81	;; NEGATION and ONE'S COMPLEMENT
82	;;
83	;; ....................
84	@@ -2909,6 +2938,25 @@
85	(set_attr "compression" "micromips,*")
86	(set_attr "mode" "<MODE>")])
87
88	+(define_expand "rotl<mode>3"
89	+ [(set (match_operand:GPR 0 "register_operand")
90	+ (rotate:GPR (match_operand:GPR 1 "register_operand")
91	+ (match_operand:SI 2 "arith_operand")))]
92	+ "ISA_HAS_ROR"
93	+{
94	+ rtx temp;
95	+
96	+ if (GET_CODE (operands[2]) == CONST_INT)
97	+ temp = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - INTVAL (operands[2]));
98	+ else
99	+ {
100	+ temp = gen_reg_rtx (<MODE>mode);
101	+ emit_insn (gen_neg<mode>2 (temp, operands[2]));
102	+ }
103	+ emit_insn (gen_rotr<mode>3 (operands[0], operands[1], temp));
104	+ DONE;
105	+})
106	+
107	;;
108	;; ....................
109	;;
110	@@ -6869,7 +6917,7 @@
111	(const_int 0)])
112	(match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
113	(match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
114	- "ISA_HAS_CONDMOVE"
115	+ "ISA_HAS_CONDMOVE \|\| ISA_HAS_INT_CONDMOVE"
116	"@
117	mov%T4\t%0,%z2,%1
118	mov%t4\t%0,%z3,%1"
119	@@ -6912,8 +6960,12 @@
120	(if_then_else:GPR (match_dup 5)
121	(match_operand:GPR 2 "reg_or_0_operand")
122	(match_operand:GPR 3 "reg_or_0_operand")))]
123	- "ISA_HAS_CONDMOVE"
124	+ "ISA_HAS_CONDMOVE \|\| ISA_HAS_INT_CONDMOVE"
125	{
126	+ if (ISA_HAS_INT_CONDMOVE
127	+ && GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_FLOAT)
128	+ FAIL;
129	+
130	mips_expand_conditional_move (operands);
131	DONE;
132	})
133	@@ -7184,6 +7236,9 @@
134
135	; ST-Microelectronics Loongson-2E/2F-specific patterns.
136	(include "loongson.md")
137	+
138	+; Sony ALLEGREX instructions.
139	+(include "allegrex.md")
140
141	(define_c_enum "unspec" [
142	UNSPEC_ADDRESS_FIRST

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(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_mips.opt (+12 lines)
	1	--- gcc/config/mips/mips.opt.orig 2014-02-21 13:30:47 UTC
	2	+++ gcc/config/mips/mips.opt
	3	@@ -400,5 +400,9 @@ mxgot
	4	Target Report Var(TARGET_XGOT)
	5	Lift restrictions on GOT size
	6
	7	+mpreferred-stack-boundary=
	8	+Target RejectNegative Joined Var(mips_preferred_stack_boundary_string)
	9	+Attempt to keep stack aligned to this power of 2
	10	+
	11	noasmopt
	12	Driver

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(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_psp.h (+34 lines)
	1	--- gcc/config/mips/psp.h.orig 2019-06-06 21:32:32 UTC
	2	+++ gcc/config/mips/psp.h
	3	@@ -0,0 +1,31 @@
	4	+/* Support for Sony's Playstation Portable (PSP).
	5	+ Copyright (C) 2005 Free Software Foundation, Inc.
	6	+ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
	7	+
	8	+This file is part of GCC.
	9	+
	10	+GCC is free software; you can redistribute it and/or modify
	11	+it under the terms of the GNU General Public License as published by
	12	+the Free Software Foundation; either version 2, or (at your option)
	13	+any later version.
	14	+
	15	+GCC is distributed in the hope that it will be useful,
	16	+but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+GNU General Public License for more details.
	19	+
	20	+You should have received a copy of the GNU General Public License
	21	+along with GCC; see the file COPYING. If not, write to
	22	+the Free Software Foundation, 59 Temple Place - Suite 330,
	23	+Boston, MA 02111-1307, USA. */
	24	+
	25	+/* Override the startfile spec to include crt0.o. */
	26	+#undef STARTFILE_SPEC
	27	+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
	28	+
	29	+#undef SUBTARGET_CPP_SPEC
	30	+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
	31	+
	32	+/* Get rid of the .pdr section. */
	33	+#undef SUBTARGET_ASM_SPEC
	34	+#define SUBTARGET_ASM_SPEC "-mno-pdr"

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(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_config_mips_t-allegrex (+32 lines)
	1	--- gcc/config/mips/t-allegrex.orig 2019-06-06 21:32:32 UTC
	2	+++ gcc/config/mips/t-allegrex
	3	@@ -0,0 +1,29 @@
	4	+# Suppress building libgcc1.a, since the MIPS compiler port is complete
	5	+# and does not need anything from libgcc1.a.
	6	+LIBGCC1 =
	7	+CROSS_LIBGCC1 =
	8	+
	9	+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
	10	+# Don't let CTOR_LIST end up in sdata section.
	11	+CRTSTUFF_T_CFLAGS = -G 0
	12	+
	13	+# Assemble startup files.
	14	+$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
	15	+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
	16	+ -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
	17	+
	18	+$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
	19	+ $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
	20	+ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
	21	+
	22	+# We must build libgcc2.a with -G 0, in case the user wants to link
	23	+# without the $gp register.
	24	+TARGET_LIBGCC2_CFLAGS = -G 0
	25	+
	26	+# Build the libraries for both hard and soft floating point
	27	+
	28	+MULTILIB_OPTIONS =
	29	+MULTILIB_DIRNAMES =
	30	+
	31	+LIBGCC = stmp-multilib
	32	+INSTALL_LIBGCC = install-multilib

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(-)devel/psptoolchain-gcc-stage1/files/patch-gcc_gengtype.c (-18 lines)
1	--- gcc/gengtype.c.orig 2010-11-25 19:03:27.000000000 +0000
2	+++ gcc/gengtype.c
3	@@ -3594,14 +3594,13 @@ write_field_root (outf_p f, pair_p v, ty
4	int has_length, struct fileloc line, const char if_marked,
5	bool emit_pch, type_p field_type, const char *field_name)
6	{
7	+ struct pair newv;
8	/* If the field reference is relative to V, rather than to some
9	subcomponent of V, we can mark any subarrays with a single stride.
10	We're effectively treating the field as a global variable in its
11	own right. */
12	if (v && type == v->type)
13	{
14	- struct pair newv;
15	-
16	newv = *v;
17	newv.type = field_type;
18	newv.name = ACONCAT ((v->name, ".", field_name, NULL));

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(-)devel/psptoolchain-gcc-stage1/files/patch-libcpp_Makefile.in (+13 lines)
	1	--- libcpp/Makefile.in.orig 2015-06-26 17:59:14 UTC
	2	+++ libcpp/Makefile.in
	3	@@ -208,8 +208,8 @@ ifeq ($(DEPMODE),depmode=gcc3)
	4	# Note that we put the dependencies into a .Tpo file, then move them
	5	# into place if the compile succeeds. We need this because gcc does
	6	# not atomically write the dependency output file.
	7	-COMPILE = $(COMPILE.base) -o $@ -MT $@ -MMD -MP -MF $(DEPDIR)/$*.Tpo
	8	-POSTCOMPILE = @mv $(DEPDIR)/$.Tpo $(DEPDIR)/$.Po
	9	+COMPILE = $(COMPILE.base) -o $@
	10	+POSTCOMPILE =
	11	else
	12	COMPILE = source='$<' object='$@' libtool=no DEPDIR=$(DEPDIR) $(DEPMODE) \
	13	$(depcomp) $(COMPILE.base)

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_config.host (+35 lines)
	1	--- libgcc/config.host.orig 2014-03-27 15:40:31 UTC
	2	+++ libgcc/config.host
	3	@@ -140,11 +140,15 @@ microblaze--*)
	4	cpu_type=microblaze
	5	;;
	6	mips--*)
	7	- # All MIPS targets provide a full set of FP routines.
	8	cpu_type=mips
	9	tmake_file="mips/t-mips"
	10	if test "${libgcc_cv_mips_hard_float}" = yes; then
	11	- tmake_file="${tmake_file} t-hardfp-sfdf t-hardfp"
	12	+ if test "${libgcc_cv_mips_single_float}" = yes; then
	13	+ tmake_file="${tmake_file} t-hardfp-sf"
	14	+ else
	15	+ tmake_file="${tmake_file} t-hardfp-sfdf"
	16	+ fi
	17	+ tmake_file="${tmake_file} t-hardfp"
	18	else
	19	tmake_file="${tmake_file} t-softfp-sfdf"
	20	fi
	21	@@ -859,6 +863,14 @@ mips-wrs-vxworks)
	22	;;
	23	mipstx39--elf \| mipstx39el--elf)
	24	tmake_file="$tmake_file mips/t-crtstuff mips/t-mips16"
	25	+ ;;
	26	+mips-psp)
	27	+ tmake_file="${tmake_file} mips/t-allegrex"
	28	+ target_cpu_default="MASK_SINGLE_FLOAT\|MASK_DIVIDE_BREAKS"
	29	+ tm_file="${tm_file} mips/psp.h"
	30	+ extra_parts="$extra_parts crti.o crtn.o"
	31	+ use_fixproto=yes
	32	+ tm_defines="MIPS_ISA_DEFAULT=2 MIPS_CPU_STRING_DEFAULT=\\\"allegrex\\\" MIPS_ABI_DEFAULT=ABI_EABI"
	33	;;
	34	mmix-knuth-mmixware)
	35	extra_parts="crti.o crtn.o crtbegin.o crtend.o"

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_config_mips_psp.h (+34 lines)
	1	--- libgcc/config/mips/psp.h.orig 2019-06-06 21:32:32 UTC
	2	+++ libgcc/config/mips/psp.h
	3	@@ -0,0 +1,31 @@
	4	+/* Support for Sony's Playstation Portable (PSP).
	5	+ Copyright (C) 2005 Free Software Foundation, Inc.
	6	+ Contributed by Marcus R. Brown <mrbrown@ocgnet.org>
	7	+
	8	+This file is part of GCC.
	9	+
	10	+GCC is free software; you can redistribute it and/or modify
	11	+it under the terms of the GNU General Public License as published by
	12	+the Free Software Foundation; either version 2, or (at your option)
	13	+any later version.
	14	+
	15	+GCC is distributed in the hope that it will be useful,
	16	+but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	+GNU General Public License for more details.
	19	+
	20	+You should have received a copy of the GNU General Public License
	21	+along with GCC; see the file COPYING. If not, write to
	22	+the Free Software Foundation, 59 Temple Place - Suite 330,
	23	+Boston, MA 02111-1307, USA. */
	24	+
	25	+/* Override the startfile spec to include crt0.o. */
	26	+#undef STARTFILE_SPEC
	27	+#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
	28	+
	29	+#undef SUBTARGET_CPP_SPEC
	30	+#define SUBTARGET_CPP_SPEC "-DPSP=1 -D__psp__=1 -D_PSP=1"
	31	+
	32	+/* Get rid of the .pdr section. */
	33	+#undef SUBTARGET_ASM_SPEC
	34	+#define SUBTARGET_ASM_SPEC "-mno-pdr"

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_config_mips_t-allegrex (+23 lines)
	1	--- libgcc/config/mips/t-allegrex.orig 2019-06-06 21:32:32 UTC
	2	+++ libgcc/config/mips/t-allegrex
	3	@@ -0,0 +1,20 @@
	4	+# Suppress building libgcc1.a, since the MIPS compiler port is complete
	5	+# and does not need anything from libgcc1.a.
	6	+LIBGCC1 =
	7	+CROSS_LIBGCC1 =
	8	+
	9	+EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
	10	+# Don't let CTOR_LIST end up in sdata section.
	11	+CRTSTUFF_T_CFLAGS = -G 0
	12	+
	13	+# We must build libgcc2.a with -G 0, in case the user wants to link
	14	+# without the $gp register.
	15	+TARGET_LIBGCC2_CFLAGS = -G 0
	16	+
	17	+# Build the libraries for both hard and soft floating point
	18	+
	19	+MULTILIB_OPTIONS =
	20	+MULTILIB_DIRNAMES =
	21	+
	22	+LIBGCC = stmp-multilib
	23	+INSTALL_LIBGCC = install-multilib

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_config_t-hardfp (+42 lines)
	1	--- libgcc/config/t-hardfp.orig 2014-02-07 07:46:34 UTC
	2	+++ libgcc/config/t-hardfp
	3	@@ -50,12 +50,16 @@ hardfp_func_list += $(foreach pair, $(hardfp_extension
	4	hardfp_func_list += $(foreach pair, $(hardfp_truncations), \
	5	$(subst M,$(pair),truncM2))
	6
	7	+hardfp_suffixes := $(hardfp_int_modes) 2 3
	8	+
	9	# Regexp for matching a floating-point mode.
	10	hardfp_mode_regexp := $(shell echo $(hardfp_float_modes) \| sed 's/ /\\\|/g')
	11	+hardfp_mode_regexp_awk := $(shell echo $(hardfp_float_modes) \| sed 's/ /\|/g')
	12
	13	# Regexp for matching the end of a function name, after the last
	14	# floating-point mode.
	15	-hardfp_suffix_regexp := $(shell echo $(hardfp_int_modes) 2 3 \| sed 's/ /\\\|/g')
	16	+hardfp_suffix_regexp := $(shell echo $(hardfp_suffixes) \| sed 's/ /\\\|/g')
	17	+hardfp_suffix_regexp_awk := $(shell echo $(hardfp_suffixes) \| sed 's/ /\|/g')
	18
	19	# Add -D options to define:
	20	# FUNC: the function name (e.g. __addsf3)
	21	@@ -64,12 +68,20 @@ hardfp_suffix_regexp := $(shell echo $(hardfp_int_mode
	22	# TYPE: the last floating-point mode (e.g. sf)
	23	hardfp_defines_for = \
	24	$(shell echo $1 \| \
	25	- sed 's/\(.*\)\($(hardfp_mode_regexp)\)\($(hardfp_suffix_regexp)\\|\)$$/-DFUNC=__& -DOP_\1\3 -DTYPE=\2/')
	26	+ $(AWK) 'BEGIN{split("$(hardfp_mode_regexp_awk)",mode,"\|"); \
	27	+ split("$(hardfp_suffix_regexp_awk)",suffix,"\|")} \
	28	+ { sfx=""; for (s in suffix) if (match($$0, suffix[s]"$$")) { sfx=suffix[s]; break; } \
	29	+ o=substr($$0,0,length($$0)-length(sfx)); \
	30	+ for (m in mode) { if (match(o, mode[m]"$$")) { \
	31	+ op=substr(o,0,length(o)-length(mode[m])); \
	32	+ print"-DFUNC=__"$$0" -DOP_" op sfx" -DTYPE="mode[m];exit; }}}')
	33
	34	hardfp-o = $(patsubst %,%$(objext),$(hardfp_func_list))
	35	$(hardfp-o): %$(objext): $(srcdir)/config/hardfp.c
	36	@echo "Mode = $(hardfp_mode_regexp)"
	37	@echo "Suffix = $(hardfp_suffix_regexp)"
	38	+ $(info $(call hardfp_defines_for, $*))
	39	+ $(info $$=$)
	40	$(gcc_compile) $(call hardfp_defines_for, $*) -c $< $(vis_hide) -Wno-missing-prototypes
	41	libgcc-objects += $(hardfp-o)
	42

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_config_t-hardfp-sf (+35 lines)
	1	--- libgcc/config/t-hardfp-sf.orig 2019-06-06 21:40:23 UTC
	2	+++ libgcc/config/t-hardfp-sf
	3	@@ -0,0 +1,32 @@
	4	+# Copyright (C) 2014 Free Software Foundation, Inc.
	5	+
	6	+# This file is part of GCC.
	7	+
	8	+# GCC is free software; you can redistribute it and/or modify
	9	+# it under the terms of the GNU General Public License as published by
	10	+# the Free Software Foundation; either version 3, or (at your option)
	11	+# any later version.
	12	+
	13	+# GCC is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with GCC; see the file COPYING3. If not see
	20	+# <http://www.gnu.org/licenses/>.
	21	+
	22	+hardfp_float_modes := sf
	23	+# di and ti are provided by libgcc2.c where needed.
	24	+hardfp_int_modes := si
	25	+hardfp_extensions :=
	26	+hardfp_truncations :=
	27	+
	28	+# Emulate 64 bit float:
	29	+FPBIT = true
	30	+DPBIT = true
	31	+# Don't build functions handled by 32 bit hardware:
	32	+LIB2FUNCS_EXCLUDE = _addsub_sf _mul_sf _div_sf \
	33	+ _fpcmp_parts_sf _compare_sf _eq_sf _ne_sf _gt_sf _ge_sf \
	34	+ _lt_sf _le_sf _unord_sf _si_to_sf _sf_to_si _negate_sf \
	35	+ _thenan_sf _sf_to_usi _usi_to_sf

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_configure (+29 lines)
	1	--- libgcc/configure.orig 2014-02-07 07:46:34 UTC
	2	+++ libgcc/configure
	3	@@ -4352,6 +4352,26 @@ rm -f core conftest.err conftest.$ac_objext conftest.$
	4	fi
	5	{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_hard_float" >&5
	6	$as_echo "$libgcc_cv_mips_hard_float" >&6; }
	7	+ { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the target is single-float" >&5
	8	+$as_echo_n "checking whether the target is single-float... " >&6; }
	9	+if test "${libgcc_cv_mips_single_float+set}" = set; then :
	10	+ $as_echo_n "(cached) " >&6
	11	+else
	12	+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
	13	+/* end confdefs.h. */
	14	+#ifndef __mips_single_float
	15	+ #error FOO
	16	+ #endif
	17	+_ACEOF
	18	+if ac_fn_c_try_compile "$LINENO"; then :
	19	+ libgcc_cv_mips_single_float=yes
	20	+else
	21	+ libgcc_cv_mips_single_float=no
	22	+fi
	23	+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
	24	+fi
	25	+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $libgcc_cv_mips_single_float" >&5
	26	+$as_echo "$libgcc_cv_mips_single_float" >&6; }
	27	esac
	28
	29	# Collect host-machine-specific information.

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(-)devel/psptoolchain-gcc-stage1/files/patch-libgcc_configure.ac (+17 lines)
	1	--- libgcc/configure.ac.orig 2014-02-07 07:46:34 UTC
	2	+++ libgcc/configure.ac
	3	@@ -302,6 +302,14 @@ mips--*)
	4	#endif],
	5	[libgcc_cv_mips_hard_float=yes],
	6	[libgcc_cv_mips_hard_float=no])])
	7	+ AC_CACHE_CHECK([whether the target is single-float],
	8	+ [libgcc_cv_mips_single_float],
	9	+ [AC_COMPILE_IFELSE(
	10	+ [#ifndef __mips_single_float
	11	+ #error FOO
	12	+ #endif],
	13	+ [libgcc_cv_mips_single_float=yes],
	14	+ [libgcc_cv_mips_single_float=no])])
	15	esac
	16
	17	# Collect host-machine-specific information.