Lines 206-216
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return (0); |
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return (0); |
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} |
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} |
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/* |
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* During suspend we save registers and re-initialize them |
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* during resume. This is a list of the registers to save. |
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* |
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* IG4_REGS_CONTEXT_SIZE is the length of this array. |
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* It must be updated if this list is. |
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* |
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* The regs_context field of struct ig4iic_softc holds the |
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* values of the saved registers. |
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* |
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* -- NOTE: IG4_REG_I2C_EN MUST be the last register in the list -- |
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* certain registers require it to be disabled for them to be written |
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*/ |
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uint32_t regs_context_ids[IG4_REGS_CONTEXT_SIZE] = { |
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IG4_REG_CTL, |
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IG4_REG_TAR_ADD, |
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IG4_REG_DATA_CMD, |
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IG4_REG_SS_SCL_HCNT, |
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IG4_REG_SS_SCL_LCNT, |
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IG4_REG_FS_SCL_HCNT, |
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IG4_REG_FS_SCL_LCNT, |
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IG4_REG_INTR_MASK, |
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IG4_REG_RX_TL, |
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IG4_REG_TX_TL, |
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IG4_REG_SDA_HOLD, |
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IG4_REG_SLV_DATA_NACK, |
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IG4_REG_DMA_CTRL, |
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IG4_REG_DMA_TDLR, |
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IG4_REG_DMA_RDLR, |
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IG4_REG_SDA_SETUP, |
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IG4_REG_GENERAL, |
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IG4_REG_ACK_GENERAL_CALL, |
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IG4_REG_SW_LTR_VALUE, |
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IG4_REG_AUTO_LTR_VALUE, |
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IG4_REG_I2C_EN, |
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}; |
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|
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static int |
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ig4iic_pci_suspend(device_t dev) |
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{ |
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ig4iic_softc_t *sc; |
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|
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sc = device_get_softc(dev); |
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|
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/* RESETS spec (22.2.36) recommends saving and re-initializing registers */ |
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for (int i = 0; i < IG4_REGS_CONTEXT_SIZE; i++) { |
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sc->regs_context[i] = reg_read(sc, regs_context_ids[i]); |
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} |
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|
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/* |
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* reset the controller before we suspend |
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* Haswell and Skylake apparently have different RESET methods |
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*/ |
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if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { |
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reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); |
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|
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} else if (sc->version == IG4_SKYLAKE) { |
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/* |
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* |
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* set IG4_DEVICE_IDLE and IG4_RESTORE_REQUIRED |
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* to place the device in the idle state, just to be safe |
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*/ |
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reg_write(sc, IG4_REG_DEVIDLE_CTRL, |
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IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); |
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|
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reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); |
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|
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} else { |
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device_printf(dev, "Unable to assert reset, reset register unavailable\n"); |
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} |
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|
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/* suspend all children */ |
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return bus_generic_suspend(dev); |
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} |
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|
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static int |
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ig4iic_pci_resume(device_t dev) |
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{ |
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ig4iic_softc_t *sc; |
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|
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sc = device_get_softc(dev); |
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|
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/* wake the controller before its children */ |
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if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { |
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reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); |
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|
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} else if (sc->version == IG4_SKYLAKE) { |
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/* unset IG4_DEVICE_IDLE */ |
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reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); |
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reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); |
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|
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} else { |
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device_printf(dev, "Unable to deassert reset, reset register unavailable\n"); |
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} |
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|
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/* disable the controller before restoring registers */ |
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set_controller(sc, 0); |
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|
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/* |
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* set registers to values previously saved in regs_context |
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* this will re-enable the controller. |
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*/ |
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for (int i = 0; i < IG4_REGS_CONTEXT_SIZE; i++) { |
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reg_write(sc, regs_context_ids[i], sc->regs_context[i]); |
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} |
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|
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return bus_generic_resume(dev); |
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} |
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|
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static device_method_t ig4iic_pci_methods[] = { |
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static device_method_t ig4iic_pci_methods[] = { |
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/* Device interface */ |
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/* Device interface */ |
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DEVMETHOD(device_probe, ig4iic_pci_probe), |
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DEVMETHOD(device_probe, ig4iic_pci_probe), |
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DEVMETHOD(device_attach, ig4iic_pci_attach), |
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DEVMETHOD(device_attach, ig4iic_pci_attach), |
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DEVMETHOD(device_detach, ig4iic_pci_detach), |
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DEVMETHOD(device_detach, ig4iic_pci_detach), |
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|
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DEVMETHOD(device_suspend, ig4iic_pci_suspend), |
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DEVMETHOD(device_resume, ig4iic_pci_resume), |
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|
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|
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DEVMETHOD(iicbus_transfer, ig4iic_transfer), |
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DEVMETHOD(iicbus_transfer, ig4iic_transfer), |
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DEVMETHOD(iicbus_reset, ig4iic_reset), |
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DEVMETHOD(iicbus_reset, ig4iic_reset), |