Attachment #208621 for bug #241513




# $FreeBSD$

PORTNAME=	nextpnr
DISTVERSION=	g20191026
CATEGORIES=	cad
CATEGORIES=	devel

MAINTAINER=	manu@FreeBSD.org
COMMENT=	Portable FPGA place and route tool

LICENSE=	ISCL

		${PY_BOOST}

USES=		cmake qt:5 eigen:3 python:3.5+ gl

USE_QT=		buildtools_build core gui opengl qmake_build widgets
USE_GL=		gl glu

USE_GITHUB=	yes
GH_ACCOUNT=	YosysHQ
GH_TAGNAME=	5cf0ed5
GH_TUPLE=	YosysHQ:nextpnr-tests:8f93e7e:tests/tests

BINARY_ALIAS=	python3=${PYTHON_CMD}


Lines 1-3 Link Here

(-)cad/nextpnr/distinfo (-3 / +5 lines)
1	TIMESTAMP = 1560153617	1	TIMESTAMP = 1572127579
2	SHA256 (YosysHQ-nextpnr-g20190529-150004e3_GH0.tar.gz) = 10d04e5ae05144f3191d5a11219d7f8252d7cd52de7ac022b67020fe7797693f	2	SHA256 (YosysHQ-nextpnr-g20191026-5cf0ed5_GH0.tar.gz) = ed7566b3e09741a4d3ef0bc0f5854a1ad7157c0c715c6c692c0b7e8d00cb6b72
3	SIZE (YosysHQ-nextpnr-g20190529-150004e3_GH0.tar.gz) = 3191173	3	SIZE (YosysHQ-nextpnr-g20191026-5cf0ed5_GH0.tar.gz) = 3212729
		4	SHA256 (YosysHQ-nextpnr-tests-8f93e7e_GH0.tar.gz) = 5de9c0132957fcac6be6643a50499eb8d57402198b97ea20e684f9a0a10487a1
		5	SIZE (YosysHQ-nextpnr-tests-8f93e7e_GH0.tar.gz) = 1034317

Lines 6-8 Link Here

(-)cad/nextpnr/pkg-descr (+2 lines)
6	Lattice iCE40 devices supported by Project IceStorm	6	Lattice iCE40 devices supported by Project IceStorm
7	(experimental) Lattice ECP5 devices supported by Project Trellis	7	(experimental) Lattice ECP5 devices supported by Project Trellis
8	(experimental) a "generic" back-end for user-defined architectures	8	(experimental) a "generic" back-end for user-defined architectures
		9
		10	WWW: https://github.com/YosysHQ/nextpnr

Return to bug 241513

Lines 1-11 Link Here

(-)cad/nextpnr/Makefile (-8 / +6 lines)
1	# $FreeBSD$	1	# $FreeBSD$
2		2
3	PORTNAME= nextpnr	3	PORTNAME= nextpnr
4	PORTVERSION= g20190529	4	DISTVERSION= g20191026
5	PORTREVISION= 1	5	CATEGORIES= cad
6	CATEGORIES= devel
7		6
8	MAINTAINER= manu@FreeBSD.Org	7	MAINTAINER= manu@FreeBSD.org
9	COMMENT= Portable FPGA place and route tool	8	COMMENT= Portable FPGA place and route tool
10		9
11	LICENSE= ISCL	10	LICENSE= ISCL
Lines 19-31 Link Here
19	${PY_BOOST}	18	${PY_BOOST}
20		19
21	USES= cmake qt:5 eigen:3 python:3.5+ gl	20	USES= cmake qt:5 eigen:3 python:3.5+ gl
22
23	USE_QT= buildtools_build core gui opengl qmake_build widgets	21	USE_QT= buildtools_build core gui opengl qmake_build widgets
24	USE_GL= gl	22	USE_GL= gl glu
25
26	USE_GITHUB= yes	23	USE_GITHUB= yes
27	GH_ACCOUNT= YosysHQ	24	GH_ACCOUNT= YosysHQ
28	GH_TAGNAME= 150004e3	25	GH_TAGNAME= 5cf0ed5
		26	GH_TUPLE= YosysHQ:nextpnr-tests:8f93e7e:tests/tests
29		27
30	BINARY_ALIAS= python3=${PYTHON_CMD}	28	BINARY_ALIAS= python3=${PYTHON_CMD}
31		29