Attachment #211710 for bug #243657

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--- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig	2019-10-21 10:14:54 UTC
+++ src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c
@@ -14,49 +14,47 @@
 
 #include <openssl/cpu.h>
 

-
 extern uint32_t OPENSSL_armcap_P;
 
-void OPENSSL_cpuid_setup(void) {
-  unsigned long hwcap = getauxval(AT_HWCAP);
+#include <machine/armreg.h>
+
 void OPENSSL_cpuid_setup(void) {
-  unsigned long hwcap = getauxval(AT_HWCAP);
+  uint64_t id_aa64isar0;
 
-  // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
-  // these values.

-  static const unsigned long kPMULL = 1 << 4;
-  static const unsigned long kSHA1 = 1 << 5;
-  static const unsigned long kSHA256 = 1 << 6;
+#ifndef ID_AA64ISAR0_AES_VAL
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
+#endif
+#ifndef ID_AA64ISAR0_AES_VAL
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
+#endif
+#ifndef ID_AA64ISAR0_SHA1_VAL
+#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1
+#endif
+#ifndef ID_AA64ISAR0_SHA2_VAL
+#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2
+#endif
 
-  if ((hwcap & kNEON) == 0) {
-    // Matching OpenSSL, if NEON is missing, don't report other features

-    // either.
-    return;
-  }
+void OPENSSL_cpuid_setup(void) {
+  uint64_t id_aa64isar0;
 
+  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
+
   OPENSSL_armcap_P |= ARMV7_NEON;
 
-  if (hwcap & kAES) {
+  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
     OPENSSL_armcap_P |= ARMV8_AES;
   }
-  if (hwcap & kPMULL) {
+  if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
     OPENSSL_armcap_P |= ARMV8_PMULL;
   }
-  if (hwcap & kSHA1) {
+  if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
     OPENSSL_armcap_P |= ARMV8_SHA1;
   }
-  if (hwcap & kSHA256) {
+  if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
     OPENSSL_armcap_P |= ARMV8_SHA256;
   }
 }




--- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig	2019-10-21 10:14:54 UTC
+++ src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h
@@ -16,6 +16,29 @@
 
 #if HAVE_ARM64_CRC32C
 
+#if defined(__FreeBSD__)
+#include <machine/armreg.h>
+#ifndef ID_AA64ISAR0_AES_VAL
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
+#endif
+#ifndef ID_AA64ISAR0_CRC32_VAL
+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
+#endif
+namespace crc32c {
+
+inline bool CanUseArm64Linux() {
+  uint64_t id_aa64isar0;
+
+  id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
+  if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
+     (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
+    return true;
+  return false;
+}

 #if HAVE_STRONG_GETAUXVAL
 #include <sys/auxv.h>
 #elif HAVE_WEAK_GETAUXVAL
@@ -43,6 +66,7 @@ inline bool CanUseArm64Linux() {
 
 }  // namespace crc32c
 




--- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp	2019-10-21 10:14:54 UTC
+++ src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp
@@ -70,6 +70,23 @@
         return features;
     }
 
+#elif defined(SK_CPU_ARM64) && defined(__FreeBSD__)
+    #include <machine/armreg.h>
+    #ifndef ID_AA64ISAR0_CRC32_VAL
+    #define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
+    #endif
+
+    static uint32_t read_cpu_features() {
+        uint32_t features = 0;
+        uint64_t id_aa64isar0;
+
+        id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
+        if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {
+            features |= SkCpu::CRC32;
+        }
+        return features;

 #elif defined(SK_CPU_ARM64) && __has_include(<sys/auxv.h>)
     #include <sys/auxv.h>
 
@@ -78,7 +95,12 @@
                        kHWCAP_ASIMDHP = (1<<10);
 
         uint32_t features = 0;
+#if defined(__FreeBSD__)

+#else
         uint32_t hwcaps = getauxval(AT_HWCAP);
+#endif
         if (hwcaps & kHWCAP_CRC32  ) { features |= SkCpu::CRC32; }
         if (hwcaps & kHWCAP_ASIMDHP) { features |= SkCpu::ASIMDHP; }
         return features;




--- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig	2019-10-21 10:14:54 UTC
+++ src/3rdparty/chromium/third_party/zlib/arm_features.c
@@ -8,83 +8,36 @@
 
 #include "zutil.h"
 

 static void init_arm_features(void)
 {
-    uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0;
-
+    uint64_t id_aa64isar0;
 
-#if defined(ARMV8_OS_ANDROID)
-    flag_crc32 = ANDROID_CPU_ARM_FEATURE_CRC32;
-    flag_pmull = ANDROID_CPU_ARM_FEATURE_PMULL;

-        flag_pmull = HWCAP2_PMULL;
-        capabilities = getauxval(AT_HWCAP2);
-    #endif
+#if defined (__aarch64__)
+#ifndef ID_AA64ISAR0_AES_VAL
+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
 #endif
+#ifndef ID_AA64ISAR0_CRC32_VAL
+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
+#endif
+    uint64_t id_aa64isar0;
 
-    if (capabilities & flag_crc32)
-        arm_cpu_enable_crc32 = 1;
-
-    if (capabilities & flag_pmull)
+    id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
+    if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
         arm_cpu_enable_pmull = 1;
+    if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
+        arm_cpu_enable_crc32 = 1;
+#endif
 }

Return to bug 243657

Lines 1-6 Link Here

(-)www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_boringssl_src_crypto_cpu-aarch64-linux.c (-13 / +25 lines)
1	--- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig 2019-05-23 12:39:34 UTC	1	--- src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c.orig 2019-10-21 10:14:54 UTC
2	+++ src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c	2	+++ src/3rdparty/chromium/third_party/boringssl/src/crypto/cpu-aarch64-linux.c
3	@@ -14,49 +14,35 @@	3	@@ -14,49 +14,47 @@
4		4
5	#include <openssl/cpu.h>	5	#include <openssl/cpu.h>
6		6
Lines 17-28 Link Here
17	-	17	-
18	extern uint32_t OPENSSL_armcap_P;	18	extern uint32_t OPENSSL_armcap_P;
19		19
20	+#include <sys/types.h>	20	-void OPENSSL_cpuid_setup(void) {
		21	- unsigned long hwcap = getauxval(AT_HWCAP);
21	+#include <machine/armreg.h>	22	+#include <machine/armreg.h>
22	+
23	void OPENSSL_cpuid_setup(void) {
24	- unsigned long hwcap = getauxval(AT_HWCAP);
25	+ uint64_t id_aa64isar0;
26		23
27	- // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of	24	- // See /usr/include/asm/hwcap.h on an aarch64 installation for the source of
28	- // these values.	25	- // these values.
Lines 31-37 Link Here
31	- static const unsigned long kPMULL = 1 << 4;	28	- static const unsigned long kPMULL = 1 << 4;
32	- static const unsigned long kSHA1 = 1 << 5;	29	- static const unsigned long kSHA1 = 1 << 5;
33	- static const unsigned long kSHA256 = 1 << 6;	30	- static const unsigned long kSHA256 = 1 << 6;
34	+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);	31	+#ifndef ID_AA64ISAR0_AES_VAL
		32	+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
		33	+#endif
		34	+#ifndef ID_AA64ISAR0_AES_VAL
		35	+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
		36	+#endif
		37	+#ifndef ID_AA64ISAR0_SHA1_VAL
		38	+#define ID_AA64ISAR0_SHA1_VAL ID_AA64ISAR0_SHA1
		39	+#endif
		40	+#ifndef ID_AA64ISAR0_SHA2_VAL
		41	+#define ID_AA64ISAR0_SHA2_VAL ID_AA64ISAR0_SHA2
		42	+#endif
35		43
36	- if ((hwcap & kNEON) == 0) {	44	- if ((hwcap & kNEON) == 0) {
37	- // Matching OpenSSL, if NEON is missing, don't report other features	45	- // Matching OpenSSL, if NEON is missing, don't report other features
Lines 38-60 Link Here
38	- // either.	46	- // either.
39	- return;	47	- return;
40	- }	48	- }
41	-	49	+void OPENSSL_cpuid_setup(void) {
		50	+ uint64_t id_aa64isar0;
		51
		52	+ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
		53	+
42	OPENSSL_armcap_P \|= ARMV7_NEON;	54	OPENSSL_armcap_P \|= ARMV7_NEON;
43		55
44	- if (hwcap & kAES) {	56	- if (hwcap & kAES) {
45	+ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_BASE) {	57	+ if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE) {
46	OPENSSL_armcap_P \|= ARMV8_AES;	58	OPENSSL_armcap_P \|= ARMV8_AES;
47	}	59	}
48	- if (hwcap & kPMULL) {	60	- if (hwcap & kPMULL) {
49	+ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {	61	+ if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) {
50	OPENSSL_armcap_P \|= ARMV8_PMULL;	62	OPENSSL_armcap_P \|= ARMV8_PMULL;
51	}	63	}
52	- if (hwcap & kSHA1) {	64	- if (hwcap & kSHA1) {
53	+ if (ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {	65	+ if (ID_AA64ISAR0_SHA1_VAL(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE) {
54	OPENSSL_armcap_P \|= ARMV8_SHA1;	66	OPENSSL_armcap_P \|= ARMV8_SHA1;
55	}	67	}
56	- if (hwcap & kSHA256) {	68	- if (hwcap & kSHA256) {
57	+ if(ID_AA64ISAR0_SHA2(id_aa64isar0) == ID_AA64ISAR0_SHA2_BASE) {	69	+ if(ID_AA64ISAR0_SHA2_VAL(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE) {
58	OPENSSL_armcap_P \|= ARMV8_SHA256;	70	OPENSSL_armcap_P \|= ARMV8_SHA256;
59	}	71	}
60	}	72	}

Lines 1-20 Link Here

(-)www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_crc32c_src_src_crc32c__arm64__linux__check.h (-7 / +12 lines)
1	--- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig 2019-05-23 12:39:34 UTC	1	--- src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h.orig 2019-10-21 10:14:54 UTC
2	+++ src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h	2	+++ src/3rdparty/chromium/third_party/crc32c/src/src/crc32c_arm64_linux_check.h
3	@@ -16,6 +16,24 @@	3	@@ -16,6 +16,29 @@
4		4
5	#if HAVE_ARM64_CRC32C	5	#if HAVE_ARM64_CRC32C
6		6
7	+#if defined(__FreeBSD__)	7	+#if defined(__FreeBSD__)
8	+#include <machine/armreg.h>	8	+#include <machine/armreg.h>
9	+#include <sys/types.h>	9	+#ifndef ID_AA64ISAR0_AES_VAL
		10	+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
		11	+#endif
		12	+#ifndef ID_AA64ISAR0_CRC32_VAL
		13	+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
		14	+#endif
10	+namespace crc32c {	15	+namespace crc32c {
11	+	16	+
12	+inline bool CanUseArm64Linux() {	17	+inline bool CanUseArm64Linux() {
13	+ uint64_t id_aa64isar0;	18	+ uint64_t id_aa64isar0;
14	+	19	+
15	+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);	20	+ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
16	+ if ((ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \	21	+ if ((ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL) && \
17	+ (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))	22	+ (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE))
18	+ return true;	23	+ return true;
19	+ return false;	24	+ return false;
20	+}	25	+}
Lines 25-31 Link Here
25	#if HAVE_STRONG_GETAUXVAL	30	#if HAVE_STRONG_GETAUXVAL
26	#include <sys/auxv.h>	31	#include <sys/auxv.h>
27	#elif HAVE_WEAK_GETAUXVAL	32	#elif HAVE_WEAK_GETAUXVAL
28	@@ -43,6 +61,7 @@ inline bool CanUseArm64Linux() {	33	@@ -43,6 +66,7 @@ inline bool CanUseArm64Linux() {
29		34
30	} // namespace crc32c	35	} // namespace crc32c
31		36

Lines 1-18 Link Here

(-)www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_skia_src_core_SkCpu.cpp (-9 / +12 lines)
1	--- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp.orig 2019-05-23 12:39:34 UTC	1	--- src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp 2019-10-21 10:14:54 UTC
2	+++ src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp	2	+++ src/3rdparty/chromium/third_party/skia/src/core/SkCpu.cpp
3	@@ -70,6 +70,20 @@	3	@@ -70,6 +70,23 @@
4	return features;	4	return features;
5	}	5	}
6		6
7	+#elif defined(SK_CPU_ARM64) && defined(__FreeBSD__)	7	+#elif defined(SK_CPU_ARM64) && defined(__FreeBSD__)
8	+ #include <machine/armreg.h>	8	+ #include <machine/armreg.h>
		9	+ #ifndef ID_AA64ISAR0_CRC32_VAL
		10	+ #define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
		11	+ #endif
9	+	12	+
10	+ static uint32_t read_cpu_features() {	13	+ static uint32_t read_cpu_features() {
11	+ uint32_t features = 0;	14	+ uint32_t features = 0;
12	+ uint64_t id_aa64isar0;	15	+ uint64_t id_aa64isar0;
13	+	16	+
14	+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);	17	+ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
15	+ if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {	18	+ if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE) {
16	+ features \|= SkCpu::CRC32;	19	+ features \|= SkCpu::CRC32;
17	+ }	20	+ }
18	+ return features;	21	+ return features;
Lines 21-28 Link Here
21	#elif defined(SK_CPU_ARM64) && __has_include(<sys/auxv.h>)	24	#elif defined(SK_CPU_ARM64) && __has_include(<sys/auxv.h>)
22	#include <sys/auxv.h>	25	#include <sys/auxv.h>
23		26
24	@@ -95,7 +109,12 @@	27	@@ -78,7 +95,12 @@
25	const uint32_t kHWCAP_VFPv4 = (1<<16);	28	kHWCAP_ASIMDHP = (1<<10);
26		29
27	uint32_t features = 0;	30	uint32_t features = 0;
28	+#if defined(__FreeBSD__)	31	+#if defined(__FreeBSD__)
Lines 31-36 Link Here
31	+#else	34	+#else
32	uint32_t hwcaps = getauxval(AT_HWCAP);	35	uint32_t hwcaps = getauxval(AT_HWCAP);
33	+#endif	36	+#endif
34	if (hwcaps & kHWCAP_NEON ) {	37	if (hwcaps & kHWCAP_CRC32 ) { features \|= SkCpu::CRC32; }
35	features \|= SkCpu::NEON;	38	if (hwcaps & kHWCAP_ASIMDHP) { features \|= SkCpu::ASIMDHP; }
36	if (hwcaps & kHWCAP_VFPv4) { features \|= SkCpu::NEON_FMA\|SkCpu::VFP_FP16; }	39	return features;

Lines 1-6 Link Here

(-)www/qt5-webengine/files/patch-src_3rdparty_chromium_third__party_zlib_arm__features.c (-10 / +15 lines)
1	--- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig 2019-05-23 12:39:34 UTC	1	--- src/3rdparty/chromium/third_party/zlib/arm_features.c.orig 2019-10-21 10:14:54 UTC
2	+++ src/3rdparty/chromium/third_party/zlib/arm_features.c	2	+++ src/3rdparty/chromium/third_party/zlib/arm_features.c
3	@@ -8,83 +8,30 @@	3	@@ -8,83 +8,36 @@
4		4
5	#include "zutil.h"	5	#include "zutil.h"
6		6
Lines 29-37 Link Here
29	static void init_arm_features(void)	29	static void init_arm_features(void)
30	{	30	{
31	- uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0;	31	- uint64_t flag_crc32 = 0, flag_pmull = 0, capabilities = 0;
32	+#if defined (__aarch64__)	32	-
33	+ uint64_t id_aa64isar0;
34
35	-#if defined(ARMV8_OS_ANDROID)	33	-#if defined(ARMV8_OS_ANDROID)
36	- flag_crc32 = ANDROID_CPU_ARM_FEATURE_CRC32;	34	- flag_crc32 = ANDROID_CPU_ARM_FEATURE_CRC32;
37	- flag_pmull = ANDROID_CPU_ARM_FEATURE_PMULL;	35	- flag_pmull = ANDROID_CPU_ARM_FEATURE_PMULL;
Lines 49-64 Link Here
49	- flag_pmull = HWCAP2_PMULL;	47	- flag_pmull = HWCAP2_PMULL;
50	- capabilities = getauxval(AT_HWCAP2);	48	- capabilities = getauxval(AT_HWCAP2);
51	- #endif	49	- #endif
52	-#endif	50	+#if defined (__aarch64__)
53	-	51	+#ifndef ID_AA64ISAR0_AES_VAL
		52	+#define ID_AA64ISAR0_AES_VAL ID_AA64ISAR0_AES
		53	#endif
		54	+#ifndef ID_AA64ISAR0_CRC32_VAL
		55	+#define ID_AA64ISAR0_CRC32_VAL ID_AA64ISAR0_CRC32
		56	+#endif
		57	+ uint64_t id_aa64isar0;
		58
54	- if (capabilities & flag_crc32)	59	- if (capabilities & flag_crc32)
55	- arm_cpu_enable_crc32 = 1;	60	- arm_cpu_enable_crc32 = 1;
56	-	61	-
57	- if (capabilities & flag_pmull)	62	- if (capabilities & flag_pmull)
58	+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);	63	+ id_aa64isar0 = READ_SPECIALREG(id_aa64isar0_el1);
59	+ if (ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)	64	+ if (ID_AA64ISAR0_AES_VAL(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL)
60	arm_cpu_enable_pmull = 1;	65	arm_cpu_enable_pmull = 1;
61	+ if (ID_AA64ISAR0_CRC32(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)	66	+ if (ID_AA64ISAR0_CRC32_VAL(id_aa64isar0) == ID_AA64ISAR0_CRC32_BASE)
62	+ arm_cpu_enable_crc32 = 1;	67	+ arm_cpu_enable_crc32 = 1;
63	+#endif	68	+#endif
64	}	69	}