Attachment #235345 for bug #139743




static int		pci_msix_blacklisted(void);
static void		pci_resume_msi(device_t dev);
static void		pci_resume_msix(device_t dev);
static void		pci_fix_asus_smbus(device_t dev);
static int		pci_remap_intr_method(device_t bus, device_t dev,
			    u_int irq);
static void		pci_hint_device_unit(device_t acdev, device_t child,

#define	PCI_QUIRK_REALLOC_BAR	7 /* Can't allocate memory at the default address */
	int	arg1;
	int	arg2;
	void (*fixup_func)(device_t dev);
};

static const struct pci_quirk pci_quirks[] = {
	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
	{ 0x71138086, PCI_QUIRK_MAP_REG,	0x90,	 0,	NULL },
	{ 0x719b8086, PCI_QUIRK_MAP_REG,	0x90,	 0,	NULL },
	/* As does the Serverworks OSB4 (the SMBus mapping register) */
	{ 0x02001166, PCI_QUIRK_MAP_REG,	0x90,	 0,	NULL },

	/*
	 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
	 * or the CMIC-SL (AKA ServerWorks GC_LE).
	 */
	{ 0x00141166, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x00171166, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },

	/*
	 * MSI doesn't work on earlier Intel chipsets including
	 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
	 */
	{ 0x25408086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x25508086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x25608086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x25708086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x25788086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },
	{ 0x35808086, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },

	/*
	 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
	 * bridge.
	 */
	{ 0x74501022, PCI_QUIRK_DISABLE_MSI,	0,	0,	NULL },

	/*
	 * Some virtualization environments emulate an older chipset
	 * but support MSI just fine.  QEMU uses the Intel 82440.
	 */
	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM,	0,	0,	NULL },

	/*
	 * HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus

	 * For SB600 A21 and later, firmware must set the bit to hide it.
	 * For SB700 and later, it is unused and hardcoded to zero.
	 */
	{ 0x43851002, PCI_QUIRK_UNMAP_REG,	0x14,	0,	NULL },

	/*
	 * Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
	 * a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
	 * of the command register is set.
	 */
	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL },
	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL },
	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL },
	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL },
	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL },

	/*
	 * Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
	 * issue MSI interrupts with PCIM_CMD_INTxDIS set either.
	 */
	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL }, /* BCM5714 */
	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL }, /* BCM5714S */
	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL }, /* BCM5780 */
	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL }, /* BCM5780S */
	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL }, /* BCM5715 */
	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG,	0,	0,	NULL }, /* BCM5715S */

	/*
	 * HPE Gen 10 VGA has a memory range that can't be allocated in the
	 * expected place.
	 */
	{ 0x98741002, PCI_QUIRK_REALLOC_BAR,	0, 	0,	NULL },

	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
	{ 0x24408086, PCI_QUIRK_UNMAP_REG,	0,	0,	&pci_fix_asus_smbus }, /* Intel 82801AB (ICH2) */
	{ 0x24C08086, PCI_QUIRK_UNMAP_REG,	0,	0,	&pci_fix_asus_smbus }, /* Intel 82801DB/DBL (ICH4/ICH4-L) */
	{ 0 }
};


		cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
}

/* asus p4b/p4pe hack */
static void
pci_fix_asus_smbus(device_t dev)
{
	int	pmccfg;
        
	/* read subsystem vendor-id */
	pmccfg = pci_read_config(dev, 0xF2, 2);
	printf(" [-] pmccfg: %.4x\n",pmccfg);
	if( pmccfg & 0x8 ){
	    pmccfg &= ~0x8;
	    pci_write_config(dev, 0xF2, pmccfg, 2);
	    pmccfg = pci_read_config(dev, 0xF2, 2);
	    if( pmccfg & 0x8 )
		printf("Could not enable Intel 801SMBus!\n");
	    else
		printf("Enabled Intel 801SMBus\n");
	}
}

/* extract header type specific config data */

static void

	 * Add additional, quirked resources.
	 */
	for (q = &pci_quirks[0]; q->devid != 0; q++)

		if (q->devid == ((cfg->device << 16) | cfg->vendor) ){
		    if( q->type == PCI_QUIRK_MAP_REG )
			pci_add_map(bus, dev, q->arg1, rl, force, 0);
		    else if( q->type == PCI_QUIRK_UNMAP_REG )
			q->fixup_func(dev);
		}

	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
#ifdef __PCI_REROUTE_INTERRUPT

Return to bug 139743

Lines 126-131 static int pci_msi_blacklisted(void); Link Here

(-)sys/dev/pci/pci.c (-28 / +59 lines)
126	static int pci_msix_blacklisted(void);	126	static int pci_msix_blacklisted(void);
127	static void pci_resume_msi(device_t dev);	127	static void pci_resume_msi(device_t dev);
128	static void pci_resume_msix(device_t dev);	128	static void pci_resume_msix(device_t dev);
		129	static void pci_fix_asus_smbus(device_t dev);
129	static int pci_remap_intr_method(device_t bus, device_t dev,	130	static int pci_remap_intr_method(device_t bus, device_t dev,
130	u_int irq);	131	u_int irq);
131	static void pci_hint_device_unit(device_t acdev, device_t child,	132	static void pci_hint_device_unit(device_t acdev, device_t child,
Lines 245-289 struct pci_quirk { Link Here
245	#define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */	246	#define PCI_QUIRK_REALLOC_BAR 7 /* Can't allocate memory at the default address */
246	int arg1;	247	int arg1;
247	int arg2;	248	int arg2;
		249	void (*fixup_func)(device_t dev);
248	};	250	};
249		251
250	static const struct pci_quirk pci_quirks[] = {	252	static const struct pci_quirk pci_quirks[] = {
251	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */	253	/* The Intel 82371AB and 82443MX have a map register at offset 0x90. */
252	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },	254	{ 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
253	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },	255	{ 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
254	/* As does the Serverworks OSB4 (the SMBus mapping register) */	256	/* As does the Serverworks OSB4 (the SMBus mapping register) */
255	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },	257	{ 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0, NULL },
256		258
257	/*	259	/*
258	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge	260	* MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
259	* or the CMIC-SL (AKA ServerWorks GC_LE).	261	* or the CMIC-SL (AKA ServerWorks GC_LE).
260	*/	262	*/
261	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	263	{ 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
262	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },	264	{ 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
263		265
264	/*	266	/*
265	* MSI doesn't work on earlier Intel chipsets including	267	* MSI doesn't work on earlier Intel chipsets including
266	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.	268	* E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
267	*/	269	*/
268	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	270	{ 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
269	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	271	{ 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
270	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	272	{ 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
271	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	273	{ 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
272	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	274	{ 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
273	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	275	{ 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
274	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },	276	{ 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
275		277
276	/*	278	/*
277	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX	279	* MSI doesn't work with devices behind the AMD 8131 HT-PCIX
278	* bridge.	280	* bridge.
279	*/	281	*/
280	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },	282	{ 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0, NULL },
281		283
282	/*	284	/*
283	* Some virtualization environments emulate an older chipset	285	* Some virtualization environments emulate an older chipset
284	* but support MSI just fine. QEMU uses the Intel 82440.	286	* but support MSI just fine. QEMU uses the Intel 82440.
285	*/	287	*/
286	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0 },	288	{ 0x12378086, PCI_QUIRK_ENABLE_MSI_VM, 0, 0, NULL },
287		289
288	/*	290	/*
289	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus	291	* HPET MMIO base address may appear in Bar1 for AMD SB600 SMBus
Lines 293-327 static const struct pci_quirk pci_quirks[] = { Link Here
293	* For SB600 A21 and later, firmware must set the bit to hide it.	295	* For SB600 A21 and later, firmware must set the bit to hide it.
294	* For SB700 and later, it is unused and hardcoded to zero.	296	* For SB700 and later, it is unused and hardcoded to zero.
295	*/	297	*/
296	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0 },	298	{ 0x43851002, PCI_QUIRK_UNMAP_REG, 0x14, 0, NULL },
297		299
298	/*	300	/*
299	* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have	301	* Atheros AR8161/AR8162/E2200/E2400/E2500 Ethernet controllers have
300	* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit	302	* a bug that MSI interrupt does not assert if PCIM_CMD_INTxDIS bit
301	* of the command register is set.	303	* of the command register is set.
302	*/	304	*/
303	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	305	{ 0x10911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
304	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	306	{ 0xE0911969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
305	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	307	{ 0xE0A11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
306	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	308	{ 0xE0B11969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
307	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0 },	309	{ 0x10901969, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL },
308		310
309	/*	311	/*
310	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't	312	* Broadcom BCM5714(S)/BCM5715(S)/BCM5780(S) Ethernet MACs don't
311	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.	313	* issue MSI interrupts with PCIM_CMD_INTxDIS set either.
312	*/	314	*/
313	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714 */	315	{ 0x166814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714 */
314	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5714S */	316	{ 0x166914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5714S */
315	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780 */	317	{ 0x166a14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780 */
316	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5780S */	318	{ 0x166b14e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5780S */
317	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715 */	319	{ 0x167814e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715 */
318	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0 }, /* BCM5715S */	320	{ 0x167914e4, PCI_QUIRK_MSI_INTX_BUG, 0, 0, NULL }, /* BCM5715S */
319		321
320	/*	322	/*
321	* HPE Gen 10 VGA has a memory range that can't be allocated in the	323	* HPE Gen 10 VGA has a memory range that can't be allocated in the
322	* expected place.	324	* expected place.
323	*/	325	*/
324	{ 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0 },	326	{ 0x98741002, PCI_QUIRK_REALLOC_BAR, 0, 0, NULL },
		327
		328	/* The ASUS P4B-motherboards needs a hack to enable the Intel 801SMBus */
		329	{ 0x24408086, PCI_QUIRK_UNMAP_REG, 0, 0, &pci_fix_asus_smbus }, /* Intel 82801AB (ICH2) */
		330	{ 0x24C08086, PCI_QUIRK_UNMAP_REG, 0, 0, &pci_fix_asus_smbus }, /* Intel 82801DB/DBL (ICH4/ICH4-L) */
325	{ 0 }	331	{ 0 }
326	};	332	};
327		333
Lines 638-643 pci_fixancient(pcicfgregs *cfg) Link Here
638	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;	644	cfg->hdrtype = PCIM_HDRTYPE_BRIDGE;
639	}	645	}
640		646
		647	/* asus p4b/p4pe hack */
		648	static void
		649	pci_fix_asus_smbus(device_t dev)
		650	{
		651	int pmccfg;
		652
		653	/* read subsystem vendor-id */
		654	pmccfg = pci_read_config(dev, 0xF2, 2);
		655	printf(" [-] pmccfg: %.4x\n",pmccfg);
		656	if( pmccfg & 0x8 ){
		657	pmccfg &= ~0x8;
		658	pci_write_config(dev, 0xF2, pmccfg, 2);
		659	pmccfg = pci_read_config(dev, 0xF2, 2);
		660	if( pmccfg & 0x8 )
		661	printf("Could not enable Intel 801SMBus!\n");
		662	else
		663	printf("Enabled Intel 801SMBus\n");
		664	}
		665	}
		666
641	/* extract header type specific config data */	667	/* extract header type specific config data */
642		668
643	static void	669	static void
Lines 4088-4095 pci_add_resources(device_t bus, device_t dev, int forc Link Here
4088	* Add additional, quirked resources.	4114	* Add additional, quirked resources.
4089	*/	4115	*/
4090	for (q = &pci_quirks[0]; q->devid != 0; q++)	4116	for (q = &pci_quirks[0]; q->devid != 0; q++)
4091	if (q->devid == devid && q->type == PCI_QUIRK_MAP_REG)	4117
		4118	if (q->devid == ((cfg->device << 16) \| cfg->vendor) ){
		4119	if( q->type == PCI_QUIRK_MAP_REG )
4092	pci_add_map(bus, dev, q->arg1, rl, force, 0);	4120	pci_add_map(bus, dev, q->arg1, rl, force, 0);
		4121	else if( q->type == PCI_QUIRK_UNMAP_REG )
		4122	q->fixup_func(dev);
		4123	}
4093		4124
4094	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {	4125	if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
4095	#ifdef __PCI_REROUTE_INTERRUPT	4126	#ifdef __PCI_REROUTE_INTERRUPT