Attachment #241908 for bug #271062




.\"
.\" $FreeBSD$
.\"
.Dd April 25, 2023
.Dt ISP 4
.Os
.Sh NAME

Optical 16Gb Fibre Channel PCIe cards.
.It Qlogic 2740/2742/2764 (aka 2722/2714)
Optical 32Gb Fibre Channel PCIe cards.
.It Qlogic QLE2770/QLE2772 (aka 2812)
Optical 32Gb Fibre Channel PCIe cards.
.It Qlogic QLE2774 (aka 2814)
Optical 32Gb Fibre Channel PCIe cards.
.It Qlogic QLE2870/QLE2872 (aka 2812)
Optical 64Gb Fibre Channel PCIe cards.
.It Qlogic QLE2874 (aka 2814)
Optical 64Gb Fibre Channel PCIe cards.
.El
.Sh CONFIGURATION OPTIONS
Target mode support for Fibre Channel adapters may be enabled with the

Lines 22-28 Link Here

(-)b/share/man/man4/ispfw.4 (-1 / +3 lines)
22	.\"	22	.\"
23	.\" $FreeBSD$	23	.\" $FreeBSD$
24	.\"	24	.\"
25	.Dd November 19, 2020	25	.Dd April 25, 2023
26	.Dt ISPFW 4	26	.Dt ISPFW 4
27	.Os	27	.Os
28	.Sh NAME	28	.Sh NAME
Lines 60-62 This driver was written by Link Here
60	.An Matthew Jacob .	60	.An Matthew Jacob .
61	Later improvement was done by	61	Later improvement was done by
62	.An Alexander Motin Aq Mt mav@FreeBSD.org .	62	.An Alexander Motin Aq Mt mav@FreeBSD.org .
		63	.Sh BUGS
		64	Only firmware for the 24xx and 25xx based cards is included.

Lines 123-128 static int isp_read_nvram_2400(ispsoftc_t *); Link Here

(-)b/sys/dev/isp/isp.c (-3 / +310 lines)
123	static void isp_rd_2400_nvram(ispsoftc_t , uint32_t, uint32_t );	123	static void isp_rd_2400_nvram(ispsoftc_t , uint32_t, uint32_t );
124	static void isp_parse_nvram_2400(ispsoftc_t , uint8_t );	124	static void isp_parse_nvram_2400(ispsoftc_t , uint8_t );
125		125
		126	static int isp_read_flthdr_28xx(ispsoftc_t *);
		127	static void isp_rd_28xx_flthdr(ispsoftc_t , uint32_t, uint32_t );
		128	static void isp_parse_flthdr_28xx(ispsoftc_t , uint8_t );
		129
		130	static int isp_read_flt_28xx(ispsoftc_t *);
		131	static void isp_rd_28xx_flt(ispsoftc_t , uint32_t, uint32_t );
		132	static int isp_parse_flt_28xx(ispsoftc_t , uint8_t );
		133
126	static void	134	static void
127	isp_change_fw_state(ispsoftc_t *isp, int chan, int state)	135	isp_change_fw_state(ispsoftc_t *isp, int chan, int state)
128	{	136	{
Lines 179-184 isp_reset(ispsoftc_t *isp, int do_load_defaults) Link Here
179	case ISP_HA_FC_2700:	187	case ISP_HA_FC_2700:
180	btype = "2700";	188	btype = "2700";
181	break;	189	break;
		190	case ISP_HA_FC_2800:
		191	btype = "2800";
		192	break;
182	default:	193	default:
183	break;	194	break;
184	}	195	}
Lines 710-717 isp_init(ispsoftc_t *isp) Link Here
710	icbp->icb_version = ICB_VERSION1;	721	icbp->icb_version = ICB_VERSION1;
711	icbp->icb_maxfrmlen = DEFAULT_FRAMESIZE(isp);	722	icbp->icb_maxfrmlen = DEFAULT_FRAMESIZE(isp);
712	if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN \|\| icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) {	723	if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN \|\| icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) {
713	isp_prt(isp, ISP_LOGERR, "bad frame length (%d) from NVRAM- using %d", DEFAULT_FRAMESIZE(isp), ICB_DFLT_FRMLEN);
714	icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN;	724	icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN;
		725	if (IS_28XX(isp))
		726	icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN_28XX;
		727
		728	isp_prt(isp, ISP_LOGERR, "bad frame length (%d) from NVRAM - using %d", DEFAULT_FRAMESIZE(isp), icbp->icb_maxfrmlen);
715	}	729	}
716		730
717	if (!IS_26XX(isp))	731	if (!IS_26XX(isp))
Lines 822-833 isp_init(ispsoftc_t *isp) Link Here
822	} else if (isp->isp_confopts & ISP_CFG_32GB) {	836	} else if (isp->isp_confopts & ISP_CFG_32GB) {
823	icbp->icb_fwoptions3 &= ~ICB2400_OPT3_RATE_MASK;	837	icbp->icb_fwoptions3 &= ~ICB2400_OPT3_RATE_MASK;
824	icbp->icb_fwoptions3 \|= ICB2400_OPT3_RATE_32GB;	838	icbp->icb_fwoptions3 \|= ICB2400_OPT3_RATE_32GB;
		839	} else if (isp->isp_confopts & ISP_CFG_64GB) {
		840	icbp->icb_fwoptions3 &= ~ICB2400_OPT3_RATE_MASK;
		841	icbp->icb_fwoptions3 \|= ICB2400_OPT3_RATE_64GB;
825	} else {	842	} else {
826	switch (icbp->icb_fwoptions3 & ICB2400_OPT3_RATE_MASK) {	843	switch (icbp->icb_fwoptions3 & ICB2400_OPT3_RATE_MASK) {
827	case ICB2400_OPT3_RATE_4GB:	844	case ICB2400_OPT3_RATE_4GB:
828	case ICB2400_OPT3_RATE_8GB:	845	case ICB2400_OPT3_RATE_8GB:
829	case ICB2400_OPT3_RATE_16GB:	846	case ICB2400_OPT3_RATE_16GB:
830	case ICB2400_OPT3_RATE_32GB:	847	case ICB2400_OPT3_RATE_32GB:
		848	case ICB2400_OPT3_RATE_64GB:
831	case ICB2400_OPT3_RATE_AUTO:	849	case ICB2400_OPT3_RATE_AUTO:
832	break;	850	break;
833	case ICB2400_OPT3_RATE_2GB:	851	case ICB2400_OPT3_RATE_2GB:
Lines 1537-1542 isp_fclink_test(ispsoftc_t *isp, int chan, int usdelay) Link Here
1537	if (mbs.param[0] == MBOX_COMMAND_COMPLETE) {	1555	if (mbs.param[0] == MBOX_COMMAND_COMPLETE) {
1538	if (mbs.param[1] == MBGSD_10GB)	1556	if (mbs.param[1] == MBGSD_10GB)
1539	fcp->isp_gbspeed = 10;	1557	fcp->isp_gbspeed = 10;
		1558	else if (mbs.param[1] == MBGSD_64GB)
		1559	fcp->isp_gbspeed = 64;
1540	else if (mbs.param[1] == MBGSD_32GB)	1560	else if (mbs.param[1] == MBGSD_32GB)
1541	fcp->isp_gbspeed = 32;	1561	fcp->isp_gbspeed = 32;
1542	else if (mbs.param[1] == MBGSD_16GB)	1562	else if (mbs.param[1] == MBGSD_16GB)
Lines 4322-4339 isp_reinit(ispsoftc_t *isp, int do_load_defaults) Link Here
4322	static int	4342	static int
4323	isp_read_nvram(ispsoftc_t *isp, int bus)	4343	isp_read_nvram(ispsoftc_t *isp, int bus)
4324	{	4344	{
		4345	if (IS_28XX(isp)) {
		4346	fcparam *fcp = FCPARAM(isp, 0);
		4347	int r = 0;
4325		4348
		4349	fcp->flash_data_addr = ISP28XX_BASE_ADDR;
		4350	fcp->flt_length = 0;
		4351	r = isp_read_flthdr_28xx(isp);
		4352	if (r == 0) {
		4353	isp_read_flt_28xx(isp);
		4354	} else {
		4355	fcp->flt_region_nvram =
		4356	(0x300000 + ISP2400_NVRAM_PORT_ADDR(isp->isp_port));
		4357	}
		4358	}
4326	return (isp_read_nvram_2400(isp));	4359	return (isp_read_nvram_2400(isp));
4327	}	4360	}
4328		4361
4329	static int	4362	static int
4330	isp_read_nvram_2400(ispsoftc_t *isp)	4363	isp_read_nvram_2400(ispsoftc_t *isp)
4331	{	4364	{
		4365	fcparam *fcp = FCPARAM(isp, 0);
4332	int retval = 0;	4366	int retval = 0;
4333	uint32_t addr, csum, lwrds, *dptr;	4367	uint32_t addr, csum, lwrds, *dptr;
4334	uint8_t nvram_data[ISP2400_NVRAM_SIZE];	4368	uint8_t nvram_data[ISP2400_NVRAM_SIZE];
4335		4369
4336	addr = ISP2400_NVRAM_PORT_ADDR(isp->isp_port);	4370	if (IS_28XX(isp)) {
		4371	addr = fcp->flt_region_nvram;
		4372	} else {
		4373	addr = ISP2400_NVRAM_PORT_ADDR(isp->isp_port);
		4374	}
4337	dptr = (uint32_t *) nvram_data;	4375	dptr = (uint32_t *) nvram_data;
4338	for (lwrds = 0; lwrds < ISP2400_NVRAM_SIZE >> 2; lwrds++) {	4376	for (lwrds = 0; lwrds < ISP2400_NVRAM_SIZE >> 2; lwrds++) {
4339	isp_rd_2400_nvram(isp, addr++, dptr++);	4377	isp_rd_2400_nvram(isp, addr++, dptr++);
Lines 4368-4374 isp_rd_2400_nvram(ispsoftc_t isp, uint32_t addr, uint32_t rp) Link Here
4368	uint32_t base = 0x7ffe0000;	4406	uint32_t base = 0x7ffe0000;
4369	uint32_t tmp = 0;	4407	uint32_t tmp = 0;
4370		4408
4371	if (IS_26XX(isp)) {	4409	if (IS_28XX(isp)) {
		4410	// base = 0x7fad0000; /* 0x7f7d0000 + 0x300000 */
		4411	fcparam *fcp = FCPARAM(isp, 0);
		4412	base = fcp->flash_data_addr + addr;
		4413	addr = 0;
		4414	} else if (IS_26XX(isp)) {
4372	base = 0x7fe7c000; /* XXX: Observation, may be wrong. */	4415	base = 0x7fe7c000; /* XXX: Observation, may be wrong. */
4373	} else if (IS_25XX(isp)) {	4416	} else if (IS_25XX(isp)) {
4374	base = 0x7ff00000 \| 0x48000;	4417	base = 0x7ff00000 \| 0x48000;
Lines 4435-4437 isp_parse_nvram_2400(ispsoftc_t isp, uint8_t nvram_data) Link Here
4435	fcp->isp_xfwoptions = ISP2400_NVRAM_FIRMWARE_OPTIONS2(nvram_data);	4478	fcp->isp_xfwoptions = ISP2400_NVRAM_FIRMWARE_OPTIONS2(nvram_data);
4436	fcp->isp_zfwoptions = ISP2400_NVRAM_FIRMWARE_OPTIONS3(nvram_data);	4479	fcp->isp_zfwoptions = ISP2400_NVRAM_FIRMWARE_OPTIONS3(nvram_data);
4437	}	4480	}
		4481
		4482	static int
		4483	isp_read_flthdr_28xx(ispsoftc_t *isp)
		4484	{
		4485	int retval = 0;
		4486	uint32_t addr, lwrds, *dptr;
		4487	uint16_t csum;
		4488	uint8_t flthdr_data[FLT_HEADER_SIZE];
		4489
		4490	addr = ISP28XX_FLT_ADDR;
		4491	dptr = (uint32_t *) flthdr_data;
		4492
		4493	isp_prt(isp, ISP_LOGDEBUG0,
		4494	"FLTL[DEF]: 0x%x", ISP28XX_FLT_ADDR);
		4495	for (lwrds = 0; lwrds < FLT_HEADER_SIZE >> 2; lwrds++) {
		4496	isp_rd_28xx_flthdr(isp, addr++, dptr++);
		4497	}
		4498	dptr = (uint32_t *) flthdr_data;
		4499	for (csum = 0, lwrds = 0; lwrds < FLT_HEADER_SIZE >> 4; lwrds++) {
		4500	uint16_t tmp;
		4501	ISP_IOXGET_16(isp, &dptr[lwrds], tmp);
		4502	csum += tmp;
		4503	}
		4504	if (csum != 0) {
		4505	retval = -1;
		4506	goto out;
		4507	}
		4508	isp_parse_flthdr_28xx(isp, flthdr_data);
		4509	out:
		4510	return (retval);
		4511	}
		4512
		4513	static void
		4514	isp_rd_28xx_flthdr(ispsoftc_t isp, uint32_t addr, uint32_t rp)
		4515	{
		4516	fcparam *fcp = FCPARAM(isp, 0);
		4517	int loops = 0;
		4518	uint32_t base = fcp->flash_data_addr;
		4519	uint32_t tmp = 0;
		4520
		4521	ISP_WRITE(isp, BIU2400_FLASH_ADDR, base \| addr);
		4522	for (loops = 0; loops < 5000; loops++) {
		4523	ISP_DELAY(10);
		4524	tmp = ISP_READ(isp, BIU2400_FLASH_ADDR);
		4525	if ((tmp & (1U << 31)) != 0) {
		4526	break;
		4527	}
		4528	}
		4529	if (tmp & (1U << 31)) {
		4530	*rp = ISP_READ(isp, BIU2400_FLASH_DATA);
		4531	ISP_SWIZZLE_NVRAM_LONG(isp, rp);
		4532	} else {
		4533	*rp = 0xffffffff;
		4534	}
		4535	}
		4536
		4537	static void
		4538	isp_parse_flthdr_28xx(ispsoftc_t isp, uint8_t flthdr_data)
		4539	{
		4540	fcparam *fcp = FCPARAM(isp, 0);
		4541	uint16_t ver, csum;
		4542
		4543	ver = le16toh((uint16_t) (ISP28XX_FLT_VERSION(flthdr_data)));
		4544	fcp->flt_length = le16toh((uint16_t) (ISP28XX_FLT_LENGTH(flthdr_data)));
4545	csum = le16toh((uint16_t) (ISP28XX_FLT_CSUM(flthdr_data)));
4546
4547	if ((fcp->flt_length == 0 ) \|\|
4548	(fcp->flt_length > (FLT_HEADER_SIZE + FLT_REGIONS_SIZE))) {
4549	isp_prt(isp, ISP_LOGWARN,
4550	"FLT[DEF]: Invalid length=0x%x(%d)",
4551	fcp->flt_length, fcp->flt_length);
4552	}
4553	isp_prt(isp, ISP_LOGDEBUG0,
4554	"FLT[DEF]: version=0x%x length=0x%x(%d) checksum=0x%x",
4555	ver, fcp->flt_length, fcp->flt_length, csum);
4556	}
4557
4558	static int
4559	isp_read_flt_28xx(ispsoftc_t *isp)
4560	{
4561	fcparam *fcp = FCPARAM(isp, 0);
4562	int retval = 0;
4563	int len = fcp->flt_length - FLT_HEADER_SIZE;
4564	uint32_t addr, lwrds, *dptr;
4565	uint8_t flt_data[len];
4566	fcp->flt_region_entries = len / FLT_REGION_SIZE;
4567
4568	addr = ISP28XX_FLT_ADDR + (FLT_HEADER_SIZE >> 2);
4569	dptr = (uint32_t *) flt_data;
4570	isp_prt(isp, ISP_LOGDEBUG0, "FLT[DEF]: regions=%d",
4571	fcp->flt_region_entries);
4572	for (lwrds = 0; lwrds < len >> 2; lwrds++) {
4573	isp_rd_28xx_flt(isp, addr++, dptr++);
4574	}
4575	retval = isp_parse_flt_28xx(isp, flt_data);
4576	return (retval);
4577	}
4578
4579	static void
4580	isp_rd_28xx_flt(ispsoftc_t isp, uint32_t addr, uint32_t rp)
4581	{
4582	fcparam *fcp = FCPARAM(isp, 0);
4583	int loops = 0;
4584	uint32_t base = fcp->flash_data_addr;
4585	uint32_t tmp = 0;
4586
4587	ISP_WRITE(isp, BIU2400_FLASH_ADDR, base \| addr);
4588	for (loops = 0; loops < 5000; loops++) {
4589	ISP_DELAY(10);
4590	tmp = ISP_READ(isp, BIU2400_FLASH_ADDR);
4591	if ((tmp & (1U << 31)) != 0) {
4592	break;
4593	}
4594	}
4595	if (tmp & (1U << 31)) {
4596	*rp = ISP_READ(isp, BIU2400_FLASH_DATA);
4597	ISP_SWIZZLE_NVRAM_LONG(isp, rp);
4598	} else {
4599	*rp = 0xffffffff;
4600	}
4601	}
4602
4603	static int
4604	isp_parse_flt_28xx(ispsoftc_t isp, uint8_t flt_data)
4605	{
4606	fcparam *fcp = FCPARAM(isp, 0);
4607	int count;
4608	struct flt_region region[fcp->flt_region_entries];
4609
4610	for (count = 0; count < fcp->flt_region_entries; count++) {
4611	region[count].code =
4612	le16toh((uint16_t) (ISP28XX_FLT_REG_CODE(flt_data, count)));
4613	region[count].attribute =
4614	(uint8_t) (ISP28XX_FLT_REG_ATTR(flt_data, count));
4615	region[count].reserved =
4616	(uint8_t) (ISP28XX_FLT_REG_RES(flt_data, count));
4617	region[count].size =
4618	le32toh((uint32_t) (ISP28XX_FLT_REG_SIZE(flt_data, count)) >> 2);
4619	region[count].start =
4620	le32toh((uint32_t) (ISP28XX_FLT_REG_START(flt_data, count)) >> 2);
4621	region[count].end =
4622	le32toh((uint32_t) (ISP28XX_FLT_REG_END(flt_data, count)) >> 2);
4623
4624	isp_prt(isp, ISP_LOGDEBUG0,
4625	"FLT[0x%x]: start=0x%x end=0x%x size=0x%x attribute=0x%x",
4626	region[count].code, region[count].start, region[count].end,
4627	region[count].size, region[count].attribute);
4628
4629	switch(region[count].code) {
4630	case FLT_REG_FW:
4631	fcp->flt_region_fw = region[count].start;
4632	break;
4633	case FLT_REG_BOOT_CODE:
4634	fcp->flt_region_boot = region[count].start;
4635	break;
4636	case FLT_REG_VPD_0:
4637	fcp->flt_region_vpd_nvram = region[count].start;
4638	if (isp->isp_port == 0)
4639	fcp->flt_region_vpd = region[count].start;
4640	break;
4641	case FLT_REG_VPD_1:
4642	if (isp->isp_port == 1)
4643	fcp->flt_region_vpd = region[count].start;
4644	break;
4645	case FLT_REG_VPD_2:
4646	if (isp->isp_port == 2)
4647	fcp->flt_region_vpd = region[count].start;
4648	break;
4649	case FLT_REG_VPD_3:
4650	if (isp->isp_port == 3)
4651	fcp->flt_region_vpd = region[count].start;
4652	break;
4653	case FLT_REG_NVRAM_0:
4654	if (isp->isp_port == 0)
4655	fcp->flt_region_nvram = region[count].start;
4656	break;
4657	case FLT_REG_NVRAM_1:
4658	if (isp->isp_port == 1)
4659	fcp->flt_region_nvram = region[count].start;
4660	break;
4661	case FLT_REG_NVRAM_2:
4662	if (isp->isp_port == 2)
4663	fcp->flt_region_nvram = region[count].start;
4664	break;
4665	case FLT_REG_NVRAM_3:
4666	if (isp->isp_port == 3)
4667	fcp->flt_region_nvram = region[count].start;
4668	break;
4669	case FLT_REG_FDT:
4670	fcp->flt_region_fdt = region[count].start;
4671	break;
4672	case FLT_REG_FLT:
4673	fcp->flt_region_flt = region[count].start;
4674	break;
4675	case FLT_REG_NPIV_CONF_0:
4676	if (isp->isp_port == 0)
4677	fcp->flt_region_npiv_conf = region[count].start;
4678	break;
4679	case FLT_REG_NPIV_CONF_1:
4680	if (isp->isp_port == 1)
4681	fcp->flt_region_npiv_conf = region[count].start;
4682	break;
4683	case FLT_REG_GOLD_FW:
4684	fcp->flt_region_gold_fw = region[count].start;
4685	break;
4686	case FLT_REG_FCP_PRIO_0:
4687	if (isp->isp_port == 0)
4688	fcp->flt_region_fcp_prio = region[count].start;
4689	break;
4690	case FLT_REG_FCP_PRIO_1:
4691	if (isp->isp_port == 1)
4692	fcp->flt_region_fcp_prio = region[count].start;
4693	break;
4694	case FLT_REG_AUX_IMG_PRI_28XX:
4695	fcp->flt_region_aux_img_status_pri = region[count].start;
4696	break;
4697	case FLT_REG_AUX_IMG_SEC_28XX:
4698	fcp->flt_region_aux_img_status_sec = region[count].start;
4699	break;
4700	case FLT_REG_NVRAM_SEC_28XX_0:
4701	if (isp->isp_port == 0)
4702	fcp->flt_region_nvram_sec = region[count].start;
4703	break;
4704	case FLT_REG_NVRAM_SEC_28XX_1:
4705	if (isp->isp_port == 1)
4706	fcp->flt_region_nvram_sec = region[count].start;
4707	break;
4708	case FLT_REG_NVRAM_SEC_28XX_2:
4709	if (isp->isp_port == 2)
4710	fcp->flt_region_nvram_sec = region[count].start;
4711	break;
4712	case FLT_REG_NVRAM_SEC_28XX_3:
4713	if (isp->isp_port == 3)
4714	fcp->flt_region_nvram_sec = region[count].start;
4715	break;
4716	case FLT_REG_VPD_SEC_28XX_0:
4717	fcp->flt_region_vpd_nvram_sec = region[count].start;
4718	if (isp->isp_port == 0)
4719	fcp->flt_region_vpd_sec = region[count].start;
4720	break;
4721	case FLT_REG_VPD_SEC_28XX_1:
4722	if (isp->isp_port == 1)
4723	fcp->flt_region_vpd_sec = region[count].start;
4724	break;
4725	case FLT_REG_VPD_SEC_28XX_2:
4726	if (isp->isp_port == 2)
4727	fcp->flt_region_vpd_sec = region[count].start;
4728	break;
4729	case FLT_REG_VPD_SEC_28XX_3:
4730	if (isp->isp_port == 3)
4731	fcp->flt_region_vpd_sec = region[count].start;
4732	break;
4733	}
4734	}
4735	isp_prt(isp, ISP_LOGDEBUG0,
4736	"FLT[FLT]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram 0x%x "
4737	"fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x",
4738	fcp->flt_region_boot, fcp->flt_region_fw, fcp->flt_region_vpd_nvram,
4739	fcp->flt_region_vpd, fcp->flt_region_nvram, fcp->flt_region_fdt,
4740	fcp->flt_region_flt, fcp->flt_region_npiv_conf,
4741	fcp->flt_region_fcp_prio);
4742
4743	return (0);
4744	}

Lines 99-104 static struct ispmdvec mdvec_2700 = { Link Here

(-)b/sys/dev/isp/isp_pci.c (+28 lines)
99	NULL	99	NULL
100	};	100	};
101		101
		102	static struct ispmdvec mdvec_2800 = {
		103	isp_pci_run_isr_2400,
		104	isp_pci_rd_reg_2600,
		105	isp_pci_wr_reg_2600,
		106	isp_pci_mbxdma,
		107	isp_send_cmd,
		108	isp_pci_irqsetup,
		109	NULL
		110	};
		111
102	#ifndef PCIM_CMD_INVEN	112	#ifndef PCIM_CMD_INVEN
103	#define PCIM_CMD_INVEN 0x10	113	#define PCIM_CMD_INVEN 0x10
104	#endif	114	#endif
Lines 143-148 static struct ispmdvec mdvec_2700 = { Link Here
143	#define PCI_PRODUCT_QLOGIC_ISP2692 0x2b61	153	#define PCI_PRODUCT_QLOGIC_ISP2692 0x2b61
144	#define PCI_PRODUCT_QLOGIC_ISP2714 0x2071	154	#define PCI_PRODUCT_QLOGIC_ISP2714 0x2071
145	#define PCI_PRODUCT_QLOGIC_ISP2722 0x2261	155	#define PCI_PRODUCT_QLOGIC_ISP2722 0x2261
		156	#define PCI_PRODUCT_QLOGIC_ISP2812 0x2281
		157	#define PCI_PRODUCT_QLOGIC_ISP2814 0x2081
146		158
147	#define PCI_QLOGIC_ISP2422 \	159	#define PCI_QLOGIC_ISP2422 \
148	((PCI_PRODUCT_QLOGIC_ISP2422 << 16) \| PCI_VENDOR_QLOGIC)	160	((PCI_PRODUCT_QLOGIC_ISP2422 << 16) \| PCI_VENDOR_QLOGIC)
Lines 164-169 static struct ispmdvec mdvec_2700 = { Link Here
164	((PCI_PRODUCT_QLOGIC_ISP2714 << 16) \| PCI_VENDOR_QLOGIC)	176	((PCI_PRODUCT_QLOGIC_ISP2714 << 16) \| PCI_VENDOR_QLOGIC)
165	#define PCI_QLOGIC_ISP2722 \	177	#define PCI_QLOGIC_ISP2722 \
166	((PCI_PRODUCT_QLOGIC_ISP2722 << 16) \| PCI_VENDOR_QLOGIC)	178	((PCI_PRODUCT_QLOGIC_ISP2722 << 16) \| PCI_VENDOR_QLOGIC)
		179	#define PCI_QLOGIC_ISP2812 \
		180	((PCI_PRODUCT_QLOGIC_ISP2812 << 16) \| PCI_VENDOR_QLOGIC)
		181	#define PCI_QLOGIC_ISP2814 \
		182	((PCI_PRODUCT_QLOGIC_ISP2814 << 16) \| PCI_VENDOR_QLOGIC)
167		183
168	#define PCI_DFLT_LTNCY 0x40	184	#define PCI_DFLT_LTNCY 0x40
169	#define PCI_DFLT_LNSZ 0x10	185	#define PCI_DFLT_LNSZ 0x10
Lines 245-250 isp_pci_probe(device_t dev) Link Here
245	case PCI_QLOGIC_ISP2722:	261	case PCI_QLOGIC_ISP2722:
246	device_set_desc(dev, "Qlogic ISP 2722 PCI FC Adapter");	262	device_set_desc(dev, "Qlogic ISP 2722 PCI FC Adapter");
247	break;	263	break;
		264	case PCI_QLOGIC_ISP2812:
		265	device_set_desc(dev, "Qlogic ISP 2812 PCI FC Adapter");
		266	break;
		267	case PCI_QLOGIC_ISP2814:
		268	device_set_desc(dev, "Qlogic ISP 2814 PCI FC Adapter");
		269	break;
248	default:	270	default:
249	return (ENXIO);	271	return (ENXIO);
250	}	272	}
Lines 493-498 isp_pci_attach(device_t dev) Link Here
493	isp->isp_mdvec = &mdvec_2700;	515	isp->isp_mdvec = &mdvec_2700;
494	isp->isp_type = ISP_HA_FC_2700;	516	isp->isp_type = ISP_HA_FC_2700;
495	break;	517	break;
		518	case PCI_QLOGIC_ISP2812:
		519	case PCI_QLOGIC_ISP2814:
		520	did = 0x2800;
		521	isp->isp_mdvec = &mdvec_2800;
		522	isp->isp_type = ISP_HA_FC_2800;
		523	break;
496	default:	524	default:
497	device_printf(dev, "unknown device type\n");	525	device_printf(dev, "unknown device type\n");
498	goto bad;	526	goto bad;




#define		MBGSD_8GB	0x04		/* 25XX only */
#define		MBGSD_16GB	0x05		/* 26XX only */
#define		MBGSD_32GB	0x06		/* 27XX only */
#define		MBGSD_64GB	0x07		/* 28XX only */
#define		MBGSD_10GB	0x13		/* 26XX only */
#define	MBOX_SEND_RNFT			0x005e
#define	MBOX_INIT_FIRMWARE		0x0060

#define	ICB2400_OPT3_RATE_8GB		0x00008000
#define	ICB2400_OPT3_RATE_16GB		0x0000A000
#define	ICB2400_OPT3_RATE_32GB		0x0000C000
#define	ICB2400_OPT3_RATE_64GB		0x0000E000
#define	ICB2400_OPT3_ENA_OOF_XFRDY	0x00000200
#define	ICB2400_OPT3_NO_N2N_LOGI	0x00000100
#define	ICB2400_OPT3_NO_LOCAL_PLOGI	0x00000080

#define	ICB_MIN_FRMLEN		256
#define	ICB_MAX_FRMLEN		2112
#define	ICB_DFLT_FRMLEN		1024
#define	ICB_DFLT_FRMLEN_28XX	2048
#define	ICB_DFLT_RDELAY		5
#define	ICB_DFLT_RCOUNT		3





#define	ISP2400_NVRAM_FIRMWARE_OPTIONS3(c)	\
	((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))

/*
 * Qlogic FLT
 */
#define ISP24XX_BASE_ADDR	0x7ff00000
#define ISP24XX_FLT_ADDR	0x11400

#define ISP25XX_BASE_ADDR	ISP24XX_BASE_ADDR
#define ISP25XX_FLT_ADDR	0x50400

#define ISP27XX_BASE_ADDR	0x7f800000
#define ISP27XX_FLT_ADDR	(0x3F1000/4)

#define ISP28XX_BASE_ADDR	0x7f7d0000
#define ISP28XX_FLT_ADDR	(0x11000/4)

#define FLT_HEADER_SIZE		8
#define FLT_REGION_SIZE		16
#define FLT_MAX_REGIONS		0xFF
#define FLT_REGIONS_SIZE	(FLT_REGION_SIZE * FLT_MAX_REGIONS)

#define ISP28XX_FLT_VERSION(c)		((c)[0] | ((c)[1] << 8))
#define ISP28XX_FLT_LENGTH(c)		((c)[2] | ((c)[3] << 8))
#define ISP28XX_FLT_CSUM(c)		((c)[4] | ((c)[5] << 8))
#define ISP28XX_FLT_REG_CODE(c, o)	\
	((c)[0 + FLT_REGION_SIZE * o] | ((c)[1 + FLT_REGION_SIZE * o] << 8))
#define ISP28XX_FLT_REG_ATTR(c, o)	((c)[2 + FLT_REGION_SIZE * o])
#define ISP28XX_FLT_REG_RES(c, o)	((c)[3 + FLT_REGION_SIZE * o])
#define ISP28XX_FLT_REG_SIZE(c, o)	(\
		((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) | \
		((uint32_t)(c)[5 + FLT_REGION_SIZE * o] << 8) | \
		((uint32_t)(c)[6 + FLT_REGION_SIZE * o] << 16) | \
		((uint32_t)(c)[7 + FLT_REGION_SIZE * o] << 24))
#define ISP28XX_FLT_REG_START(c, o)	(\
		((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) | \
		((uint32_t)(c)[9 + FLT_REGION_SIZE * o] << 8) | \
		((uint32_t)(c)[10 + FLT_REGION_SIZE * o] << 16) | \
		((uint32_t)(c)[11 + FLT_REGION_SIZE * o] << 24))
#define ISP28XX_FLT_REG_END(c, o)	(\
		((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) | \
		((uint32_t)(c)[13 + FLT_REGION_SIZE * o] << 8) | \
		((uint32_t)(c)[14 + FLT_REGION_SIZE * o] << 16) | \
		((uint32_t)(c)[15 + FLT_REGION_SIZE * o] << 24))

struct flt_region {
	uint16_t  code;
	uint8_t attribute;
	uint8_t reserved;
	uint32_t size;
	uint32_t start;
	uint32_t end;
};

#define FLT_REG_FW		0x01
#define FLT_REG_BOOT_CODE	0x07
#define FLT_REG_VPD_0		0x14
#define FLT_REG_NVRAM_0		0x15
#define FLT_REG_VPD_1		0x16
#define FLT_REG_NVRAM_1		0x17
#define FLT_REG_VPD_2		0xd4
#define FLT_REG_NVRAM_2		0xd5
#define FLT_REG_VPD_3		0xd6
#define FLT_REG_NVRAM_3		0xd7
#define FLT_REG_FDT		0x1a
#define FLT_REG_FLT		0x1c
#define FLT_REG_NPIV_CONF_0	0x29
#define FLT_REG_NPIV_CONF_1	0x2a
#define FLT_REG_GOLD_FW		0x2f
#define FLT_REG_FCP_PRIO_0	0x87
#define FLT_REG_FCP_PRIO_1	0x88

#define FLT_REG_AUX_IMG_PRI_28XX	0x125
#define FLT_REG_AUX_IMG_SEC_28XX	0x126
#define FLT_REG_NVRAM_SEC_28XX_0	0x10d
#define FLT_REG_NVRAM_SEC_28XX_1	0x10f
#define FLT_REG_NVRAM_SEC_28XX_2	0x111
#define FLT_REG_NVRAM_SEC_28XX_3	0x113
#define FLT_REG_VPD_SEC_28XX_0		0x10c
#define FLT_REG_VPD_SEC_28XX_1		0x10e
#define FLT_REG_VPD_SEC_28XX_2		0x110
#define FLT_REG_VPD_SEC_28XX_3		0x112

#endif	/* _ISPREG_H */




	int			isp_use_gft_id;		/* Use GFT_ID */
	int			isp_use_gff_id;		/* Use GFF_ID */

	uint32_t		flash_data_addr;
	/*
	 * FLT
	 */
	uint16_t		flt_length;
	uint32_t		flt_region_entries;
	uint32_t		flt_region_aux_img_status_pri;
	uint32_t		flt_region_aux_img_status_sec;
	uint32_t		flt_region_boot;
	uint32_t		flt_region_fcp_prio;
	uint32_t		flt_region_fdt;
	uint32_t		flt_region_flt;
	uint32_t		flt_region_fw;
	uint32_t		flt_region_gold_fw;
	uint32_t		flt_region_npiv_conf;
	uint32_t		flt_region_nvram;
	uint32_t		flt_region_nvram_sec;
	uint32_t		flt_region_vpd;
	uint32_t		flt_region_vpd_nvram;
	uint32_t		flt_region_vpd_nvram_sec;
	uint32_t		flt_region_vpd_sec;

	/*
	 * Current active WWNN/WWPN
	 */

#define	ISP_CFG_8GB		0x4000	/* force 8Gb connection (25XX only) */
#define	ISP_CFG_16GB		0x8000	/* force 16Gb connection (26XX only) */
#define	ISP_CFG_32GB		0x10000	/* force 32Gb connection (27XX only) */
#define	ISP_CFG_64GB		0x20000	/* force 64Gb connection (28XX only) */

/*
 * For each channel, the outer layers should know what role that channel

#define	ISP_HA_FC_2500		0x05
#define	ISP_HA_FC_2600		0x06
#define	ISP_HA_FC_2700		0x07
#define	ISP_HA_FC_2800		0x08

#define	IS_25XX(isp)	((isp)->isp_type >= ISP_HA_FC_2500)
#define	IS_26XX(isp)	((isp)->isp_type >= ISP_HA_FC_2600)
#define	IS_27XX(isp)	((isp)->isp_type >= ISP_HA_FC_2700)
#define	IS_28XX(isp)	((isp)->isp_type >= ISP_HA_FC_2800)

/*
 * DMA related macros

Return to bug 271062

Lines 26-32 Link Here

(-)b/share/man/man4/isp.4 (-1 / +9 lines)
26	.\"	26	.\"
27	.\" $FreeBSD$	27	.\" $FreeBSD$
28	.\"	28	.\"
29	.Dd November 19, 2020	29	.Dd April 25, 2023
30	.Dt ISP 4	30	.Dt ISP 4
31	.Os	31	.Os
32	.Sh NAME	32	.Sh NAME
Lines 105-110 Optical 16Gb FC/FCoE PCIe cards. Link Here
105	Optical 16Gb Fibre Channel PCIe cards.	105	Optical 16Gb Fibre Channel PCIe cards.
106	.It Qlogic 2740/2742/2764 (aka 2722/2714)	106	.It Qlogic 2740/2742/2764 (aka 2722/2714)
107	Optical 32Gb Fibre Channel PCIe cards.	107	Optical 32Gb Fibre Channel PCIe cards.
		108	.It Qlogic QLE2770/QLE2772 (aka 2812)
		109	Optical 32Gb Fibre Channel PCIe cards.
		110	.It Qlogic QLE2774 (aka 2814)
		111	Optical 32Gb Fibre Channel PCIe cards.
		112	.It Qlogic QLE2870/QLE2872 (aka 2812)
		113	Optical 64Gb Fibre Channel PCIe cards.
		114	.It Qlogic QLE2874 (aka 2814)
		115	Optical 64Gb Fibre Channel PCIe cards.
108	.El	116	.El
109	.Sh CONFIGURATION OPTIONS	117	.Sh CONFIGURATION OPTIONS
110	Target mode support for Fibre Channel adapters may be enabled with the	118	Target mode support for Fibre Channel adapters may be enabled with the

Lines 179-184 Link Here

(-)b/sys/dev/isp/ispmbox.h (+3 lines)
179	#define MBGSD_8GB 0x04 /* 25XX only */	179	#define MBGSD_8GB 0x04 /* 25XX only */
180	#define MBGSD_16GB 0x05 /* 26XX only */	180	#define MBGSD_16GB 0x05 /* 26XX only */
181	#define MBGSD_32GB 0x06 /* 27XX only */	181	#define MBGSD_32GB 0x06 /* 27XX only */
		182	#define MBGSD_64GB 0x07 /* 28XX only */
182	#define MBGSD_10GB 0x13 /* 26XX only */	183	#define MBGSD_10GB 0x13 /* 26XX only */
183	#define MBOX_SEND_RNFT 0x005e	184	#define MBOX_SEND_RNFT 0x005e
184	#define MBOX_INIT_FIRMWARE 0x0060	185	#define MBOX_INIT_FIRMWARE 0x0060
Lines 647-652 typedef struct { Link Here
647	#define ICB2400_OPT3_RATE_8GB 0x00008000	648	#define ICB2400_OPT3_RATE_8GB 0x00008000
648	#define ICB2400_OPT3_RATE_16GB 0x0000A000	649	#define ICB2400_OPT3_RATE_16GB 0x0000A000
649	#define ICB2400_OPT3_RATE_32GB 0x0000C000	650	#define ICB2400_OPT3_RATE_32GB 0x0000C000
		651	#define ICB2400_OPT3_RATE_64GB 0x0000E000
650	#define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200	652	#define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200
651	#define ICB2400_OPT3_NO_N2N_LOGI 0x00000100	653	#define ICB2400_OPT3_NO_N2N_LOGI 0x00000100
652	#define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080	654	#define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080
Lines 661-666 typedef struct { Link Here
661	#define ICB_MIN_FRMLEN 256	663	#define ICB_MIN_FRMLEN 256
662	#define ICB_MAX_FRMLEN 2112	664	#define ICB_MAX_FRMLEN 2112
663	#define ICB_DFLT_FRMLEN 1024	665	#define ICB_DFLT_FRMLEN 1024
		666	#define ICB_DFLT_FRMLEN_28XX 2048
664	#define ICB_DFLT_RDELAY 5	667	#define ICB_DFLT_RDELAY 5
665	#define ICB_DFLT_RCOUNT 3	668	#define ICB_DFLT_RCOUNT 3
666		669

Lines 252-255 typedef struct { Link Here

(-)b/sys/dev/isp/ispreg.h (+81 lines)
252	#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \	252	#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
253	((c)[52] \| ((c)[53] << 8) \| ((c)[54] << 16) \| ((c)[55] << 24))	253	((c)[52] \| ((c)[53] << 8) \| ((c)[54] << 16) \| ((c)[55] << 24))
254		254
		255	/*
		256	* Qlogic FLT
		257	*/
		258	#define ISP24XX_BASE_ADDR 0x7ff00000
		259	#define ISP24XX_FLT_ADDR 0x11400
		260
		261	#define ISP25XX_BASE_ADDR ISP24XX_BASE_ADDR
		262	#define ISP25XX_FLT_ADDR 0x50400
		263
		264	#define ISP27XX_BASE_ADDR 0x7f800000
		265	#define ISP27XX_FLT_ADDR (0x3F1000/4)
		266
		267	#define ISP28XX_BASE_ADDR 0x7f7d0000
		268	#define ISP28XX_FLT_ADDR (0x11000/4)
		269
		270	#define FLT_HEADER_SIZE 8
		271	#define FLT_REGION_SIZE 16
		272	#define FLT_MAX_REGIONS 0xFF
		273	#define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
		274
		275	#define ISP28XX_FLT_VERSION(c) ((c)[0] \| ((c)[1] << 8))
		276	#define ISP28XX_FLT_LENGTH(c) ((c)[2] \| ((c)[3] << 8))
		277	#define ISP28XX_FLT_CSUM(c) ((c)[4] \| ((c)[5] << 8))
		278	#define ISP28XX_FLT_REG_CODE(c, o) \
		279	((c)[0 + FLT_REGION_SIZE * o] \| ((c)[1 + FLT_REGION_SIZE * o] << 8))
		280	#define ISP28XX_FLT_REG_ATTR(c, o) ((c)[2 + FLT_REGION_SIZE * o])
		281	#define ISP28XX_FLT_REG_RES(c, o) ((c)[3 + FLT_REGION_SIZE * o])
		282	#define ISP28XX_FLT_REG_SIZE(c, o) (\
		283	((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) \| \
		284	((uint32_t)(c)[5 + FLT_REGION_SIZE * o] << 8) \| \
		285	((uint32_t)(c)[6 + FLT_REGION_SIZE * o] << 16) \| \
		286	((uint32_t)(c)[7 + FLT_REGION_SIZE * o] << 24))
		287	#define ISP28XX_FLT_REG_START(c, o) (\
		288	((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) \| \
		289	((uint32_t)(c)[9 + FLT_REGION_SIZE * o] << 8) \| \
		290	((uint32_t)(c)[10 + FLT_REGION_SIZE * o] << 16) \| \
		291	((uint32_t)(c)[11 + FLT_REGION_SIZE * o] << 24))
		292	#define ISP28XX_FLT_REG_END(c, o) (\
		293	((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) \| \
		294	((uint32_t)(c)[13 + FLT_REGION_SIZE * o] << 8) \| \
		295	((uint32_t)(c)[14 + FLT_REGION_SIZE * o] << 16) \| \
		296	((uint32_t)(c)[15 + FLT_REGION_SIZE * o] << 24))
		297
		298	struct flt_region {
		299	uint16_t code;
		300	uint8_t attribute;
		301	uint8_t reserved;
		302	uint32_t size;
		303	uint32_t start;
		304	uint32_t end;
		305	};
		306
		307	#define FLT_REG_FW 0x01
		308	#define FLT_REG_BOOT_CODE 0x07
		309	#define FLT_REG_VPD_0 0x14
		310	#define FLT_REG_NVRAM_0 0x15
		311	#define FLT_REG_VPD_1 0x16
		312	#define FLT_REG_NVRAM_1 0x17
		313	#define FLT_REG_VPD_2 0xd4
		314	#define FLT_REG_NVRAM_2 0xd5
		315	#define FLT_REG_VPD_3 0xd6
		316	#define FLT_REG_NVRAM_3 0xd7
		317	#define FLT_REG_FDT 0x1a
		318	#define FLT_REG_FLT 0x1c
319	#define FLT_REG_NPIV_CONF_0 0x29
320	#define FLT_REG_NPIV_CONF_1 0x2a
321	#define FLT_REG_GOLD_FW 0x2f
322	#define FLT_REG_FCP_PRIO_0 0x87
323	#define FLT_REG_FCP_PRIO_1 0x88
324
325	#define FLT_REG_AUX_IMG_PRI_28XX 0x125
326	#define FLT_REG_AUX_IMG_SEC_28XX 0x126
327	#define FLT_REG_NVRAM_SEC_28XX_0 0x10d
328	#define FLT_REG_NVRAM_SEC_28XX_1 0x10f
329	#define FLT_REG_NVRAM_SEC_28XX_2 0x111
330	#define FLT_REG_NVRAM_SEC_28XX_3 0x113
331	#define FLT_REG_VPD_SEC_28XX_0 0x10c
332	#define FLT_REG_VPD_SEC_28XX_1 0x10e
333	#define FLT_REG_VPD_SEC_28XX_2 0x110
334	#define FLT_REG_VPD_SEC_28XX_3 0x112
335
255	#endif /* _ISPREG_H */	336	#endif /* _ISPREG_H */

Lines 369-374 typedef struct { Link Here

(-)b/sys/dev/isp/ispvar.h (+25 lines)
369	int isp_use_gft_id; /* Use GFT_ID */	369	int isp_use_gft_id; /* Use GFT_ID */
370	int isp_use_gff_id; /* Use GFF_ID */	370	int isp_use_gff_id; /* Use GFF_ID */
371		371
		372	uint32_t flash_data_addr;
		373	/*
		374	* FLT
		375	*/
		376	uint16_t flt_length;
		377	uint32_t flt_region_entries;
		378	uint32_t flt_region_aux_img_status_pri;
		379	uint32_t flt_region_aux_img_status_sec;
		380	uint32_t flt_region_boot;
		381	uint32_t flt_region_fcp_prio;
		382	uint32_t flt_region_fdt;
		383	uint32_t flt_region_flt;
		384	uint32_t flt_region_fw;
		385	uint32_t flt_region_gold_fw;
		386	uint32_t flt_region_npiv_conf;
		387	uint32_t flt_region_nvram;
		388	uint32_t flt_region_nvram_sec;
		389	uint32_t flt_region_vpd;
		390	uint32_t flt_region_vpd_nvram;
		391	uint32_t flt_region_vpd_nvram_sec;
		392	uint32_t flt_region_vpd_sec;
		393
372	/*	394	/*
373	* Current active WWNN/WWPN	395	* Current active WWNN/WWPN
374	*/	396	*/
Lines 539-544 struct ispsoftc { Link Here
539	#define ISP_CFG_8GB 0x4000 /* force 8Gb connection (25XX only) */	561	#define ISP_CFG_8GB 0x4000 /* force 8Gb connection (25XX only) */
540	#define ISP_CFG_16GB 0x8000 /* force 16Gb connection (26XX only) */	562	#define ISP_CFG_16GB 0x8000 /* force 16Gb connection (26XX only) */
541	#define ISP_CFG_32GB 0x10000 /* force 32Gb connection (27XX only) */	563	#define ISP_CFG_32GB 0x10000 /* force 32Gb connection (27XX only) */
		564	#define ISP_CFG_64GB 0x20000 /* force 64Gb connection (28XX only) */
542		565
543	/*	566	/*
544	* For each channel, the outer layers should know what role that channel	567	* For each channel, the outer layers should know what role that channel
Lines 607-616 struct ispsoftc { Link Here
607	#define ISP_HA_FC_2500 0x05	630	#define ISP_HA_FC_2500 0x05
608	#define ISP_HA_FC_2600 0x06	631	#define ISP_HA_FC_2600 0x06
609	#define ISP_HA_FC_2700 0x07	632	#define ISP_HA_FC_2700 0x07
		633	#define ISP_HA_FC_2800 0x08
610		634
611	#define IS_25XX(isp) ((isp)->isp_type >= ISP_HA_FC_2500)	635	#define IS_25XX(isp) ((isp)->isp_type >= ISP_HA_FC_2500)
612	#define IS_26XX(isp) ((isp)->isp_type >= ISP_HA_FC_2600)	636	#define IS_26XX(isp) ((isp)->isp_type >= ISP_HA_FC_2600)
613	#define IS_27XX(isp) ((isp)->isp_type >= ISP_HA_FC_2700)	637	#define IS_27XX(isp) ((isp)->isp_type >= ISP_HA_FC_2700)
		638	#define IS_28XX(isp) ((isp)->isp_type >= ISP_HA_FC_2800)
614		639
615	/*	640	/*
616	* DMA related macros	641	* DMA related macros