Attachment #241964 for bug #271062




.\"
.\" $FreeBSD$
.\"
.Dd April 25, 2023
.Dt ISP 4
.Os
.Sh NAME

Optical 16Gb Fibre Channel PCIe cards.
.It Qlogic 2740/2742/2764 (aka 2722/2714)
Optical 32Gb Fibre Channel PCIe cards.
.It Qlogic QLE2770/QLE2772 (aka 2812)
Optical 32Gb Fibre Channel PCIe cards.
.It Qlogic QLE2774 (aka 2814)
Optical 32Gb Fibre Channel PCIe cards.
.It Qlogic QLE2870/QLE2872 (aka 2812)
Optical 64Gb Fibre Channel PCIe cards.
.It Qlogic QLE2874 (aka 2814)
Optical 64Gb Fibre Channel PCIe cards.
.El
.Sh CONFIGURATION OPTIONS
Target mode support for Fibre Channel adapters may be enabled with the

Lines 22-28 Link Here

(-)b/share/man/man4/ispfw.4 (-1 / +4 lines)
22	.\"	22	.\"
23	.\" $FreeBSD$	23	.\" $FreeBSD$
24	.\"	24	.\"
25	.Dd November 19, 2020	25	.Dd April 25, 2023
26	.Dt ISPFW 4	26	.Dt ISPFW 4
27	.Os	27	.Os
28	.Sh NAME	28	.Sh NAME
Lines 60-62 This driver was written by Link Here
60	.An Matthew Jacob .	60	.An Matthew Jacob .
61	Later improvement was done by	61	Later improvement was done by
62	.An Alexander Motin Aq Mt mav@FreeBSD.org .	62	.An Alexander Motin Aq Mt mav@FreeBSD.org .
		63	.Sh BUGS
		64	Only firmware for the 24xx and 25xx based cards is included in
		65	.Nm .

Lines 119-126 static void isp_mboxcmd(ispsoftc_t , mbreg_t ); Link Here

(-)b/sys/dev/isp/isp.c (-33 / +341 lines)
119		119
120	static void isp_setdfltfcparm(ispsoftc_t *, int);	120	static void isp_setdfltfcparm(ispsoftc_t *, int);
121	static int isp_read_nvram(ispsoftc_t *, int);	121	static int isp_read_nvram(ispsoftc_t *, int);
		122	static void isp_rd_2xxx_flash(ispsoftc_t , uint32_t, uint32_t );
		123	static int isp_read_flthdr_2xxx(ispsoftc_t *);
		124	static void isp_parse_flthdr_2xxx(ispsoftc_t , uint8_t );
		125	static int isp_read_flt_2xxx(ispsoftc_t *);
		126	static int isp_parse_flt_2xxx(ispsoftc_t , uint8_t );
122	static int isp_read_nvram_2400(ispsoftc_t *);	127	static int isp_read_nvram_2400(ispsoftc_t *);
123	static void isp_rd_2400_nvram(ispsoftc_t , uint32_t, uint32_t );
124	static void isp_parse_nvram_2400(ispsoftc_t , uint8_t );	128	static void isp_parse_nvram_2400(ispsoftc_t , uint8_t );
125		129
126	static void	130	static void
Lines 179-184 isp_reset(ispsoftc_t *isp, int do_load_defaults) Link Here
179	case ISP_HA_FC_2700:	183	case ISP_HA_FC_2700:
180	btype = "2700";	184	btype = "2700";
181	break;	185	break;
		186	case ISP_HA_FC_2800:
		187	btype = "2800";
		188	break;
182	default:	189	default:
183	break;	190	break;
184	}	191	}
Lines 710-717 isp_init(ispsoftc_t *isp) Link Here
710	icbp->icb_version = ICB_VERSION1;	717	icbp->icb_version = ICB_VERSION1;
711	icbp->icb_maxfrmlen = DEFAULT_FRAMESIZE(isp);	718	icbp->icb_maxfrmlen = DEFAULT_FRAMESIZE(isp);
712	if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN \|\| icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) {	719	if (icbp->icb_maxfrmlen < ICB_MIN_FRMLEN \|\| icbp->icb_maxfrmlen > ICB_MAX_FRMLEN) {
713	isp_prt(isp, ISP_LOGERR, "bad frame length (%d) from NVRAM- using %d", DEFAULT_FRAMESIZE(isp), ICB_DFLT_FRMLEN);
714	icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN;	720	icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN;
		721	if (IS_28XX(isp))
		722	icbp->icb_maxfrmlen = ICB_DFLT_FRMLEN_28XX;
		723
		724	isp_prt(isp, ISP_LOGERR, "bad frame length (%d) from NVRAM - using %d", DEFAULT_FRAMESIZE(isp), icbp->icb_maxfrmlen);
715	}	725	}
716		726
717	if (!IS_26XX(isp))	727	if (!IS_26XX(isp))
Lines 822-833 isp_init(ispsoftc_t *isp) Link Here
822	} else if (isp->isp_confopts & ISP_CFG_32GB) {	832	} else if (isp->isp_confopts & ISP_CFG_32GB) {
823	icbp->icb_fwoptions3 &= ~ICB2400_OPT3_RATE_MASK;	833	icbp->icb_fwoptions3 &= ~ICB2400_OPT3_RATE_MASK;
824	icbp->icb_fwoptions3 \|= ICB2400_OPT3_RATE_32GB;	834	icbp->icb_fwoptions3 \|= ICB2400_OPT3_RATE_32GB;
		835	} else if (isp->isp_confopts & ISP_CFG_64GB) {
		836	icbp->icb_fwoptions3 &= ~ICB2400_OPT3_RATE_MASK;
		837	icbp->icb_fwoptions3 \|= ICB2400_OPT3_RATE_64GB;
825	} else {	838	} else {
826	switch (icbp->icb_fwoptions3 & ICB2400_OPT3_RATE_MASK) {	839	switch (icbp->icb_fwoptions3 & ICB2400_OPT3_RATE_MASK) {
827	case ICB2400_OPT3_RATE_4GB:	840	case ICB2400_OPT3_RATE_4GB:
828	case ICB2400_OPT3_RATE_8GB:	841	case ICB2400_OPT3_RATE_8GB:
829	case ICB2400_OPT3_RATE_16GB:	842	case ICB2400_OPT3_RATE_16GB:
830	case ICB2400_OPT3_RATE_32GB:	843	case ICB2400_OPT3_RATE_32GB:
		844	case ICB2400_OPT3_RATE_64GB:
831	case ICB2400_OPT3_RATE_AUTO:	845	case ICB2400_OPT3_RATE_AUTO:
832	break;	846	break;
833	case ICB2400_OPT3_RATE_2GB:	847	case ICB2400_OPT3_RATE_2GB:
Lines 1537-1542 isp_fclink_test(ispsoftc_t *isp, int chan, int usdelay) Link Here
1537	if (mbs.param[0] == MBOX_COMMAND_COMPLETE) {	1551	if (mbs.param[0] == MBOX_COMMAND_COMPLETE) {
1538	if (mbs.param[1] == MBGSD_10GB)	1552	if (mbs.param[1] == MBGSD_10GB)
1539	fcp->isp_gbspeed = 10;	1553	fcp->isp_gbspeed = 10;
		1554	else if (mbs.param[1] == MBGSD_64GB)
		1555	fcp->isp_gbspeed = 64;
1540	else if (mbs.param[1] == MBGSD_32GB)	1556	else if (mbs.param[1] == MBGSD_32GB)
1541	fcp->isp_gbspeed = 32;	1557	fcp->isp_gbspeed = 32;
1542	else if (mbs.param[1] == MBGSD_16GB)	1558	else if (mbs.param[1] == MBGSD_16GB)
Lines 4322-4342 isp_reinit(ispsoftc_t *isp, int do_load_defaults) Link Here
4322	static int	4338	static int
4323	isp_read_nvram(ispsoftc_t *isp, int bus)	4339	isp_read_nvram(ispsoftc_t *isp, int bus)
4324	{	4340	{
4325		4341	fcparam *fcp = FCPARAM(isp, 0);
		4342	int r = 0;
		4343
		4344	if (isp->isp_type != ISP_HA_FC_2600) {
		4345	if (IS_28XX(isp)) {
		4346	fcp->flash_data_addr = ISP28XX_BASE_ADDR;
		4347	fcp->flt_region_flt = ISP28XX_FLT_ADDR;
		4348	} else if (IS_27XX(isp)) {
		4349	fcp->flash_data_addr = ISP27XX_BASE_ADDR;
		4350	fcp->flt_region_flt = ISP27XX_FLT_ADDR;
		4351	} else if (IS_25XX(isp)) {
		4352	fcp->flash_data_addr = ISP25XX_BASE_ADDR;
		4353	fcp->flt_region_flt = ISP25XX_FLT_ADDR;
		4354	} else {
		4355	fcp->flash_data_addr = ISP24XX_BASE_ADDR;
		4356	fcp->flt_region_flt = ISP24XX_FLT_ADDR;
		4357	}
		4358	fcp->flt_length = 0;
		4359	r = isp_read_flthdr_2xxx(isp);
		4360	if (r == 0) {
		4361	isp_read_flt_2xxx(isp);
		4362	} else { /* fallback to hardcoded NVRAM address */
		4363	if (IS_28XX(isp)) {
		4364	fcp->flt_region_nvram = 0x300000;
		4365	} else if (IS_27XX(isp)) {
		4366	fcp->flash_data_addr = 0x7fe7c000;
		4367	fcp->flt_region_nvram = 0;
		4368	} else if (IS_25XX(isp)) {
		4369	fcp->flt_region_nvram = 0x48000;
		4370	} else {
		4371	fcp->flash_data_addr = 0x7ffe0000;
		4372	fcp->flt_region_nvram = 0;
		4373	}
		4374	fcp->flt_region_nvram += ISP2400_NVRAM_PORT_ADDR(isp->isp_port);
		4375	}
		4376	} else {
		4377	fcp->flash_data_addr = 0x7fe7c000;
		4378	fcp->flt_region_nvram = 0;
		4379	fcp->flt_region_nvram += ISP2400_NVRAM_PORT_ADDR(isp->isp_port);
		4380	}
4326	return (isp_read_nvram_2400(isp));	4381	return (isp_read_nvram_2400(isp));
4327	}	4382	}
4328		4383
		4384	static void
		4385	isp_rd_2xxx_flash(ispsoftc_t isp, uint32_t addr, uint32_t rp)
		4386	{
		4387	fcparam *fcp = FCPARAM(isp, 0);
		4388	int loops = 0;
		4389	uint32_t base = fcp->flash_data_addr;
		4390	uint32_t tmp = 0;
		4391
		4392	ISP_WRITE(isp, BIU2400_FLASH_ADDR, base + addr);
		4393	for (loops = 0; loops < 5000; loops++) {
		4394	ISP_DELAY(10);
		4395	tmp = ISP_READ(isp, BIU2400_FLASH_ADDR);
		4396	if ((tmp & (1U << 31)) != 0) {
		4397	break;
		4398	}
		4399	}
		4400	if (tmp & (1U << 31)) {
		4401	*rp = ISP_READ(isp, BIU2400_FLASH_DATA);
		4402	ISP_SWIZZLE_NVRAM_LONG(isp, rp);
		4403	} else {
		4404	*rp = 0xffffffff;
		4405	}
		4406	}
		4407
		4408	static int
		4409	isp_read_flthdr_2xxx(ispsoftc_t *isp)
		4410	{
		4411	fcparam *fcp = FCPARAM(isp, 0);
		4412	int retval = 0;
		4413	uint32_t addr, lwrds, *dptr;
		4414	uint16_t csum;
		4415	uint8_t flthdr_data[FLT_HEADER_SIZE];
		4416
		4417	addr = fcp->flt_region_flt;
		4418	dptr = (uint32_t *) flthdr_data;
		4419
		4420	isp_prt(isp, ISP_LOGDEBUG0,
		4421	"FLTL[DEF]: 0x%x", addr);
		4422	for (lwrds = 0; lwrds < FLT_HEADER_SIZE >> 2; lwrds++) {
		4423	isp_rd_2xxx_flash(isp, addr++, dptr++);
		4424	}
		4425	dptr = (uint32_t *) flthdr_data;
		4426	for (csum = 0, lwrds = 0; lwrds < FLT_HEADER_SIZE >> 4; lwrds++) {
		4427	uint16_t tmp;
		4428	ISP_IOXGET_16(isp, &dptr[lwrds], tmp);
		4429	csum += tmp;
		4430	}
		4431	if (csum != 0) {
		4432	retval = -1;
		4433	goto out;
		4434	}
		4435	isp_parse_flthdr_2xxx(isp, flthdr_data);
		4436	out:
		4437	return (retval);
		4438	}
		4439
		4440	static void
		4441	isp_parse_flthdr_2xxx(ispsoftc_t isp, uint8_t flthdr_data)
		4442	{
		4443	fcparam *fcp = FCPARAM(isp, 0);
		4444	uint16_t ver, csum;
		4445
		4446	ver = le16toh((uint16_t) (ISP2XXX_FLT_VERSION(flthdr_data)));
		4447	fcp->flt_length = le16toh((uint16_t) (ISP2XXX_FLT_LENGTH(flthdr_data)));
4448	csum = le16toh((uint16_t) (ISP2XXX_FLT_CSUM(flthdr_data)));
4449
4450	if ((fcp->flt_length == 0 ) \|\|
4451	(fcp->flt_length > (FLT_HEADER_SIZE + FLT_REGIONS_SIZE))) {
4452	isp_prt(isp, ISP_LOGERR,
4453	"FLT[DEF]: Invalid length=0x%x(%d)",
4454	fcp->flt_length, fcp->flt_length);
4455	}
4456	isp_prt(isp, ISP_LOGDEBUG0,
4457	"FLT[DEF]: version=0x%x length=0x%x(%d) checksum=0x%x",
4458	ver, fcp->flt_length, fcp->flt_length, csum);
4459	}
4460
4461	static int
4462	isp_read_flt_2xxx(ispsoftc_t *isp)
4463	{
4464	fcparam *fcp = FCPARAM(isp, 0);
4465	int retval = 0;
4466	int len = fcp->flt_length - FLT_HEADER_SIZE;
4467	uint32_t addr, lwrds, *dptr;
4468	uint8_t flt_data[len];
4469	fcp->flt_region_entries = len / FLT_REGION_SIZE;
4470
4471	addr = fcp->flt_region_flt + (FLT_HEADER_SIZE >> 2);
4472	dptr = (uint32_t *) flt_data;
4473	isp_prt(isp, ISP_LOGDEBUG0, "FLT[DEF]: regions=%d",
4474	fcp->flt_region_entries);
4475	for (lwrds = 0; lwrds < len >> 2; lwrds++) {
4476	isp_rd_2xxx_flash(isp, addr++, dptr++);
4477	}
4478	retval = isp_parse_flt_2xxx(isp, flt_data);
4479	return (retval);
4480	}
4481
4482	static int
4483	isp_parse_flt_2xxx(ispsoftc_t isp, uint8_t flt_data)
4484	{
4485	fcparam *fcp = FCPARAM(isp, 0);
4486	int count;
4487	struct flt_region region[fcp->flt_region_entries];
4488
4489	for (count = 0; count < fcp->flt_region_entries; count++) {
4490	region[count].code =
4491	le16toh((uint16_t) (ISP2XXX_FLT_REG_CODE(flt_data, count)));
4492	region[count].attribute =
4493	(uint8_t) (ISP2XXX_FLT_REG_ATTR(flt_data, count));
4494	region[count].reserved =
4495	(uint8_t) (ISP2XXX_FLT_REG_RES(flt_data, count));
4496	region[count].size =
4497	le32toh((uint32_t) (ISP2XXX_FLT_REG_SIZE(flt_data, count)) >> 2);
4498	region[count].start =
4499	le32toh((uint32_t) (ISP2XXX_FLT_REG_START(flt_data, count)) >> 2);
4500	region[count].end =
4501	le32toh((uint32_t) (ISP2XXX_FLT_REG_END(flt_data, count)) >> 2);
4502
4503	isp_prt(isp, ISP_LOGDEBUG0,
4504	"FLT[0x%x]: start=0x%x end=0x%x size=0x%x attribute=0x%x",
4505	region[count].code, region[count].start, region[count].end,
4506	region[count].size, region[count].attribute);
4507
4508	switch(region[count].code) {
4509	case FLT_REG_FW:
4510	fcp->flt_region_fw = region[count].start;
4511	break;
4512	case FLT_REG_BOOT_CODE:
4513	fcp->flt_region_boot = region[count].start;
4514	break;
4515	case FLT_REG_VPD_0:
4516	fcp->flt_region_vpd_nvram = region[count].start;
4517	if (isp->isp_port == 0)
4518	fcp->flt_region_vpd = region[count].start;
4519	break;
4520	case FLT_REG_VPD_1:
4521	if (isp->isp_port == 1)
4522	fcp->flt_region_vpd = region[count].start;
4523	break;
4524	case FLT_REG_VPD_2:
4525	if (!IS_27XX(isp))
4526	break;
4527	if (isp->isp_port == 2)
4528	fcp->flt_region_vpd = region[count].start;
4529	break;
4530	case FLT_REG_VPD_3:
4531	if (!IS_27XX(isp))
4532	break;
4533	if (isp->isp_port == 3)
4534	fcp->flt_region_vpd = region[count].start;
4535	break;
4536	case FLT_REG_NVRAM_0:
4537	if (isp->isp_port == 0)
4538	fcp->flt_region_nvram = region[count].start;
4539	break;
4540	case FLT_REG_NVRAM_1:
4541	if (isp->isp_port == 1)
4542	fcp->flt_region_nvram = region[count].start;
4543	break;
4544	case FLT_REG_NVRAM_2:
4545	if (!IS_27XX(isp))
4546	break;
4547	if (isp->isp_port == 2)
4548	fcp->flt_region_nvram = region[count].start;
4549	break;
4550	case FLT_REG_NVRAM_3:
4551	if (!IS_27XX(isp))
4552	break;
4553	if (isp->isp_port == 3)
4554	fcp->flt_region_nvram = region[count].start;
4555	break;
4556	case FLT_REG_FDT:
4557	fcp->flt_region_fdt = region[count].start;
4558	break;
4559	case FLT_REG_FLT:
4560	fcp->flt_region_flt = region[count].start;
4561	break;
4562	case FLT_REG_NPIV_CONF_0:
4563	if (isp->isp_port == 0)
4564	fcp->flt_region_npiv_conf = region[count].start;
4565	break;
4566	case FLT_REG_NPIV_CONF_1:
4567	if (isp->isp_port == 1)
4568	fcp->flt_region_npiv_conf = region[count].start;
4569	break;
4570	case FLT_REG_GOLD_FW:
4571	fcp->flt_region_gold_fw = region[count].start;
4572	break;
4573	case FLT_REG_FCP_PRIO_0:
4574	if (isp->isp_port == 0)
4575	fcp->flt_region_fcp_prio = region[count].start;
4576	break;
4577	case FLT_REG_FCP_PRIO_1:
4578	if (isp->isp_port == 1)
4579	fcp->flt_region_fcp_prio = region[count].start;
4580	break;
4581	case FLT_REG_IMG_PRI_27XX:
4582	if (IS_27XX(isp))
4583	fcp->flt_region_img_status_pri = region[count].start;
4584	break;
4585	case FLT_REG_IMG_SEC_27XX:
4586	if (IS_27XX(isp))
4587	fcp->flt_region_img_status_sec = region[count].start;
4588	break;
4589	case FLT_REG_FW_SEC_27XX:
4590	if (IS_27XX(isp))
4591	fcp->flt_region_fw_sec = region[count].start;
4592	break;
4593	case FLT_REG_BOOTLOAD_SEC_27XX:
4594	if (IS_27XX(isp))
4595	fcp->flt_region_boot_sec = region[count].start;
4596	break;
4597	case FLT_REG_AUX_IMG_PRI_28XX:
4598	if (IS_27XX(isp))
4599	fcp->flt_region_aux_img_status_pri = region[count].start;
4600	break;
4601	case FLT_REG_AUX_IMG_SEC_28XX:
4602	if (IS_27XX(isp))
4603	fcp->flt_region_aux_img_status_sec = region[count].start;
4604	break;
4605	case FLT_REG_NVRAM_SEC_28XX_0:
4606	if (IS_27XX(isp))
4607	if (isp->isp_port == 0)
4608	fcp->flt_region_nvram_sec = region[count].start;
4609	break;
4610	case FLT_REG_NVRAM_SEC_28XX_1:
4611	if (IS_27XX(isp))
4612	if (isp->isp_port == 1)
4613	fcp->flt_region_nvram_sec = region[count].start;
4614	break;
4615	case FLT_REG_NVRAM_SEC_28XX_2:
4616	if (IS_27XX(isp))
4617	if (isp->isp_port == 2)
4618	fcp->flt_region_nvram_sec = region[count].start;
4619	break;
4620	case FLT_REG_NVRAM_SEC_28XX_3:
4621	if (IS_27XX(isp))
4622	if (isp->isp_port == 3)
4623	fcp->flt_region_nvram_sec = region[count].start;
4624	break;
4625	case FLT_REG_VPD_SEC_27XX_0:
4626	case FLT_REG_VPD_SEC_28XX_0:
4627	if (IS_27XX(isp)) {
4628	fcp->flt_region_vpd_nvram_sec = region[count].start;
4629	if (isp->isp_port == 0)
4630	fcp->flt_region_vpd_sec = region[count].start;
4631	}
4632	break;
4633	case FLT_REG_VPD_SEC_27XX_1:
4634	case FLT_REG_VPD_SEC_28XX_1:
4635	if (IS_27XX(isp))
4636	if (isp->isp_port == 1)
4637	fcp->flt_region_vpd_sec = region[count].start;
4638	break;
4639	case FLT_REG_VPD_SEC_27XX_2:
4640	case FLT_REG_VPD_SEC_28XX_2:
4641	if (IS_27XX(isp))
4642	if (isp->isp_port == 2)
4643	fcp->flt_region_vpd_sec = region[count].start;
4644	break;
4645	case FLT_REG_VPD_SEC_27XX_3:
4646	case FLT_REG_VPD_SEC_28XX_3:
4647	if (IS_27XX(isp))
4648	if (isp->isp_port == 3)
4649	fcp->flt_region_vpd_sec = region[count].start;
4650	break;
4651	}
4652	}
4653	isp_prt(isp, ISP_LOGDEBUG0,
4654	"FLT[FLT]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram 0x%x "
4655	"fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x",
4656	fcp->flt_region_boot, fcp->flt_region_fw, fcp->flt_region_vpd_nvram,
4657	fcp->flt_region_vpd, fcp->flt_region_nvram, fcp->flt_region_fdt,
4658	fcp->flt_region_flt, fcp->flt_region_npiv_conf,
4659	fcp->flt_region_fcp_prio);
4660
4661	return (0);
4662	}
4663
4329	static int	4664	static int
4330	isp_read_nvram_2400(ispsoftc_t *isp)	4665	isp_read_nvram_2400(ispsoftc_t *isp)
4331	{	4666	{
		4667	fcparam *fcp = FCPARAM(isp, 0);
4332	int retval = 0;	4668	int retval = 0;
4333	uint32_t addr, csum, lwrds, *dptr;	4669	uint32_t addr, csum, lwrds, *dptr;
4334	uint8_t nvram_data[ISP2400_NVRAM_SIZE];	4670	uint8_t nvram_data[ISP2400_NVRAM_SIZE];
4335		4671
4336	addr = ISP2400_NVRAM_PORT_ADDR(isp->isp_port);	4672	addr = fcp->flt_region_nvram;
4337	dptr = (uint32_t *) nvram_data;	4673	dptr = (uint32_t *) nvram_data;
4338	for (lwrds = 0; lwrds < ISP2400_NVRAM_SIZE >> 2; lwrds++) {	4674	for (lwrds = 0; lwrds < ISP2400_NVRAM_SIZE >> 2; lwrds++) {
4339	isp_rd_2400_nvram(isp, addr++, dptr++);	4675	isp_rd_2xxx_flash(isp, addr++, dptr++);
4340	}	4676	}
4341	if (nvram_data[0] != 'I' \|\| nvram_data[1] != 'S' \|\|	4677	if (nvram_data[0] != 'I' \|\| nvram_data[1] != 'S' \|\|
4342	nvram_data[2] != 'P') {	4678	nvram_data[2] != 'P') {
Lines 4361-4394 isp_read_nvram_2400(ispsoftc_t *isp) Link Here
4361	return (retval);	4697	return (retval);
4362	}	4698	}
4363		4699
4364	static void
4365	isp_rd_2400_nvram(ispsoftc_t isp, uint32_t addr, uint32_t rp)
4366	{
4367	int loops = 0;
4368	uint32_t base = 0x7ffe0000;
4369	uint32_t tmp = 0;
4370
4371	if (IS_26XX(isp)) {
4372	base = 0x7fe7c000; /* XXX: Observation, may be wrong. */
4373	} else if (IS_25XX(isp)) {
4374	base = 0x7ff00000 \| 0x48000;
4375	}
4376	ISP_WRITE(isp, BIU2400_FLASH_ADDR, base \| addr);
4377	for (loops = 0; loops < 5000; loops++) {
4378	ISP_DELAY(10);
4379	tmp = ISP_READ(isp, BIU2400_FLASH_ADDR);
4380	if ((tmp & (1U << 31)) != 0) {
4381	break;
4382	}
4383	}
4384	if (tmp & (1U << 31)) {
4385	*rp = ISP_READ(isp, BIU2400_FLASH_DATA);
4386	ISP_SWIZZLE_NVRAM_LONG(isp, rp);
4387	} else {
4388	*rp = 0xffffffff;
4389	}
4390	}
4391
4392	static void	4700	static void
4393	isp_parse_nvram_2400(ispsoftc_t isp, uint8_t nvram_data)	4701	isp_parse_nvram_2400(ispsoftc_t isp, uint8_t nvram_data)
4394	{	4702	{

Lines 99-104 static struct ispmdvec mdvec_2700 = { Link Here

(-)b/sys/dev/isp/isp_pci.c (+28 lines)
99	NULL	99	NULL
100	};	100	};
101		101
		102	static struct ispmdvec mdvec_2800 = {
		103	isp_pci_run_isr_2400,
		104	isp_pci_rd_reg_2600,
		105	isp_pci_wr_reg_2600,
		106	isp_pci_mbxdma,
		107	isp_send_cmd,
		108	isp_pci_irqsetup,
		109	NULL
		110	};
		111
102	#ifndef PCIM_CMD_INVEN	112	#ifndef PCIM_CMD_INVEN
103	#define PCIM_CMD_INVEN 0x10	113	#define PCIM_CMD_INVEN 0x10
104	#endif	114	#endif
Lines 143-148 static struct ispmdvec mdvec_2700 = { Link Here
143	#define PCI_PRODUCT_QLOGIC_ISP2692 0x2b61	153	#define PCI_PRODUCT_QLOGIC_ISP2692 0x2b61
144	#define PCI_PRODUCT_QLOGIC_ISP2714 0x2071	154	#define PCI_PRODUCT_QLOGIC_ISP2714 0x2071
145	#define PCI_PRODUCT_QLOGIC_ISP2722 0x2261	155	#define PCI_PRODUCT_QLOGIC_ISP2722 0x2261
		156	#define PCI_PRODUCT_QLOGIC_ISP2812 0x2281
		157	#define PCI_PRODUCT_QLOGIC_ISP2814 0x2081
146		158
147	#define PCI_QLOGIC_ISP2422 \	159	#define PCI_QLOGIC_ISP2422 \
148	((PCI_PRODUCT_QLOGIC_ISP2422 << 16) \| PCI_VENDOR_QLOGIC)	160	((PCI_PRODUCT_QLOGIC_ISP2422 << 16) \| PCI_VENDOR_QLOGIC)
Lines 164-169 static struct ispmdvec mdvec_2700 = { Link Here
164	((PCI_PRODUCT_QLOGIC_ISP2714 << 16) \| PCI_VENDOR_QLOGIC)	176	((PCI_PRODUCT_QLOGIC_ISP2714 << 16) \| PCI_VENDOR_QLOGIC)
165	#define PCI_QLOGIC_ISP2722 \	177	#define PCI_QLOGIC_ISP2722 \
166	((PCI_PRODUCT_QLOGIC_ISP2722 << 16) \| PCI_VENDOR_QLOGIC)	178	((PCI_PRODUCT_QLOGIC_ISP2722 << 16) \| PCI_VENDOR_QLOGIC)
		179	#define PCI_QLOGIC_ISP2812 \
		180	((PCI_PRODUCT_QLOGIC_ISP2812 << 16) \| PCI_VENDOR_QLOGIC)
		181	#define PCI_QLOGIC_ISP2814 \
		182	((PCI_PRODUCT_QLOGIC_ISP2814 << 16) \| PCI_VENDOR_QLOGIC)
167		183
168	#define PCI_DFLT_LTNCY 0x40	184	#define PCI_DFLT_LTNCY 0x40
169	#define PCI_DFLT_LNSZ 0x10	185	#define PCI_DFLT_LNSZ 0x10
Lines 245-250 isp_pci_probe(device_t dev) Link Here
245	case PCI_QLOGIC_ISP2722:	261	case PCI_QLOGIC_ISP2722:
246	device_set_desc(dev, "Qlogic ISP 2722 PCI FC Adapter");	262	device_set_desc(dev, "Qlogic ISP 2722 PCI FC Adapter");
247	break;	263	break;
		264	case PCI_QLOGIC_ISP2812:
		265	device_set_desc(dev, "Qlogic ISP 2812 PCI FC Adapter");
		266	break;
		267	case PCI_QLOGIC_ISP2814:
		268	device_set_desc(dev, "Qlogic ISP 2814 PCI FC Adapter");
		269	break;
248	default:	270	default:
249	return (ENXIO);	271	return (ENXIO);
250	}	272	}
Lines 493-498 isp_pci_attach(device_t dev) Link Here
493	isp->isp_mdvec = &mdvec_2700;	515	isp->isp_mdvec = &mdvec_2700;
494	isp->isp_type = ISP_HA_FC_2700;	516	isp->isp_type = ISP_HA_FC_2700;
495	break;	517	break;
		518	case PCI_QLOGIC_ISP2812:
		519	case PCI_QLOGIC_ISP2814:
		520	did = 0x2800;
		521	isp->isp_mdvec = &mdvec_2800;
		522	isp->isp_type = ISP_HA_FC_2800;
		523	break;
496	default:	524	default:
497	device_printf(dev, "unknown device type\n");	525	device_printf(dev, "unknown device type\n");
498	goto bad;	526	goto bad;




#define		MBGSD_8GB	0x04		/* 25XX only */
#define		MBGSD_16GB	0x05		/* 26XX only */
#define		MBGSD_32GB	0x06		/* 27XX only */
#define		MBGSD_64GB	0x07		/* 28XX only */
#define		MBGSD_10GB	0x13		/* 26XX only */
#define	MBOX_SEND_RNFT			0x005e
#define	MBOX_INIT_FIRMWARE		0x0060

#define	ICB2400_OPT3_RATE_8GB		0x00008000
#define	ICB2400_OPT3_RATE_16GB		0x0000A000
#define	ICB2400_OPT3_RATE_32GB		0x0000C000
#define	ICB2400_OPT3_RATE_64GB		0x0000E000
#define	ICB2400_OPT3_ENA_OOF_XFRDY	0x00000200
#define	ICB2400_OPT3_NO_N2N_LOGI	0x00000100
#define	ICB2400_OPT3_NO_LOCAL_PLOGI	0x00000080

#define	ICB_MIN_FRMLEN		256
#define	ICB_MAX_FRMLEN		2112
#define	ICB_DFLT_FRMLEN		1024
#define	ICB_DFLT_FRMLEN_28XX	2048
#define	ICB_DFLT_RDELAY		5
#define	ICB_DFLT_RCOUNT		3





#define	ISP2400_NVRAM_FIRMWARE_OPTIONS3(c)	\
	((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))

/*
 * Qlogic FLT
 */
#define ISP24XX_BASE_ADDR	0x7ff00000
#define ISP24XX_FLT_ADDR	0x11400

#define ISP25XX_BASE_ADDR	ISP24XX_BASE_ADDR
#define ISP25XX_FLT_ADDR	0x50400

#define ISP27XX_BASE_ADDR	0x7f800000
#define ISP27XX_FLT_ADDR	(0x3F1000/4)

#define ISP28XX_BASE_ADDR	0x7f7d0000
#define ISP28XX_FLT_ADDR	(0x11000/4)

#define FLT_HEADER_SIZE		8
#define FLT_REGION_SIZE		16
#define FLT_MAX_REGIONS		0xFF
#define FLT_REGIONS_SIZE	(FLT_REGION_SIZE * FLT_MAX_REGIONS)

#define ISP2XXX_FLT_VERSION(c)		((c)[0] | ((c)[1] << 8))
#define ISP2XXX_FLT_LENGTH(c)		((c)[2] | ((c)[3] << 8))
#define ISP2XXX_FLT_CSUM(c)		((c)[4] | ((c)[5] << 8))
#define ISP2XXX_FLT_REG_CODE(c, o)	\
	((c)[0 + FLT_REGION_SIZE * o] | ((c)[1 + FLT_REGION_SIZE * o] << 8))
#define ISP2XXX_FLT_REG_ATTR(c, o)	((c)[2 + FLT_REGION_SIZE * o])
#define ISP2XXX_FLT_REG_RES(c, o)	((c)[3 + FLT_REGION_SIZE * o])
#define ISP2XXX_FLT_REG_SIZE(c, o)	(\
		((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) | \
		((uint32_t)(c)[5 + FLT_REGION_SIZE * o] << 8) | \
		((uint32_t)(c)[6 + FLT_REGION_SIZE * o] << 16) | \
		((uint32_t)(c)[7 + FLT_REGION_SIZE * o] << 24))
#define ISP2XXX_FLT_REG_START(c, o)	(\
		((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) | \
		((uint32_t)(c)[9 + FLT_REGION_SIZE * o] << 8) | \
		((uint32_t)(c)[10 + FLT_REGION_SIZE * o] << 16) | \
		((uint32_t)(c)[11 + FLT_REGION_SIZE * o] << 24))
#define ISP2XXX_FLT_REG_END(c, o)	(\
		((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) | \
		((uint32_t)(c)[13 + FLT_REGION_SIZE * o] << 8) | \
		((uint32_t)(c)[14 + FLT_REGION_SIZE * o] << 16) | \
		((uint32_t)(c)[15 + FLT_REGION_SIZE * o] << 24))

struct flt_region {
	uint16_t  code;
	uint8_t attribute;
	uint8_t reserved;
	uint32_t size;
	uint32_t start;
	uint32_t end;
};

#define FLT_REG_FW		0x01
#define FLT_REG_BOOT_CODE	0x07
#define FLT_REG_VPD_0		0x14
#define FLT_REG_NVRAM_0		0x15
#define FLT_REG_VPD_1		0x16
#define FLT_REG_NVRAM_1		0x17
#define FLT_REG_VPD_2		0xd4
#define FLT_REG_NVRAM_2		0xd5
#define FLT_REG_VPD_3		0xd6
#define FLT_REG_NVRAM_3		0xd7
#define FLT_REG_FDT		0x1a
#define FLT_REG_FLT		0x1c
#define FLT_REG_NPIV_CONF_0	0x29
#define FLT_REG_NPIV_CONF_1	0x2a
#define FLT_REG_GOLD_FW		0x2f
#define FLT_REG_FCP_PRIO_0	0x87
#define FLT_REG_FCP_PRIO_1	0x88

/* 27xx */
#define FLT_REG_IMG_PRI_27XX	0x95
#define FLT_REG_IMG_SEC_27XX	0x96
#define FLT_REG_FW_SEC_27XX	0x02
#define FLT_REG_BOOTLOAD_SEC_27XX	0x9
#define FLT_REG_VPD_SEC_27XX_0	0x50
#define FLT_REG_VPD_SEC_27XX_1	0x52
#define FLT_REG_VPD_SEC_27XX_2	0xd8
#define FLT_REG_VPD_SEC_27XX_3	0xda

/* 28xx */
#define FLT_REG_AUX_IMG_PRI_28XX	0x125
#define FLT_REG_AUX_IMG_SEC_28XX	0x126
#define FLT_REG_NVRAM_SEC_28XX_0	0x10d
#define FLT_REG_NVRAM_SEC_28XX_1	0x10f
#define FLT_REG_NVRAM_SEC_28XX_2	0x111
#define FLT_REG_NVRAM_SEC_28XX_3	0x113
#define FLT_REG_VPD_SEC_28XX_0		0x10c
#define FLT_REG_VPD_SEC_28XX_1		0x10e
#define FLT_REG_VPD_SEC_28XX_2		0x110
#define FLT_REG_VPD_SEC_28XX_3		0x112

#endif	/* _ISPREG_H */




	int			isp_use_gft_id;		/* Use GFT_ID */
	int			isp_use_gff_id;		/* Use GFF_ID */

	uint32_t		flash_data_addr;
	/*
	 * FLT
	 */
	uint16_t		flt_length;
	uint32_t		flt_region_entries;
	uint32_t		flt_region_aux_img_status_pri;
	uint32_t		flt_region_aux_img_status_sec;
	uint32_t		flt_region_boot;
	uint32_t		flt_region_fcp_prio;
	uint32_t		flt_region_fdt;
	uint32_t		flt_region_flt;
	uint32_t		flt_region_fw;
	uint32_t		flt_region_gold_fw;
	uint32_t		flt_region_img_status_pri;
	uint32_t		flt_region_img_status_sec;
	uint32_t		flt_region_fw_sec;
	uint32_t		flt_region_boot_sec;
	uint32_t		flt_region_npiv_conf;
	uint32_t		flt_region_nvram;
	uint32_t		flt_region_nvram_sec;
	uint32_t		flt_region_vpd;
	uint32_t		flt_region_vpd_nvram;
	uint32_t		flt_region_vpd_nvram_sec;
	uint32_t		flt_region_vpd_sec;

	/*
	 * Current active WWNN/WWPN
	 */

#define	ISP_CFG_8GB		0x4000	/* force 8Gb connection (25XX only) */
#define	ISP_CFG_16GB		0x8000	/* force 16Gb connection (26XX only) */
#define	ISP_CFG_32GB		0x10000	/* force 32Gb connection (27XX only) */
#define	ISP_CFG_64GB		0x20000	/* force 64Gb connection (28XX only) */

/*
 * For each channel, the outer layers should know what role that channel

#define	ISP_HA_FC_2500		0x05
#define	ISP_HA_FC_2600		0x06
#define	ISP_HA_FC_2700		0x07
#define	ISP_HA_FC_2800		0x08

#define	IS_25XX(isp)	((isp)->isp_type >= ISP_HA_FC_2500)
#define	IS_26XX(isp)	((isp)->isp_type >= ISP_HA_FC_2600)
#define	IS_27XX(isp)	((isp)->isp_type >= ISP_HA_FC_2700)
#define	IS_28XX(isp)	((isp)->isp_type >= ISP_HA_FC_2800)

/*
 * DMA related macros

Return to bug 271062

Lines 26-32 Link Here

(-)b/share/man/man4/isp.4 (-1 / +9 lines)
26	.\"	26	.\"
27	.\" $FreeBSD$	27	.\" $FreeBSD$
28	.\"	28	.\"
29	.Dd November 19, 2020	29	.Dd April 25, 2023
30	.Dt ISP 4	30	.Dt ISP 4
31	.Os	31	.Os
32	.Sh NAME	32	.Sh NAME
Lines 105-110 Optical 16Gb FC/FCoE PCIe cards. Link Here
105	Optical 16Gb Fibre Channel PCIe cards.	105	Optical 16Gb Fibre Channel PCIe cards.
106	.It Qlogic 2740/2742/2764 (aka 2722/2714)	106	.It Qlogic 2740/2742/2764 (aka 2722/2714)
107	Optical 32Gb Fibre Channel PCIe cards.	107	Optical 32Gb Fibre Channel PCIe cards.
		108	.It Qlogic QLE2770/QLE2772 (aka 2812)
		109	Optical 32Gb Fibre Channel PCIe cards.
		110	.It Qlogic QLE2774 (aka 2814)
		111	Optical 32Gb Fibre Channel PCIe cards.
		112	.It Qlogic QLE2870/QLE2872 (aka 2812)
		113	Optical 64Gb Fibre Channel PCIe cards.
		114	.It Qlogic QLE2874 (aka 2814)
		115	Optical 64Gb Fibre Channel PCIe cards.
108	.El	116	.El
109	.Sh CONFIGURATION OPTIONS	117	.Sh CONFIGURATION OPTIONS
110	Target mode support for Fibre Channel adapters may be enabled with the	118	Target mode support for Fibre Channel adapters may be enabled with the

Lines 179-184 Link Here

(-)b/sys/dev/isp/ispmbox.h (+3 lines)
179	#define MBGSD_8GB 0x04 /* 25XX only */	179	#define MBGSD_8GB 0x04 /* 25XX only */
180	#define MBGSD_16GB 0x05 /* 26XX only */	180	#define MBGSD_16GB 0x05 /* 26XX only */
181	#define MBGSD_32GB 0x06 /* 27XX only */	181	#define MBGSD_32GB 0x06 /* 27XX only */
		182	#define MBGSD_64GB 0x07 /* 28XX only */
182	#define MBGSD_10GB 0x13 /* 26XX only */	183	#define MBGSD_10GB 0x13 /* 26XX only */
183	#define MBOX_SEND_RNFT 0x005e	184	#define MBOX_SEND_RNFT 0x005e
184	#define MBOX_INIT_FIRMWARE 0x0060	185	#define MBOX_INIT_FIRMWARE 0x0060
Lines 647-652 typedef struct { Link Here
647	#define ICB2400_OPT3_RATE_8GB 0x00008000	648	#define ICB2400_OPT3_RATE_8GB 0x00008000
648	#define ICB2400_OPT3_RATE_16GB 0x0000A000	649	#define ICB2400_OPT3_RATE_16GB 0x0000A000
649	#define ICB2400_OPT3_RATE_32GB 0x0000C000	650	#define ICB2400_OPT3_RATE_32GB 0x0000C000
		651	#define ICB2400_OPT3_RATE_64GB 0x0000E000
650	#define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200	652	#define ICB2400_OPT3_ENA_OOF_XFRDY 0x00000200
651	#define ICB2400_OPT3_NO_N2N_LOGI 0x00000100	653	#define ICB2400_OPT3_NO_N2N_LOGI 0x00000100
652	#define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080	654	#define ICB2400_OPT3_NO_LOCAL_PLOGI 0x00000080
Lines 661-666 typedef struct { Link Here
661	#define ICB_MIN_FRMLEN 256	663	#define ICB_MIN_FRMLEN 256
662	#define ICB_MAX_FRMLEN 2112	664	#define ICB_MAX_FRMLEN 2112
663	#define ICB_DFLT_FRMLEN 1024	665	#define ICB_DFLT_FRMLEN 1024
		666	#define ICB_DFLT_FRMLEN_28XX 2048
664	#define ICB_DFLT_RDELAY 5	667	#define ICB_DFLT_RDELAY 5
665	#define ICB_DFLT_RCOUNT 3	668	#define ICB_DFLT_RCOUNT 3
666		669

Lines 252-255 typedef struct { Link Here

(-)b/sys/dev/isp/ispreg.h (+92 lines)
252	#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \	252	#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
253	((c)[52] \| ((c)[53] << 8) \| ((c)[54] << 16) \| ((c)[55] << 24))	253	((c)[52] \| ((c)[53] << 8) \| ((c)[54] << 16) \| ((c)[55] << 24))
254		254
		255	/*
		256	* Qlogic FLT
		257	*/
		258	#define ISP24XX_BASE_ADDR 0x7ff00000
		259	#define ISP24XX_FLT_ADDR 0x11400
		260
		261	#define ISP25XX_BASE_ADDR ISP24XX_BASE_ADDR
		262	#define ISP25XX_FLT_ADDR 0x50400
		263
		264	#define ISP27XX_BASE_ADDR 0x7f800000
		265	#define ISP27XX_FLT_ADDR (0x3F1000/4)
		266
		267	#define ISP28XX_BASE_ADDR 0x7f7d0000
		268	#define ISP28XX_FLT_ADDR (0x11000/4)
		269
		270	#define FLT_HEADER_SIZE 8
		271	#define FLT_REGION_SIZE 16
		272	#define FLT_MAX_REGIONS 0xFF
		273	#define FLT_REGIONS_SIZE (FLT_REGION_SIZE * FLT_MAX_REGIONS)
		274
		275	#define ISP2XXX_FLT_VERSION(c) ((c)[0] \| ((c)[1] << 8))
		276	#define ISP2XXX_FLT_LENGTH(c) ((c)[2] \| ((c)[3] << 8))
		277	#define ISP2XXX_FLT_CSUM(c) ((c)[4] \| ((c)[5] << 8))
		278	#define ISP2XXX_FLT_REG_CODE(c, o) \
		279	((c)[0 + FLT_REGION_SIZE * o] \| ((c)[1 + FLT_REGION_SIZE * o] << 8))
		280	#define ISP2XXX_FLT_REG_ATTR(c, o) ((c)[2 + FLT_REGION_SIZE * o])
		281	#define ISP2XXX_FLT_REG_RES(c, o) ((c)[3 + FLT_REGION_SIZE * o])
		282	#define ISP2XXX_FLT_REG_SIZE(c, o) (\
		283	((uint32_t)(c)[4 + FLT_REGION_SIZE * o] << 0) \| \
		284	((uint32_t)(c)[5 + FLT_REGION_SIZE * o] << 8) \| \
		285	((uint32_t)(c)[6 + FLT_REGION_SIZE * o] << 16) \| \
		286	((uint32_t)(c)[7 + FLT_REGION_SIZE * o] << 24))
		287	#define ISP2XXX_FLT_REG_START(c, o) (\
		288	((uint32_t)(c)[8 + FLT_REGION_SIZE * o] << 0) \| \
		289	((uint32_t)(c)[9 + FLT_REGION_SIZE * o] << 8) \| \
		290	((uint32_t)(c)[10 + FLT_REGION_SIZE * o] << 16) \| \
		291	((uint32_t)(c)[11 + FLT_REGION_SIZE * o] << 24))
		292	#define ISP2XXX_FLT_REG_END(c, o) (\
		293	((uint32_t)(c)[12 + FLT_REGION_SIZE * o] << 0) \| \
		294	((uint32_t)(c)[13 + FLT_REGION_SIZE * o] << 8) \| \
		295	((uint32_t)(c)[14 + FLT_REGION_SIZE * o] << 16) \| \
		296	((uint32_t)(c)[15 + FLT_REGION_SIZE * o] << 24))
		297
		298	struct flt_region {
		299	uint16_t code;
		300	uint8_t attribute;
		301	uint8_t reserved;
		302	uint32_t size;
		303	uint32_t start;
		304	uint32_t end;
		305	};
		306
		307	#define FLT_REG_FW 0x01
		308	#define FLT_REG_BOOT_CODE 0x07
		309	#define FLT_REG_VPD_0 0x14
		310	#define FLT_REG_NVRAM_0 0x15
		311	#define FLT_REG_VPD_1 0x16
		312	#define FLT_REG_NVRAM_1 0x17
		313	#define FLT_REG_VPD_2 0xd4
		314	#define FLT_REG_NVRAM_2 0xd5
		315	#define FLT_REG_VPD_3 0xd6
		316	#define FLT_REG_NVRAM_3 0xd7
		317	#define FLT_REG_FDT 0x1a
		318	#define FLT_REG_FLT 0x1c
319	#define FLT_REG_NPIV_CONF_0 0x29
320	#define FLT_REG_NPIV_CONF_1 0x2a
321	#define FLT_REG_GOLD_FW 0x2f
322	#define FLT_REG_FCP_PRIO_0 0x87
323	#define FLT_REG_FCP_PRIO_1 0x88
324
325	/* 27xx */
326	#define FLT_REG_IMG_PRI_27XX 0x95
327	#define FLT_REG_IMG_SEC_27XX 0x96
328	#define FLT_REG_FW_SEC_27XX 0x02
329	#define FLT_REG_BOOTLOAD_SEC_27XX 0x9
330	#define FLT_REG_VPD_SEC_27XX_0 0x50
331	#define FLT_REG_VPD_SEC_27XX_1 0x52
332	#define FLT_REG_VPD_SEC_27XX_2 0xd8
333	#define FLT_REG_VPD_SEC_27XX_3 0xda
334
335	/* 28xx */
336	#define FLT_REG_AUX_IMG_PRI_28XX 0x125
337	#define FLT_REG_AUX_IMG_SEC_28XX 0x126
338	#define FLT_REG_NVRAM_SEC_28XX_0 0x10d
339	#define FLT_REG_NVRAM_SEC_28XX_1 0x10f
340	#define FLT_REG_NVRAM_SEC_28XX_2 0x111
341	#define FLT_REG_NVRAM_SEC_28XX_3 0x113
342	#define FLT_REG_VPD_SEC_28XX_0 0x10c
343	#define FLT_REG_VPD_SEC_28XX_1 0x10e
344	#define FLT_REG_VPD_SEC_28XX_2 0x110
345	#define FLT_REG_VPD_SEC_28XX_3 0x112
346
255	#endif /* _ISPREG_H */	347	#endif /* _ISPREG_H */

Lines 369-374 typedef struct { Link Here

(-)b/sys/dev/isp/ispvar.h (+29 lines)
369	int isp_use_gft_id; /* Use GFT_ID */	369	int isp_use_gft_id; /* Use GFT_ID */
370	int isp_use_gff_id; /* Use GFF_ID */	370	int isp_use_gff_id; /* Use GFF_ID */
371		371
		372	uint32_t flash_data_addr;
		373	/*
		374	* FLT
		375	*/
		376	uint16_t flt_length;
		377	uint32_t flt_region_entries;
		378	uint32_t flt_region_aux_img_status_pri;
		379	uint32_t flt_region_aux_img_status_sec;
		380	uint32_t flt_region_boot;
		381	uint32_t flt_region_fcp_prio;
		382	uint32_t flt_region_fdt;
		383	uint32_t flt_region_flt;
		384	uint32_t flt_region_fw;
		385	uint32_t flt_region_gold_fw;
		386	uint32_t flt_region_img_status_pri;
		387	uint32_t flt_region_img_status_sec;
		388	uint32_t flt_region_fw_sec;
		389	uint32_t flt_region_boot_sec;
		390	uint32_t flt_region_npiv_conf;
		391	uint32_t flt_region_nvram;
		392	uint32_t flt_region_nvram_sec;
		393	uint32_t flt_region_vpd;
		394	uint32_t flt_region_vpd_nvram;
		395	uint32_t flt_region_vpd_nvram_sec;
		396	uint32_t flt_region_vpd_sec;
		397
372	/*	398	/*
373	* Current active WWNN/WWPN	399	* Current active WWNN/WWPN
374	*/	400	*/
Lines 539-544 struct ispsoftc { Link Here
539	#define ISP_CFG_8GB 0x4000 /* force 8Gb connection (25XX only) */	565	#define ISP_CFG_8GB 0x4000 /* force 8Gb connection (25XX only) */
540	#define ISP_CFG_16GB 0x8000 /* force 16Gb connection (26XX only) */	566	#define ISP_CFG_16GB 0x8000 /* force 16Gb connection (26XX only) */
541	#define ISP_CFG_32GB 0x10000 /* force 32Gb connection (27XX only) */	567	#define ISP_CFG_32GB 0x10000 /* force 32Gb connection (27XX only) */
		568	#define ISP_CFG_64GB 0x20000 /* force 64Gb connection (28XX only) */
542		569
543	/*	570	/*
544	* For each channel, the outer layers should know what role that channel	571	* For each channel, the outer layers should know what role that channel
Lines 607-616 struct ispsoftc { Link Here
607	#define ISP_HA_FC_2500 0x05	634	#define ISP_HA_FC_2500 0x05
608	#define ISP_HA_FC_2600 0x06	635	#define ISP_HA_FC_2600 0x06
609	#define ISP_HA_FC_2700 0x07	636	#define ISP_HA_FC_2700 0x07
		637	#define ISP_HA_FC_2800 0x08
610		638
611	#define IS_25XX(isp) ((isp)->isp_type >= ISP_HA_FC_2500)	639	#define IS_25XX(isp) ((isp)->isp_type >= ISP_HA_FC_2500)
612	#define IS_26XX(isp) ((isp)->isp_type >= ISP_HA_FC_2600)	640	#define IS_26XX(isp) ((isp)->isp_type >= ISP_HA_FC_2600)
613	#define IS_27XX(isp) ((isp)->isp_type >= ISP_HA_FC_2700)	641	#define IS_27XX(isp) ((isp)->isp_type >= ISP_HA_FC_2700)
		642	#define IS_28XX(isp) ((isp)->isp_type >= ISP_HA_FC_2800)
614		643
615	/*	644	/*
616	* DMA related macros	645	* DMA related macros