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Lines 408-414
powermac_register_timebase(device_t dev, powermac_tb_disable_t cb)
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| 408 |
static void |
408 |
static void |
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powermac_smp_timebase_sync(platform_t plat, u_long tb, int ap) |
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powermac_smp_timebase_sync(platform_t plat, u_long tb, int ap) |
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{ |
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{ |
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static volatile bool tb_ready; |
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static volatile int tb_ready; |
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static volatile int cpu_done; |
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static volatile int cpu_done; |
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/* |
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/* |
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Lines 424-450
powermac_smp_timebase_sync(platform_t plat, u_long tb, int ap)
Link Here
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| 424 |
if (ap) { |
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if (ap) { |
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/* APs. Hold off until we get a stable timebase. */ |
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/* APs. Hold off until we get a stable timebase. */ |
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critical_enter(); |
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critical_enter(); |
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while (!tb_ready) |
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while (atomic_load_acq_int(&tb_ready) < 1) |
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atomic_thread_fence_seq_cst(); |
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atomic_thread_fence_seq_cst(); |
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mttb(tb); |
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mttb(tb); |
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atomic_add_int(&cpu_done, 1); |
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atomic_add_rel_int(&cpu_done, 1); |
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while (cpu_done < mp_ncpus) |
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while (atomic_load_acq_int(&cpu_done) < mp_ncpus) |
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atomic_thread_fence_seq_cst(); |
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atomic_thread_fence_seq_cst(); |
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critical_exit(); |
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critical_exit(); |
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} else { |
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} else { |
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/* BSP */ |
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/* BSP */ |
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critical_enter(); |
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critical_enter(); |
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/* Ensure cpu_done is zeroed so we can resync at runtime */ |
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/* Ensure cpu_done is zeroed so we can resync at runtime */ |
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atomic_set_int(&cpu_done, 0); |
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atomic_set_rel_int(&cpu_done, 0); |
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freeze_timebase(powermac_tb_dev, true); |
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freeze_timebase(powermac_tb_dev, true); |
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tb_ready = true; |
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atomic_set_rel_int(&tb_ready, 1); |
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mttb(tb); |
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mttb(tb); |
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atomic_add_int(&cpu_done, 1); |
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atomic_add_rel_int(&cpu_done, 1); |
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while (cpu_done < mp_ncpus) |
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while (atomic_load_acq_int(&cpu_done) < mp_ncpus) |
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atomic_thread_fence_seq_cst(); |
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atomic_thread_fence_seq_cst(); |
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freeze_timebase(powermac_tb_dev, false); |
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freeze_timebase(powermac_tb_dev, false); |
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/* Reset tb_ready so we can resync at runtime */ |
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/* Reset tb_ready so we can resync at runtime */ |
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tb_ready = false; |
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atomic_set_rel_int(&tb_ready, 0); |
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critical_exit(); |
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critical_exit(); |
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} |
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} |
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} |
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} |