Attachment #255497 for bug #282738

View | Details | Raw Unified | Return to bug 282738 | Differences between
Collapse All | Expand All




/*-
 * Copyright (c) 2016 Daniel Wyatt <Daniel.Wyatt@gmail.com>
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 */

/*
 * Nuvoton GPIO driver.
 */

#include <sys/cdefs.h>

#include <sys/param.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/eventhandler.h>
#include <sys/lock.h>

#include <sys/module.h>
#include <sys/gpio.h>

#include <machine/bus.h>

#include <dev/gpio/gpiobusvar.h>
#include <dev/superio/superio.h>

#include "gpio_if.h"

#define NCT_PPOD_LDN 0xf /* LDN used to select Push-Pull/Open-Drain */

/* Direct access through GPIO register table */
#define	NCT_IO_GSR			0 /* Group Select */
#define	NCT_IO_IOR			1 /* I/O */
#define	NCT_IO_DAT			2 /* Data */
#define	NCT_IO_INV			3 /* Inversion */
#define	NCT_IO_DST          4 /* Status */

#define NCT_MAX_GROUP   9
#define NCT_MAX_PIN     75

#define NCT_PIN_IS_VALID(_sc, _p)   ((_p) < (_sc)->npins)
#define NCT_PIN_GROUP(_sc, _p)      ((_sc)->pinmap[(_p)].group)
#define NCT_PIN_GRPNUM(_sc, _p)     ((_sc)->pinmap[(_p)].grpnum)
#define NCT_PIN_BIT(_sc, _p)        ((_sc)->pinmap[(_p)].bit)
#define NCT_PIN_BITMASK(_p)         (1 << ((_p) & 7))

#define NCT_GPIO_CAPS	(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
	GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \
	GPIO_PIN_INVIN | GPIO_PIN_INVOUT)

#define NCT_PREFER_INDIRECT_CHANNEL 2
#define NCT_NO_ENABLE               4

#define NCT_VERBOSE_PRINTF(dev, ...)            \
	do {                                        \
		if (__predict_false(bootverbose))       \
			device_printf(dev, __VA_ARGS__);    \
	} while (0)

/*
 * Note that the values are important.
 * They match actual register offsets.
 */
typedef enum {
	REG_IOR = 0,
	REG_DAT = 1,
	REG_INV = 2,
} reg_t;

struct nct_gpio_group {
 	uint32_t    caps;
	uint8_t     enable_ldn;
	uint8_t     enable_reg;
	uint8_t     enable_mask;
	uint8_t     data_ldn;
	uint8_t     iobase;
	uint8_t     ppod_reg; /* Push-Pull/Open-Drain */
	uint8_t     grpnum;
	uint8_t     pinbits[8];
	uint8_t     npins;
};

struct nct_softc {
	device_t			dev;
	device_t			busdev;
	struct mtx			mtx;
	struct resource			*iores;
	int				iorid;
	int				curgrp;
	struct {
		uint8_t ior[NCT_MAX_GROUP + 1];       /* direction, 1: input 0: output */
		uint8_t out[NCT_MAX_GROUP + 1];       /* output value */
		uint8_t out_known[NCT_MAX_GROUP + 1]; /* whether out is valid */
		uint8_t inv[NCT_MAX_GROUP + 1];       /* inversion, 1: inverted */
	} cache;
	struct gpio_pin				pins[NCT_MAX_PIN + 1];
	struct nct_device			*nctdevp;
	int							npins; /* Total number of pins */

	/* Lookup tables */
	struct {
		struct nct_gpio_group *group;
		uint8_t                grpnum;
		uint8_t                bit;
	} pinmap[NCT_MAX_PIN+1];
	struct nct_gpio_group *grpmap[NCT_MAX_GROUP+1];
};

#define GPIO_LOCK_INIT(_sc)	mtx_init(&(_sc)->mtx,		\
		device_get_nameunit(dev), NULL, MTX_DEF)
#define GPIO_LOCK_DESTROY(_sc)		mtx_destroy(&(_sc)->mtx)
#define GPIO_LOCK(_sc)		mtx_lock(&(_sc)->mtx)
#define GPIO_UNLOCK(_sc)	mtx_unlock(&(_sc)->mtx)
#define GPIO_ASSERT_LOCKED(_sc)	mtx_assert(&(_sc)->mtx, MA_OWNED)
#define GPIO_ASSERT_UNLOCKED(_sc)	mtx_assert(&(_sc)->mtx, MA_NOTOWNED)

#define GET_BIT(v, b)	(((v) >> (b)) & 1)

/*
 * For most devices there are several GPIO devices, we attach only to one of
 * them and use the rest without attaching.
 */
struct nct_device {
	uint16_t                  devid;
	uint16_t                  mask;
	int                       extid;
	uint8_t                   ldn;
	const char               *descr;
	int                       ngroups;
	struct nct_gpio_group     groups[NCT_MAX_GROUP + 1];
} nct_devices[] = {
	{
		.devid   = 0xa025,
		.descr   = "GPIO on Winbond 83627DHG IC ver. 5",
		.ngroups = 5,
		.groups  = {
			{
				.grpnum      = 2,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x01,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe0, /* FIXME Need to check for this group. */
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe3,
			},
			{
				.grpnum      = 3,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x02,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf0,
			},
			{
				.grpnum      = 4,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x04,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf4,
			},
			{
				.grpnum      = 5,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x08,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe0,
			},
			{
				.grpnum      = 6,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x01,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1, /* FIXME Need to check for this group. */
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf4,
			},
		},
	},
	{
		.devid   = 0x1061,
		.descr   = "GPIO on Nuvoton NCT5104D",
		.ngroups = 2,
		.groups  = {
			{
				.grpnum      = 0,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x01,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe0,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe0,
			},
			{
				.grpnum      = 1,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x02,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe4,

			},
			{
				.grpnum      = 1,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x02,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe4,
			},
			{
				.grpnum      = 2,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x04,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe8,
			},
			{
				.grpnum      = 3,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x08,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xec,
			},
			{
				.grpnum      = 4,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x10,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf0,
			},
			{
				.grpnum      = 5,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x20,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf4,
			},
			{
				.grpnum      = 6,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x40,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf8,
			},
			{
				.grpnum      = 7,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x80,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xfc,
			},
			{
				.grpnum      = 8,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x01,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf0,
			},
		},
	},
	{
		.devid   = 0xd284,
		.mask    = 0xffdf,
		.ldn	 = 7,
		.descr   = "GPIO on Nuvoton NCT6122D/NCT6126D",
		.ngroups = 8,
		.groups  = {
			// LDN7, GPIO0-7
			{
				.grpnum      = 0,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x01,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe0,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe0,
			},
			{
				.grpnum      = 1,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x02,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe1,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe4,
			},
			{
				.grpnum      = 2,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x04,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe2,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xe8,
			},
			{
				.grpnum      = 3,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x08,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe3,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xec,
			},
			{
				.grpnum      = 4,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x10,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe4,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf0,
			},
			{
				.grpnum      = 5,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x20,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe5,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf4,
			},
			{
				.grpnum      = 6,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x40,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe6,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf8,
			},
			{
				.grpnum      = 7,
				.pinbits     = { 0, 1 },
				.enable_ldn  = 0x07,
				.enable_reg  = 0x30,
				.enable_mask = 0x80,
				.data_ldn    = 0x07,
				.ppod_reg    = 0xe7,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 2,
				.iobase      = 0xfc,
			},
		},
	},
	{
		.devid   = 0xd284,
		.mask    = 0xffdf,
		.ldn	 = 9,
		.descr   = "GPIO on Nuvoton NCT6122D/NCT6126D",
		.ngroups = 4,
		.groups  = {
			// LDN9, GPIO8,GPIO9,GPIOA,GPIOB
			{
				.grpnum      = 8,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x01,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe8,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf0,
			},
			{
				.grpnum      = 9,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x02,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xe9,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf4,
			},
			{
				.grpnum      = 0xa,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x04,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xea,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xf8,
			},
			{
				.grpnum      = 0xb,
				.pinbits     = { 0, 1, 2, 3, 4, 5, 6, 7 },
				.enable_ldn  = 0x09,
				.enable_reg  = 0x30,
				.enable_mask = 0x08,
				.data_ldn    = 0x09,
				.ppod_reg    = 0xeb,
				.caps        = NCT_GPIO_CAPS,
				.npins       = 8,
				.iobase      = 0xfc,
			},
		},
	},
};

static const char *
io2str(uint8_t ioport)
{
	switch (ioport) {
	case NCT_IO_GSR: return ("grpsel");
	case NCT_IO_IOR: return ("io");
	case NCT_IO_DAT: return ("data");
	case NCT_IO_INV: return ("inv");
	case NCT_IO_DST: return ("status");
	default:         return ("?");
	}
}

static void
nct_io_set_group(struct nct_softc *sc, uint8_t grpnum)
{
	GPIO_ASSERT_LOCKED(sc);

	if (grpnum == sc->curgrp)
		return;

	NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n",
		io2str(NCT_IO_GSR), grpnum, NCT_IO_GSR);
	bus_write_1(sc->iores, NCT_IO_GSR, grpnum);
	sc->curgrp = grpnum;
}

static uint8_t
nct_io_read(struct nct_softc *sc, uint8_t grpnum, uint8_t reg)
{
	uint8_t val;

	nct_io_set_group(sc, grpnum);

	val = bus_read_1(sc->iores, reg);
	NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x ioport %d\n",
		io2str(reg), val, reg);
	return (val);
}

static void
nct_io_write(struct nct_softc *sc, uint8_t grpnum, uint8_t reg, uint8_t val)
{
	nct_io_set_group(sc, grpnum);

	NCT_VERBOSE_PRINTF(sc->dev, "write %s 0x%x ioport %d\n",
		io2str(reg), val, reg);
	bus_write_1(sc->iores, reg, val);
}

static uint8_t
nct_get_ioreg(struct nct_softc *sc, reg_t reg, uint8_t grpnum)
{
	uint8_t iobase;

	if (sc->iores != NULL)
		iobase = NCT_IO_IOR;
	else
		iobase = sc->grpmap[grpnum]->iobase;
	return (iobase + reg);
}

static const char *
reg2str(reg_t reg)
{
	switch (reg) {
	case REG_IOR: return ("io");
	case REG_DAT: return ("data");
	case REG_INV: return ("inv");
	default:      return ("?");
	}
}

static uint8_t
nct_read_reg(struct nct_softc *sc, reg_t reg, uint8_t grpnum)
{
	struct nct_gpio_group *gp;
	uint8_t                ioreg;
	uint8_t                val;

	ioreg = nct_get_ioreg(sc, reg, grpnum);

	if (sc->iores != NULL)
		return (nct_io_read(sc, grpnum, ioreg));

	gp  = sc->grpmap[grpnum];
	val = superio_ldn_read(sc->dev, gp->data_ldn, ioreg);
	NCT_VERBOSE_PRINTF(sc->dev, "read %s 0x%x from group GPIO%u ioreg 0x%x\n",
		reg2str(reg), val, grpnum, ioreg);
	return (val);
}

static int
nct_get_pin_cache(struct nct_softc *sc, uint32_t pin_num, uint8_t *cache)
{
	uint8_t bit;
	uint8_t group;

		else
			NCT_VERBOSE_PRINTF(sc->dev,
				"read %d from output pin %u<GPIO%u%u>, cache miss\n",
				b, pin_num, group, bit);
	}

	return (b);
}

/*
 * NB: state of an input pin cannot be cached, of course.
 * For an output we can either take the value from the cache if it's valid
 * or read the state from the hadrware and cache it.
 */
static bool
nct_read_pin(struct nct_softc *sc, uint32_t pin_num)
{
	uint8_t bit;
	uint8_t group;
	bool    val;

	if (nct_pin_is_input(sc, pin_num)) {
		return (nct_get_pin_reg(sc, REG_DAT, pin_num));
	}

	group = NCT_PIN_GRPNUM(sc, pin_num);
	bit   = NCT_PIN_BIT(sc, pin_num);

	if (GET_BIT(sc->cache.out_known[group], bit)) {
		val = GET_BIT(sc->cache.out[group], bit);

		NCT_VERBOSE_PRINTF(sc->dev,
			"read %d from output pin %u<GPIO%u%u>, cache hit\n",
			val, pin_num, group, bit);

		return (val);
	}

	val = nct_get_pin_reg(sc, REG_DAT, pin_num);
	sc->cache.out_known[group] |= 1 << bit;
	if (val)
		sc->cache.out[group] |= 1 << bit;
	else
		sc->cache.out[group] &= ~(1 << bit);
	return (val);
}

/* FIXME Incorret for NCT5585D and probably other chips. */
static uint8_t
nct_ppod_reg(struct nct_softc *sc, uint32_t pin_num)
{
	uint8_t group = NCT_PIN_GRPNUM(sc, pin_num);

	return (sc->grpmap[group]->ppod_reg);
}

/*
 * NB: PP/OD can be configured only via configuration registers.
 * Also, the registers are in a different logical device.
 * So, this is a special case.  No caching too.
 */
static void
nct_set_pin_opendrain(struct nct_softc *sc, uint32_t pin_num)
{
	uint8_t reg;
	uint8_t outcfg;

	reg = nct_ppod_reg(sc, pin_num);
	outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);
	outcfg |= NCT_PIN_BITMASK(pin_num);
	superio_ldn_write(sc->dev, 0xf, reg, outcfg);
}

static void
nct_set_pin_pushpull(struct nct_softc *sc, uint32_t pin_num)
{
	uint8_t reg;
	uint8_t outcfg;

	reg = nct_ppod_reg(sc, pin_num);
	outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);
	outcfg &= ~NCT_PIN_BITMASK(pin_num);
	superio_ldn_write(sc->dev, 0xf, reg, outcfg);
}

static bool
nct_pin_is_opendrain(struct nct_softc *sc, uint32_t pin_num)
{
	uint8_t reg;
	uint8_t outcfg;

	reg = nct_ppod_reg(sc, pin_num);
	outcfg = superio_ldn_read(sc->dev, NCT_PPOD_LDN, reg);
	return (outcfg & NCT_PIN_BITMASK(pin_num));
}

static struct nct_device *
nct_lookup_device(device_t dev)
{
	struct nct_device *nd;
	uint16_t           devid;
	int                i, extid;
	uint8_t            ldn;

	devid = superio_devid(dev);
	extid = superio_extid(dev);
	ldn = superio_get_ldn(dev);
	for (i = 0, nd = nct_devices; i < nitems(nct_devices); i++, nd++) {
		if (nd->devid != (nd->mask ? (devid & nd->mask) : devid))
			continue;
		if (nd->extid && (nd->extid != extid))
			continue;
		if (nd->ldn && (nd->ldn != ldn))
			continue;

		return (nd);
	}
	return (NULL);
}

static int
nct_probe(device_t dev)
{
	struct nct_device *nctdevp;
	uint8_t            ldn;

	ldn = superio_get_ldn(dev);

	if (superio_vendor(dev) != SUPERIO_VENDOR_NUVOTON) {
		NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not a Nuvoton device\n", ldn);
		return (ENXIO);
	}
	if (superio_get_type(dev) != SUPERIO_DEV_GPIO) {
		NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not a GPIO device\n", ldn);
		return (ENXIO);
	}

	nctdevp = nct_lookup_device(dev);
	if (nctdevp == NULL) {
		NCT_VERBOSE_PRINTF(dev, "ldn 0x%x not supported\n", ldn);
		return (ENXIO);
	}
	device_set_desc(dev, nctdevp->descr);
	return (BUS_PROBE_DEFAULT);
}

static void
nct_enable_gpios (device_t dev, struct nct_softc *sc)
{
	struct nct_gpio_group *gp;
	uint8_t v;
	int g;

	/* Enable GPIO groups */
	for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) {
		NCT_VERBOSE_PRINTF(dev,
			"GPIO%d: %d pins, enable with mask 0x%x via ldn 0x%x reg 0x%x\n",
			gp->grpnum, gp->npins, gp->enable_mask, gp->enable_ldn,
			gp->enable_reg);
		v = superio_ldn_read(dev, gp->enable_ldn, gp->enable_reg);
		v |= gp->enable_mask;
		superio_ldn_write(dev, gp->enable_ldn, gp->enable_reg, v);
	}
	return;
}

static int
nct_attach(device_t dev)
{
	struct nct_softc *sc;
	struct nct_gpio_group *gp;
	uint32_t pin_num;
	uint8_t v;
	int flags, i, g;

	sc          = device_get_softc(dev);
	sc->dev     = dev;
	sc->nctdevp = nct_lookup_device(dev);

	flags = 0;
	(void)resource_int_value(device_get_name(dev), device_get_unit(dev), "flags", &flags);

	if ((flags & NCT_PREFER_INDIRECT_CHANNEL) == 0) {
		uint16_t iobase;
		device_t dev_8;

		/*
		 * As strange as it may seem, I/O port base is configured in the
		 * Logical Device 8 which is primarily used for WDT, but also plays
		 * a role in GPIO configuration.
		 */
		iobase = 0;
		dev_8 = superio_find_dev(device_get_parent(dev), SUPERIO_DEV_WDT, 8);
		if (dev_8 != NULL)
			iobase = superio_get_iobase(dev_8);
		if (iobase != 0 && iobase != 0xffff) {
			int err;

			NCT_VERBOSE_PRINTF(dev, "iobase %#x\n", iobase);
			sc->curgrp = -1;
			sc->iorid = 0;
			err = bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid,
				iobase, 7); /* FIXME NCT6796D-E have 8 registers according to table 18.3. */
			if (err == 0) {
				sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
					&sc->iorid, RF_ACTIVE|RF_SHAREABLE);
				if (sc->iores == NULL) {
					device_printf(dev, "can't map i/o space, "
						"iobase=%#x\n", iobase);
				}
			} else {
				device_printf(dev,
					"failed to set io port resource at %#x\n", iobase);
			}
		}
	}
	NCT_VERBOSE_PRINTF(dev, "iores %p %s channel\n",
		sc->iores, (sc->iores ? "direct" : "indirect"));

	if (flags & NCT_NO_ENABLE) {
		NCT_VERBOSE_PRINTF(dev, "skipping enable.\n");
	} else {
		nct_enable_gpios(dev, sc);
			gp->grpnum, gp->npins, gp->enable_mask, gp->enable_ldn,
			gp->enable_reg);
		v = superio_ldn_read(dev, gp->enable_ldn, gp->enable_reg);
		v |= gp->enable_mask;
		superio_ldn_write(dev, gp->enable_ldn, gp->enable_reg, v);
	}

	GPIO_LOCK_INIT(sc);
	GPIO_LOCK(sc);

	pin_num   = 0;
	sc->npins = 0;
	for (g = 0, gp = sc->nctdevp->groups; g < sc->nctdevp->ngroups; g++, gp++) {

		sc->grpmap[gp->grpnum] = gp;

		if (flags & NCT_NO_ENABLE) {
			v = superio_ldn_read(dev, gp->enable_ldn, gp->enable_reg);
			if ((v & gp->enable_mask) == 0)
				continue;
		}

		/*
		 * Caching input values is meaningless as an input can be changed at any
		 * time by an external agent.  But outputs are controlled by this
		 * driver, so it can cache their state.  Also, the hardware remembers
		 * the output state of a pin when the pin is switched to input mode and
		 * then back to output mode.  So, the cache stays valid.
		 * The only problem is with pins that are in input mode at the attach
		 * time.  For them the output state is not known until it is set by the
		 * driver for the first time.
		 * 'out' and 'out_known' bits form a tri-state output cache:
		 * |-----+-----------+---------|
		 * | out | out_known | cache   |
		 * |-----+-----------+---------|
		 * |   X |         0 | invalid |
		 * |   0 |         1 |       0 |
		 * |   1 |         1 |       1 |
		 * |-----+-----------+---------|
		 */
		sc->cache.inv[gp->grpnum]       = nct_read_reg(sc, REG_INV, gp->grpnum);
		sc->cache.ior[gp->grpnum]       = nct_read_reg(sc, REG_IOR, gp->grpnum);
		sc->cache.out[gp->grpnum]       = nct_read_reg(sc, REG_DAT, gp->grpnum);
		sc->cache.out_known[gp->grpnum] = ~sc->cache.ior[gp->grpnum];

		sc->npins += gp->npins;
		for (i = 0; i < gp->npins; i++, pin_num++) {
			struct gpio_pin *pin;

			sc->pinmap[pin_num].group  = gp;
			sc->pinmap[pin_num].grpnum = gp->grpnum;
			sc->pinmap[pin_num].bit    = gp->pinbits[i];

			pin           = &sc->pins[pin_num];
			pin->gp_pin   = pin_num;
			pin->gp_caps  = gp->caps;
			pin->gp_flags = 0;

			snprintf(pin->gp_name, GPIOMAXNAME, "GPIO%u%u",
				gp->grpnum, gp->pinbits[i]);

			if (nct_pin_is_input(sc, pin_num))
				pin->gp_flags |= GPIO_PIN_INPUT;
			else
				pin->gp_flags |= GPIO_PIN_OUTPUT;

			if (nct_pin_is_opendrain(sc, pin_num))
				pin->gp_flags |= GPIO_PIN_OPENDRAIN;
			else
				pin->gp_flags |= GPIO_PIN_PUSHPULL;

			if (nct_pin_is_inverted(sc, pin_num))
				pin->gp_flags |= (GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
		}
	}
	NCT_VERBOSE_PRINTF(dev, "%d pins available\n", sc->npins);

	GPIO_UNLOCK(sc);

	sc->busdev = gpiobus_attach_bus(dev);
	if (sc->busdev == NULL) {
		device_printf(dev, "failed to attach to gpiobus\n");
		GPIO_LOCK_DESTROY(sc);
		return (ENXIO);
	}

	return (0);
}

static int
nct_detach(device_t dev)
{
	struct nct_softc *sc;

	sc = device_get_softc(dev);
	gpiobus_detach_bus(dev);

	if (sc->iores != NULL)
		bus_release_resource(dev, SYS_RES_IOPORT, sc->iorid, sc->iores);
	GPIO_ASSERT_UNLOCKED(sc);
	GPIO_LOCK_DESTROY(sc);

	return (0);
}

static device_t
nct_gpio_get_bus(device_t dev)
{
	struct nct_softc *sc;

	sc = device_get_softc(dev);

	return (sc->busdev);
}

static int
nct_gpio_pin_max(device_t dev, int *maxpin)
{
	struct nct_softc *sc;

	sc      = device_get_softc(dev);




/*-
 * SPDX-License-Identifier: BSD-2-Clause
 *
 * Copyright (c) 2016-2022 Stormshield
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

#include <sys/cdefs.h>
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <sys/watchdog.h>

#include <dev/superio/superio.h>

#include <machine/bus.h>
#include <machine/resource.h>

#define NCTHWM_FAN_MAX                 5

#define NCTHWM_BANK_SELECT 0x4e
#define NCTHWM_VENDOR_ID   0x4f

#define NCTHWM_VERBOSE_PRINTF(dev, ...)         \
	do {                                        \
		if (__predict_false(bootverbose))       \
			device_printf(dev, __VA_ARGS__);    \
	} while (0)

struct ncthwm_softc {
	device_t              dev;
	struct ncthwm_device *nctdevp;
	struct resource      *iores;
	int                   iorid;
};

struct ncthwm_fan_info
{
	const char *name;
	uint8_t     low_byte_offset;
	uint8_t     high_byte_offset;
};

struct ncthwm_device {
	uint16_t                 devid;
	uint16_t		 mask;
	const char              *descr;
	uint8_t                  base_offset;
	uint8_t                  fan_bank;
	uint8_t                  fan_count;
	struct ncthwm_fan_info   fan_info[NCTHWM_FAN_MAX];
} ncthwm_devices[] = {
	{
		.devid       = 0xc562,
		.descr       = "HWM on Nuvoton NCT6779D",
		.base_offset = 5,
		.fan_bank    = 4,
		.fan_count   = 5,
		.fan_info = {
			{ .name = "SYSFAN",  .low_byte_offset = 0xc1, .high_byte_offset = 0xc0 },
			{ .name = "CPUFAN",  .low_byte_offset = 0xc3, .high_byte_offset = 0xc2 },
			{ .name = "AUXFAN0", .low_byte_offset = 0xc5, .high_byte_offset = 0xc4 },
			{ .name = "AUXFAN1", .low_byte_offset = 0xc7, .high_byte_offset = 0xc6 },
			{ .name = "AUXFAN2", .low_byte_offset = 0xc9, .high_byte_offset = 0xc8 },
		},
	}, {
		.devid       = 0xd42a,
		.descr       = "HWM on Nuvoton NCT6796D-E",
		.base_offset = 5,
		.fan_bank    = 4,
		.fan_count   = 5,
		.fan_info = {
			{ .name = "SYSFAN",  .low_byte_offset = 0xc1, .high_byte_offset = 0xc0 },
			{ .name = "CPUFAN",  .low_byte_offset = 0xc3, .high_byte_offset = 0xc2 },
			{ .name = "AUXFAN0", .low_byte_offset = 0xc5, .high_byte_offset = 0xc4 },
			{ .name = "AUXFAN1", .low_byte_offset = 0xc7, .high_byte_offset = 0xc6 },
			{ .name = "AUXFAN2", .low_byte_offset = 0xc9, .high_byte_offset = 0xc8 },
		},
	}, {
		.devid       = 0xd284,
		.mask	     = 0xffdf,
		.descr       = "HWM on Nuvoton NCT6122D/NCT6126D",
		.base_offset = 5,
		.fan_bank    = 0,
		.fan_count   = 5,
		.fan_info = {
			{ .name = "SYSFAN",  .low_byte_offset = 0x31, .high_byte_offset = 0x30 },
			{ .name = "CPUFAN",  .low_byte_offset = 0x33, .high_byte_offset = 0x32 },
			{ .name = "AUXFAN0", .low_byte_offset = 0x35, .high_byte_offset = 0x34 },
			{ .name = "AUXFAN1", .low_byte_offset = 0x37, .high_byte_offset = 0x36 },
			{ .name = "AUXFAN2", .low_byte_offset = 0x39, .high_byte_offset = 0x38 },
		},
	}
};

static struct ncthwm_device *
ncthwm_lookup_device(device_t dev)
{
	struct ncthwm_device *d = ncthwm_devices;
	uint16_t devid;

	devid = superio_devid(dev);
	for (int i = 0; i < nitems(ncthwm_devices); i++, d++) {
		if (d->devid != (d->mask ? (devid & d->mask) : devid))
			continue;

		return (d);
	}
	return (NULL);
}

static void
ncthwm_write(struct ncthwm_softc *sc, uint8_t reg, uint8_t val)
{
	bus_write_1(sc->iores, 0, reg);
	bus_write_1(sc->iores, 1, val);
}

static uint8_t
ncthwm_read(struct ncthwm_softc *sc, uint8_t reg)
{
	bus_write_1(sc->iores, 0, reg);
	return (bus_read_1(sc->iores, 1));
}

static int
ncthwm_query_fan_speed(SYSCTL_HANDLER_ARGS)
{
	struct ncthwm_softc    *sc;
	struct ncthwm_fan_info *fan;
	uint16_t                val;

	sc = arg1;
	if (sc == NULL)
		return (EINVAL);

	KASSERT(sc->nctdevp != NULL, ("Unreachable"));

	if (sc->nctdevp->fan_count <= arg2)
		return (EINVAL);
	fan = &sc->nctdevp->fan_info[arg2];

	KASSERT(sc->iores != NULL, ("Unreachable"));

	ncthwm_write(sc, NCTHWM_BANK_SELECT, sc->nctdevp->fan_bank);
	val  = ncthwm_read(sc, fan->high_byte_offset) << 8;
	val |= ncthwm_read(sc, fan->low_byte_offset);

	NCTHWM_VERBOSE_PRINTF(sc->dev, "%s: read %u from bank %u offset 0x%x-0x%x\n",
		fan->name, val, sc->nctdevp->fan_bank, fan->high_byte_offset, fan->low_byte_offset);

	return (sysctl_handle_16(oidp, &val, 0, req));
}

static int
ncthwm_probe(device_t dev)
{
	struct ncthwm_device *nctdevp;
	uint8_t               ldn;

	ldn = superio_get_ldn(dev);

	if (superio_vendor(dev) != SUPERIO_VENDOR_NUVOTON) {
		NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not a Nuvoton device\n", ldn);
		return (ENXIO);
	}
	if (superio_get_type(dev) != SUPERIO_DEV_HWM) {
		NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not a HWM device\n", ldn);
		return (ENXIO);
	}

	nctdevp = ncthwm_lookup_device(dev);
	if (nctdevp == NULL) {
		NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not supported\n", ldn);
		return (ENXIO);
	}
	device_set_desc(dev, nctdevp->descr);
	return (BUS_PROBE_DEFAULT);
}

static int
ncthwm_attach(device_t dev)
{
	struct ncthwm_softc *sc;
	int                  i;
	uint16_t             iobase;

	sc      = device_get_softc(dev);
	sc->dev = dev;

	sc->nctdevp = ncthwm_lookup_device(dev);
	if (sc->nctdevp == NULL) {
		device_printf(dev, "device not supported\n");
		return (ENXIO);
	}

	iobase    = superio_get_iobase(dev) + sc->nctdevp->base_offset;
	sc->iorid = 0;
	if (bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid, iobase, 2) != 0) {
		device_printf(dev, "failed to set I/O port resource at 0x%x\n", iobase);
		return (ENXIO);
	}
	sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
		&sc->iorid, RF_ACTIVE);
	if (sc->iores == NULL) {
		device_printf(dev, "can't map I/O space at 0x%x\n", iobase);




	bus_write_1(res, 0, port == 0x2e ? 0x55 : 0xaa);
}

static void
ite_conf_exit(struct resource* res, uint16_t port)
{
	sio_write(res, 0x02, 0x02);
}

static const struct sio_conf_methods ite_conf_methods = {
	.enter = ite_conf_enter,
	.exit = ite_conf_exit,
	.vendor = SUPERIO_VENDOR_ITE
};

static void
nvt_conf_enter(struct resource* res, uint16_t port)
{
	bus_write_1(res, 0, 0x87);
	bus_write_1(res, 0, 0x87);
}

static void
nvt_conf_exit(struct resource* res, uint16_t port)
{
	bus_write_1(res, 0, 0xaa);
}

static const struct sio_conf_methods nvt_conf_methods = {
	.enter = nvt_conf_enter,
	.exit = nvt_conf_exit,
	.vendor = SUPERIO_VENDOR_NUVOTON
};

static void
fintek_conf_enter(struct resource* res, uint16_t port)
{
	bus_write_1(res, 0, 0x87);
	bus_write_1(res, 0, 0x87);
}

static void
fintek_conf_exit(struct resource* res, uint16_t port)
{
	bus_write_1(res, 0, 0xaa);
}

static const struct sio_conf_methods fintek_conf_methods = {
	.enter = fintek_conf_enter,
	.exit = fintek_conf_exit,
	.vendor = SUPERIO_VENDOR_FINTEK
};

static const struct sio_conf_methods * const methods_table[] = {
	&ite_conf_methods,
	&nvt_conf_methods,
	&fintek_conf_methods,
	NULL
};

static const uint16_t ports_table[] = {
	0x2e, 0x4e, 0
};

const struct sio_device ite_devices[] = {
	{ .ldn = 4, .type = SUPERIO_DEV_HWM },
	{ .ldn = 7, .type = SUPERIO_DEV_WDT },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device w83627_devices[] = {
	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device nvt_devices[] = {
	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device nct5104_devices[] = {
	{ .ldn = 7, .type = SUPERIO_DEV_GPIO },
	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
	{ .ldn = 15, .type = SUPERIO_DEV_GPIO },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device nct5585_devices[] = {
	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device nct611x_devices[] = {
	{ .ldn = 0x7, .type = SUPERIO_DEV_GPIO },
	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device nct612x_devices[] = {
	{ .ldn = 0x7, .type = SUPERIO_DEV_GPIO },
	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
	{ .ldn = 0x9, .type = SUPERIO_DEV_GPIO },
	{ .ldn = 0xb, .type = SUPERIO_DEV_HWM },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device nct67xx_devices[] = {
	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
	{ .ldn = 0x9, .type = SUPERIO_DEV_GPIO },
	{ .ldn = 0xb, .type = SUPERIO_DEV_HWM },
	{ .type = SUPERIO_DEV_NONE },
};

const struct sio_device fintek_devices[] = {
	{ .ldn = 6, .type = SUPERIO_DEV_GPIO },
	{ .ldn = 7, .type = SUPERIO_DEV_WDT },
	{ .type = SUPERIO_DEV_NONE },
};

static const struct {
	superio_vendor_t	vendor;
	uint16_t		devid;
	uint16_t		mask;
	int			extid; /* Extra ID: used to handle conflicting devid. */
	const char		*descr;
	const struct sio_device	*devices;
} superio_table[] = {
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8613,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8712,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8716,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8718,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8720,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8721,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8726,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8728,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8771,
		.devices = ite_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x1061, .mask = 0x00,
		.descr	= "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. A)",
		.devices = nct5104_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5200, .mask = 0xff,
		.descr = "Winbond 83627HF/F/HG/G",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5900, .mask = 0xff,
		.descr = "Winbond 83627S",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6000, .mask = 0xff,
		.descr = "Winbond 83697HF",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6800, .mask = 0xff,
		.descr = "Winbond 83697UG",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x7000, .mask = 0xff,
		.descr = "Winbond 83637HF",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8200, .mask = 0xff,
		.descr = "Winbond 83627THF",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8500, .mask = 0xff,
		.descr = "Winbond 83687THF",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8800, .mask = 0xff,
		.descr = "Winbond 83627EHF",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa000, .mask = 0xff,
		.descr = "Winbond 83627DHG",
		.devices = w83627_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa200, .mask = 0xff,
		.descr = "Winbond 83627UHG",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa500, .mask = 0xff,
		.descr = "Winbond 83667HG",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb000, .mask = 0xff,
		.descr = "Winbond 83627DHG-P",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb300, .mask = 0xff,
		.descr = "Winbond 83667HG-B",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb400, .mask = 0xff,
		.descr = "Nuvoton NCT6775",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc300, .mask = 0xff,
		.descr = "Nuvoton NCT6776",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc400, .mask = 0xff,
		.descr = "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. B+)",
		.devices = nct5104_devices,
	},
	{
		.vendor  = SUPERIO_VENDOR_NUVOTON, .devid = 0xc500, .mask = 0xff,
		.descr   = "Nuvoton NCT6779D",
		.devices = nct67xx_devices,
	},
	{
		.vendor  = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 1,
		.descr   = "Nuvoton NCT6796D-E",
		.devices = nct67xx_devices,
	},
	{
		.vendor  = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 2,
		.descr   = "Nuvoton NCT5585D",
		.devices = nct5585_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc800, .mask = 0xff,
		.descr = "Nuvoton NCT6791",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc900, .mask = 0xff,
		.descr = "Nuvoton NCT6792",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd100, .mask = 0xff,
		.descr = "Nuvoton NCT6793",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd282,
		.descr = "Nuvoton NCT6112D",	// 2 UART
		.devices = nct611x_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd280, .mask = 0x0003,
		.descr = "Nuvoton NCT6114D/NCT6116D",	// 4/6 UART - 0xd281? 0xd283?
		.devices = nct611x_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd2A4,
		.descr = "Nuvoton NCT6122D",	// 2 UART
		.devices = nct612x_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd284,
		.descr = "Nuvoton NCT6126D",	// 6 UART
		.devices = nct612x_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd300, .mask = 0xff,
		.descr = "Nuvoton NCT6795",
		.devices = nvt_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x1210, .mask = 0xff,
		.descr = "Fintek F81803",
		.devices = fintek_devices,
	},
	{
		.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x0704,
		.descr = "Fintek F81865",
		.devices = fintek_devices,
	},
	{ 0, 0 }
};

static const char *
devtype_to_str(superio_dev_type_t type)
{
	switch (type) {
	case SUPERIO_DEV_NONE:
		return ("none");
	case SUPERIO_DEV_HWM:
		return ("HWM");
	case SUPERIO_DEV_WDT:
		return ("WDT");
	case SUPERIO_DEV_GPIO:
		return ("GPIO");
	case SUPERIO_DEV_MAX:
		return ("invalid");
	}
	return ("invalid");
}

static int
superio_detect(device_t dev, bool claim, struct siosc *sc)
{
	struct resource *res;
	rman_res_t port;
	rman_res_t count;
	uint16_t devid;
	uint8_t revid;
	int error;
	int rid;
	int i, m;
	int prefer;

	error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, &count);
	if (error != 0)
		return (error);
	if (port > UINT16_MAX || count < NUMPORTS) {
		device_printf(dev, "unexpected I/O range size\n");
		return (ENXIO);
	}

	/*
	 * Make a temporary resource reservation for hardware probing.
	 * If we can't get the resources we need then
	 * we need to abort.  Possibly this indicates
	 * the resources were used by another device
	 * in which case the probe would have failed anyhow.
	 */
	rid = 0;
	res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
	if (res == NULL) {
		if (claim)
			device_printf(dev, "failed to allocate I/O resource\n");
		return (ENXIO);
	}

	prefer = 0;
	resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer", &prefer);
	if (bootverbose && prefer > 0)
		device_printf(dev, "prefer extid %d\n", prefer);

	for (m = 0; methods_table[m] != NULL; m++) {
		methods_table[m]->enter(res, port);
		if (methods_table[m]->vendor == SUPERIO_VENDOR_ITE) {
			devid = sio_readw(res, 0x20);
			revid = sio_read(res, 0x22);
		} else if (methods_table[m]->vendor == SUPERIO_VENDOR_NUVOTON) {
			devid = sio_read(res, 0x20);
			revid = sio_read(res, 0x21);
			devid = (devid << 8) | revid;
		} else if (methods_table[m]->vendor == SUPERIO_VENDOR_FINTEK) {
			devid = sio_read(res, 0x20);
			revid = sio_read(res, 0x21);
			devid = (devid << 8) | revid;
		} else {
			continue;
		}
		methods_table[m]->exit(res, port);
		for (i = 0; superio_table[i].vendor != 0; i++) {
			uint16_t mask;

			mask = superio_table[i].mask;
			if (superio_table[i].vendor !=

Return to bug 282738

Lines 1-213 Link Here

(-)b/sys/dev/ncthwm/ncthwm.c (-4 / +21 lines)
1	/*-	1	/*-
2	* SPDX-License-Identifier: BSD-2-Clause	2	* SPDX-License-Identifier: BSD-2-Clause
3	*	3	*
4	* Copyright (c) 2016-2022 Stormshield	4	* Copyright (c) 2016-2022 Stormshield
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	* 1. Redistributions of source code must retain the above copyright	9	* 1. Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* 2. Redistributions in binary form must reproduce the above copyright	11	* 2. Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	*	14	*
15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND	15	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE	16	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE	17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE	18	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL	19	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS	20	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)	21	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT	22	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY	23	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF	24	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25	* SUCH DAMAGE.	25	* SUCH DAMAGE.
26	*/	26	*/
27		27
28	#include <sys/cdefs.h>	28	#include <sys/cdefs.h>
29	#include <sys/param.h>	29	#include <sys/param.h>
30	#include <sys/systm.h>	30	#include <sys/systm.h>
31	#include <sys/bus.h>	31	#include <sys/bus.h>
32	#include <sys/kernel.h>	32	#include <sys/kernel.h>
33	#include <sys/module.h>	33	#include <sys/module.h>
34	#include <sys/rman.h>	34	#include <sys/rman.h>
35	#include <sys/sysctl.h>	35	#include <sys/sysctl.h>
36	#include <sys/watchdog.h>	36	#include <sys/watchdog.h>
37		37
38	#include <dev/superio/superio.h>	38	#include <dev/superio/superio.h>
39		39
40	#include <machine/bus.h>	40	#include <machine/bus.h>
41	#include <machine/resource.h>	41	#include <machine/resource.h>
42		42
43	#define NCTHWM_FAN_MAX 5	43	#define NCTHWM_FAN_MAX 5
44		44
45	#define NCTHWM_BANK_SELECT 0x4e	45	#define NCTHWM_BANK_SELECT 0x4e
46	#define NCTHWM_VENDOR_ID 0x4f	46	#define NCTHWM_VENDOR_ID 0x4f
47		47
48	#define NCTHWM_VERBOSE_PRINTF(dev, ...) \	48	#define NCTHWM_VERBOSE_PRINTF(dev, ...) \
49	do { \	49	do { \
50	if (__predict_false(bootverbose)) \	50	if (__predict_false(bootverbose)) \
51	device_printf(dev, __VA_ARGS__); \	51	device_printf(dev, __VA_ARGS__); \
52	} while (0)	52	} while (0)
53		53
54	struct ncthwm_softc {	54	struct ncthwm_softc {
55	device_t dev;	55	device_t dev;
56	struct ncthwm_device *nctdevp;	56	struct ncthwm_device *nctdevp;
57	struct resource *iores;	57	struct resource *iores;
58	int iorid;	58	int iorid;
59	};	59	};
60		60
61	struct ncthwm_fan_info	61	struct ncthwm_fan_info
62	{	62	{
63	const char *name;	63	const char *name;
64	uint8_t low_byte_offset;	64	uint8_t low_byte_offset;
65	uint8_t high_byte_offset;	65	uint8_t high_byte_offset;
66	};	66	};
67		67
68	struct ncthwm_device {	68	struct ncthwm_device {
69	uint16_t devid;	69	uint16_t devid;
		70	uint16_t mask;
70	const char *descr;	71	const char *descr;
71	uint8_t base_offset;	72	uint8_t base_offset;
72	uint8_t fan_bank;	73	uint8_t fan_bank;
73	uint8_t fan_count;	74	uint8_t fan_count;
74	struct ncthwm_fan_info fan_info[NCTHWM_FAN_MAX];	75	struct ncthwm_fan_info fan_info[NCTHWM_FAN_MAX];
75	} ncthwm_devices[] = {	76	} ncthwm_devices[] = {
76	{	77	{
77	.devid = 0xc562,	78	.devid = 0xc562,
78	.descr = "HWM on Nuvoton NCT6779D",	79	.descr = "HWM on Nuvoton NCT6779D",
79	.base_offset = 5,	80	.base_offset = 5,
80	.fan_bank = 4,	81	.fan_bank = 4,
81	.fan_count = 5,	82	.fan_count = 5,
82	.fan_info = {	83	.fan_info = {
83	{ .name = "SYSFAN", .low_byte_offset = 0xc1, .high_byte_offset = 0xc0 },	84	{ .name = "SYSFAN", .low_byte_offset = 0xc1, .high_byte_offset = 0xc0 },
84	{ .name = "CPUFAN", .low_byte_offset = 0xc3, .high_byte_offset = 0xc2 },	85	{ .name = "CPUFAN", .low_byte_offset = 0xc3, .high_byte_offset = 0xc2 },
85	{ .name = "AUXFAN0", .low_byte_offset = 0xc5, .high_byte_offset = 0xc4 },	86	{ .name = "AUXFAN0", .low_byte_offset = 0xc5, .high_byte_offset = 0xc4 },
86	{ .name = "AUXFAN1", .low_byte_offset = 0xc7, .high_byte_offset = 0xc6 },	87	{ .name = "AUXFAN1", .low_byte_offset = 0xc7, .high_byte_offset = 0xc6 },
87	{ .name = "AUXFAN2", .low_byte_offset = 0xc9, .high_byte_offset = 0xc8 },	88	{ .name = "AUXFAN2", .low_byte_offset = 0xc9, .high_byte_offset = 0xc8 },
88	},	89	},
89	}, {	90	}, {
90	.devid = 0xd42a,	91	.devid = 0xd42a,
91	.descr = "HWM on Nuvoton NCT6796D-E",	92	.descr = "HWM on Nuvoton NCT6796D-E",
92	.base_offset = 5,	93	.base_offset = 5,
93	.fan_bank = 4,	94	.fan_bank = 4,
94	.fan_count = 5,	95	.fan_count = 5,
95	.fan_info = {	96	.fan_info = {
96	{ .name = "SYSFAN", .low_byte_offset = 0xc1, .high_byte_offset = 0xc0 },	97	{ .name = "SYSFAN", .low_byte_offset = 0xc1, .high_byte_offset = 0xc0 },
97	{ .name = "CPUFAN", .low_byte_offset = 0xc3, .high_byte_offset = 0xc2 },	98	{ .name = "CPUFAN", .low_byte_offset = 0xc3, .high_byte_offset = 0xc2 },
98	{ .name = "AUXFAN0", .low_byte_offset = 0xc5, .high_byte_offset = 0xc4 },	99	{ .name = "AUXFAN0", .low_byte_offset = 0xc5, .high_byte_offset = 0xc4 },
99	{ .name = "AUXFAN1", .low_byte_offset = 0xc7, .high_byte_offset = 0xc6 },	100	{ .name = "AUXFAN1", .low_byte_offset = 0xc7, .high_byte_offset = 0xc6 },
100	{ .name = "AUXFAN2", .low_byte_offset = 0xc9, .high_byte_offset = 0xc8 },	101	{ .name = "AUXFAN2", .low_byte_offset = 0xc9, .high_byte_offset = 0xc8 },
101	},	102	},
		103	}, {
		104	.devid = 0xd284,
		105	.mask = 0xffdf,
		106	.descr = "HWM on Nuvoton NCT6122D/NCT6126D",
		107	.base_offset = 5,
		108	.fan_bank = 0,
		109	.fan_count = 5,
		110	.fan_info = {
		111	{ .name = "SYSFAN", .low_byte_offset = 0x31, .high_byte_offset = 0x30 },
		112	{ .name = "CPUFAN", .low_byte_offset = 0x33, .high_byte_offset = 0x32 },
		113	{ .name = "AUXFAN0", .low_byte_offset = 0x35, .high_byte_offset = 0x34 },
		114	{ .name = "AUXFAN1", .low_byte_offset = 0x37, .high_byte_offset = 0x36 },
		115	{ .name = "AUXFAN2", .low_byte_offset = 0x39, .high_byte_offset = 0x38 },
		116	},
102	}	117	}
103	};	118	};
104		119
105	static struct ncthwm_device *	120	static struct ncthwm_device *
106	ncthwm_lookup_device(device_t dev)	121	ncthwm_lookup_device(device_t dev)
107	{	122	{
108	int i;	123	struct ncthwm_device *d = ncthwm_devices;
109	uint16_t devid;	124	uint16_t devid;
110		125
111	devid = superio_devid(dev);	126	devid = superio_devid(dev);
112	for (i = 0; i < nitems(ncthwm_devices); i++) {	127	for (int i = 0; i < nitems(ncthwm_devices); i++, d++) {
113	if (devid == ncthwm_devices[i].devid)	128	if (d->devid != (d->mask ? (devid & d->mask) : devid))
114	return (ncthwm_devices + i);	129	continue;
		130
		131	return (d);
115	}	132	}
116	return (NULL);	133	return (NULL);
117	}	134	}
118		135
119	static void	136	static void
120	ncthwm_write(struct ncthwm_softc *sc, uint8_t reg, uint8_t val)	137	ncthwm_write(struct ncthwm_softc *sc, uint8_t reg, uint8_t val)
121	{	138	{
122	bus_write_1(sc->iores, 0, reg);	139	bus_write_1(sc->iores, 0, reg);
123	bus_write_1(sc->iores, 1, val);	140	bus_write_1(sc->iores, 1, val);
124	}	141	}
125		142
126	static uint8_t	143	static uint8_t
127	ncthwm_read(struct ncthwm_softc *sc, uint8_t reg)	144	ncthwm_read(struct ncthwm_softc *sc, uint8_t reg)
128	{	145	{
129	bus_write_1(sc->iores, 0, reg);	146	bus_write_1(sc->iores, 0, reg);
130	return (bus_read_1(sc->iores, 1));	147	return (bus_read_1(sc->iores, 1));
131	}	148	}
132		149
133	static int	150	static int
134	ncthwm_query_fan_speed(SYSCTL_HANDLER_ARGS)	151	ncthwm_query_fan_speed(SYSCTL_HANDLER_ARGS)
135	{	152	{
136	struct ncthwm_softc *sc;	153	struct ncthwm_softc *sc;
137	struct ncthwm_fan_info *fan;	154	struct ncthwm_fan_info *fan;
138	uint16_t val;	155	uint16_t val;
139		156
140	sc = arg1;	157	sc = arg1;
141	if (sc == NULL)	158	if (sc == NULL)
142	return (EINVAL);	159	return (EINVAL);
143		160
144	KASSERT(sc->nctdevp != NULL, ("Unreachable"));	161	KASSERT(sc->nctdevp != NULL, ("Unreachable"));
145		162
146	if (sc->nctdevp->fan_count <= arg2)	163	if (sc->nctdevp->fan_count <= arg2)
147	return (EINVAL);	164	return (EINVAL);
148	fan = &sc->nctdevp->fan_info[arg2];	165	fan = &sc->nctdevp->fan_info[arg2];
149		166
150	KASSERT(sc->iores != NULL, ("Unreachable"));	167	KASSERT(sc->iores != NULL, ("Unreachable"));
151		168
152	ncthwm_write(sc, NCTHWM_BANK_SELECT, sc->nctdevp->fan_bank);	169	ncthwm_write(sc, NCTHWM_BANK_SELECT, sc->nctdevp->fan_bank);
153	val = ncthwm_read(sc, fan->high_byte_offset) << 8;	170	val = ncthwm_read(sc, fan->high_byte_offset) << 8;
154	val \|= ncthwm_read(sc, fan->low_byte_offset);	171	val \|= ncthwm_read(sc, fan->low_byte_offset);
155		172
156	NCTHWM_VERBOSE_PRINTF(sc->dev, "%s: read %u from bank %u offset 0x%x-0x%x\n",	173	NCTHWM_VERBOSE_PRINTF(sc->dev, "%s: read %u from bank %u offset 0x%x-0x%x\n",
157	fan->name, val, sc->nctdevp->fan_bank, fan->high_byte_offset, fan->low_byte_offset);	174	fan->name, val, sc->nctdevp->fan_bank, fan->high_byte_offset, fan->low_byte_offset);
158		175
159	return (sysctl_handle_16(oidp, &val, 0, req));	176	return (sysctl_handle_16(oidp, &val, 0, req));
160	}	177	}
161		178
162	static int	179	static int
163	ncthwm_probe(device_t dev)	180	ncthwm_probe(device_t dev)
164	{	181	{
165	struct ncthwm_device *nctdevp;	182	struct ncthwm_device *nctdevp;
166	uint8_t ldn;	183	uint8_t ldn;
167		184
168	ldn = superio_get_ldn(dev);	185	ldn = superio_get_ldn(dev);
169		186
170	if (superio_vendor(dev) != SUPERIO_VENDOR_NUVOTON) {	187	if (superio_vendor(dev) != SUPERIO_VENDOR_NUVOTON) {
171	NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not a Nuvoton device\n", ldn);	188	NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not a Nuvoton device\n", ldn);
172	return (ENXIO);	189	return (ENXIO);
173	}	190	}
174	if (superio_get_type(dev) != SUPERIO_DEV_HWM) {	191	if (superio_get_type(dev) != SUPERIO_DEV_HWM) {
175	NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not a HWM device\n", ldn);	192	NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not a HWM device\n", ldn);
176	return (ENXIO);	193	return (ENXIO);
177	}	194	}
178		195
179	nctdevp = ncthwm_lookup_device(dev);	196	nctdevp = ncthwm_lookup_device(dev);
180	if (nctdevp == NULL) {	197	if (nctdevp == NULL) {
181	NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not supported\n", ldn);	198	NCTHWM_VERBOSE_PRINTF(dev, "ldn 0x%x not supported\n", ldn);
182	return (ENXIO);	199	return (ENXIO);
183	}	200	}
184	device_set_desc(dev, nctdevp->descr);	201	device_set_desc(dev, nctdevp->descr);
185	return (BUS_PROBE_DEFAULT);	202	return (BUS_PROBE_DEFAULT);
186	}	203	}
187		204
188	static int	205	static int
189	ncthwm_attach(device_t dev)	206	ncthwm_attach(device_t dev)
190	{	207	{
191	struct ncthwm_softc *sc;	208	struct ncthwm_softc *sc;
192	int i;	209	int i;
193	uint16_t iobase;	210	uint16_t iobase;
194		211
195	sc = device_get_softc(dev);	212	sc = device_get_softc(dev);
196	sc->dev = dev;	213	sc->dev = dev;
197		214
198	sc->nctdevp = ncthwm_lookup_device(dev);	215	sc->nctdevp = ncthwm_lookup_device(dev);
199	if (sc->nctdevp == NULL) {	216	if (sc->nctdevp == NULL) {
200	device_printf(dev, "device not supported\n");	217	device_printf(dev, "device not supported\n");
201	return (ENXIO);	218	return (ENXIO);
202	}	219	}
203		220
204	iobase = superio_get_iobase(dev) + sc->nctdevp->base_offset;	221	iobase = superio_get_iobase(dev) + sc->nctdevp->base_offset;
205	sc->iorid = 0;	222	sc->iorid = 0;
206	if (bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid, iobase, 2) != 0) {	223	if (bus_set_resource(dev, SYS_RES_IOPORT, sc->iorid, iobase, 2) != 0) {
207	device_printf(dev, "failed to set I/O port resource at 0x%x\n", iobase);	224	device_printf(dev, "failed to set I/O port resource at 0x%x\n", iobase);
208	return (ENXIO);	225	return (ENXIO);
209	}	226	}
210	sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,	227	sc->iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
211	&sc->iorid, RF_ACTIVE);	228	&sc->iorid, RF_ACTIVE);
212	if (sc->iores == NULL) {	229	if (sc->iores == NULL) {
213	device_printf(dev, "can't map I/O space at 0x%x\n", iobase);	230	device_printf(dev, "can't map I/O space at 0x%x\n", iobase);

Lines 200-574 ite_conf_enter(struct resource* res, uint16_t port) Link Here

(-)b/sys/dev/superio/superio.c (-2 / +25 lines)
200	bus_write_1(res, 0, port == 0x2e ? 0x55 : 0xaa);	200	bus_write_1(res, 0, port == 0x2e ? 0x55 : 0xaa);
201	}	201	}
202		202
203	static void	203	static void
204	ite_conf_exit(struct resource* res, uint16_t port)	204	ite_conf_exit(struct resource* res, uint16_t port)
205	{	205	{
206	sio_write(res, 0x02, 0x02);	206	sio_write(res, 0x02, 0x02);
207	}	207	}
208		208
209	static const struct sio_conf_methods ite_conf_methods = {	209	static const struct sio_conf_methods ite_conf_methods = {
210	.enter = ite_conf_enter,	210	.enter = ite_conf_enter,
211	.exit = ite_conf_exit,	211	.exit = ite_conf_exit,
212	.vendor = SUPERIO_VENDOR_ITE	212	.vendor = SUPERIO_VENDOR_ITE
213	};	213	};
214		214
215	static void	215	static void
216	nvt_conf_enter(struct resource* res, uint16_t port)	216	nvt_conf_enter(struct resource* res, uint16_t port)
217	{	217	{
218	bus_write_1(res, 0, 0x87);	218	bus_write_1(res, 0, 0x87);
219	bus_write_1(res, 0, 0x87);	219	bus_write_1(res, 0, 0x87);
220	}	220	}
221		221
222	static void	222	static void
223	nvt_conf_exit(struct resource* res, uint16_t port)	223	nvt_conf_exit(struct resource* res, uint16_t port)
224	{	224	{
225	bus_write_1(res, 0, 0xaa);	225	bus_write_1(res, 0, 0xaa);
226	}	226	}
227		227
228	static const struct sio_conf_methods nvt_conf_methods = {	228	static const struct sio_conf_methods nvt_conf_methods = {
229	.enter = nvt_conf_enter,	229	.enter = nvt_conf_enter,
230	.exit = nvt_conf_exit,	230	.exit = nvt_conf_exit,
231	.vendor = SUPERIO_VENDOR_NUVOTON	231	.vendor = SUPERIO_VENDOR_NUVOTON
232	};	232	};
233		233
234	static void	234	static void
235	fintek_conf_enter(struct resource* res, uint16_t port)	235	fintek_conf_enter(struct resource* res, uint16_t port)
236	{	236	{
237	bus_write_1(res, 0, 0x87);	237	bus_write_1(res, 0, 0x87);
238	bus_write_1(res, 0, 0x87);	238	bus_write_1(res, 0, 0x87);
239	}	239	}
240		240
241	static void	241	static void
242	fintek_conf_exit(struct resource* res, uint16_t port)	242	fintek_conf_exit(struct resource* res, uint16_t port)
243	{	243	{
244	bus_write_1(res, 0, 0xaa);	244	bus_write_1(res, 0, 0xaa);
245	}	245	}
246		246
247	static const struct sio_conf_methods fintek_conf_methods = {	247	static const struct sio_conf_methods fintek_conf_methods = {
248	.enter = fintek_conf_enter,	248	.enter = fintek_conf_enter,
249	.exit = fintek_conf_exit,	249	.exit = fintek_conf_exit,
250	.vendor = SUPERIO_VENDOR_FINTEK	250	.vendor = SUPERIO_VENDOR_FINTEK
251	};	251	};
252		252
253	static const struct sio_conf_methods * const methods_table[] = {	253	static const struct sio_conf_methods * const methods_table[] = {
254	&ite_conf_methods,	254	&ite_conf_methods,
255	&nvt_conf_methods,	255	&nvt_conf_methods,
256	&fintek_conf_methods,	256	&fintek_conf_methods,
257	NULL	257	NULL
258	};	258	};
259		259
260	static const uint16_t ports_table[] = {	260	static const uint16_t ports_table[] = {
261	0x2e, 0x4e, 0	261	0x2e, 0x4e, 0
262	};	262	};
263		263
264	const struct sio_device ite_devices[] = {	264	const struct sio_device ite_devices[] = {
265	{ .ldn = 4, .type = SUPERIO_DEV_HWM },	265	{ .ldn = 4, .type = SUPERIO_DEV_HWM },
266	{ .ldn = 7, .type = SUPERIO_DEV_WDT },	266	{ .ldn = 7, .type = SUPERIO_DEV_WDT },
267	{ .type = SUPERIO_DEV_NONE },	267	{ .type = SUPERIO_DEV_NONE },
268	};	268	};
269		269
270	const struct sio_device w83627_devices[] = {	270	const struct sio_device w83627_devices[] = {
271	{ .ldn = 8, .type = SUPERIO_DEV_WDT },	271	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
272	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },	272	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },
273	{ .type = SUPERIO_DEV_NONE },	273	{ .type = SUPERIO_DEV_NONE },
274	};	274	};
275		275
276	const struct sio_device nvt_devices[] = {	276	const struct sio_device nvt_devices[] = {
277	{ .ldn = 8, .type = SUPERIO_DEV_WDT },	277	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
278	{ .type = SUPERIO_DEV_NONE },	278	{ .type = SUPERIO_DEV_NONE },
279	};	279	};
280		280
281	const struct sio_device nct5104_devices[] = {	281	const struct sio_device nct5104_devices[] = {
282	{ .ldn = 7, .type = SUPERIO_DEV_GPIO },	282	{ .ldn = 7, .type = SUPERIO_DEV_GPIO },
283	{ .ldn = 8, .type = SUPERIO_DEV_WDT },	283	{ .ldn = 8, .type = SUPERIO_DEV_WDT },
284	{ .ldn = 15, .type = SUPERIO_DEV_GPIO },	284	{ .ldn = 15, .type = SUPERIO_DEV_GPIO },
285	{ .type = SUPERIO_DEV_NONE },	285	{ .type = SUPERIO_DEV_NONE },
286	};	286	};
287		287
288	const struct sio_device nct5585_devices[] = {	288	const struct sio_device nct5585_devices[] = {
289	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },	289	{ .ldn = 9, .type = SUPERIO_DEV_GPIO },
290	{ .type = SUPERIO_DEV_NONE },	290	{ .type = SUPERIO_DEV_NONE },
291	};	291	};
292		292
293	const struct sio_device nct611x_devices[] = {	293	const struct sio_device nct611x_devices[] = {
294	{ .ldn = 0x7, .type = SUPERIO_DEV_GPIO },	294	{ .ldn = 0x7, .type = SUPERIO_DEV_GPIO },
295	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },	295	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
296	{ .type = SUPERIO_DEV_NONE },	296	{ .type = SUPERIO_DEV_NONE },
297	};	297	};
298		298
		299	const struct sio_device nct612x_devices[] = {
		300	{ .ldn = 0x7, .type = SUPERIO_DEV_GPIO },
		301	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
		302	{ .ldn = 0x9, .type = SUPERIO_DEV_GPIO },
		303	{ .ldn = 0xb, .type = SUPERIO_DEV_HWM },
		304	{ .type = SUPERIO_DEV_NONE },
		305	};
		306
299	const struct sio_device nct67xx_devices[] = {	307	const struct sio_device nct67xx_devices[] = {
300	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },	308	{ .ldn = 0x8, .type = SUPERIO_DEV_WDT },
301	{ .ldn = 0x9, .type = SUPERIO_DEV_GPIO },	309	{ .ldn = 0x9, .type = SUPERIO_DEV_GPIO },
302	{ .ldn = 0xb, .type = SUPERIO_DEV_HWM },	310	{ .ldn = 0xb, .type = SUPERIO_DEV_HWM },
303	{ .type = SUPERIO_DEV_NONE },	311	{ .type = SUPERIO_DEV_NONE },
304	};	312	};
305		313
306	const struct sio_device fintek_devices[] = {	314	const struct sio_device fintek_devices[] = {
307	{ .ldn = 6, .type = SUPERIO_DEV_GPIO },	315	{ .ldn = 6, .type = SUPERIO_DEV_GPIO },
308	{ .ldn = 7, .type = SUPERIO_DEV_WDT },	316	{ .ldn = 7, .type = SUPERIO_DEV_WDT },
309	{ .type = SUPERIO_DEV_NONE },	317	{ .type = SUPERIO_DEV_NONE },
310	};	318	};
311		319
312	static const struct {	320	static const struct {
313	superio_vendor_t vendor;	321	superio_vendor_t vendor;
314	uint16_t devid;	322	uint16_t devid;
315	uint16_t mask;	323	uint16_t mask;
316	int extid; /* Extra ID: used to handle conflicting devid. */	324	int extid; /* Extra ID: used to handle conflicting devid. */
317	const char *descr;	325	const char *descr;
318	const struct sio_device *devices;	326	const struct sio_device *devices;
319	} superio_table[] = {	327	} superio_table[] = {
320	{	328	{
321	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8613,	329	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8613,
322	.devices = ite_devices,	330	.devices = ite_devices,
323	},	331	},
324	{	332	{
325	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8712,	333	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8712,
326	.devices = ite_devices,	334	.devices = ite_devices,
327	},	335	},
328	{	336	{
329	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8716,	337	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8716,
330	.devices = ite_devices,	338	.devices = ite_devices,
331	},	339	},
332	{	340	{
333	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8718,	341	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8718,
334	.devices = ite_devices,	342	.devices = ite_devices,
335	},	343	},
336	{	344	{
337	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8720,	345	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8720,
338	.devices = ite_devices,	346	.devices = ite_devices,
339	},	347	},
340	{	348	{
341	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8721,	349	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8721,
342	.devices = ite_devices,	350	.devices = ite_devices,
343	},	351	},
344	{	352	{
345	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8726,	353	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8726,
346	.devices = ite_devices,	354	.devices = ite_devices,
347	},	355	},
348	{	356	{
349	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8728,	357	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8728,
350	.devices = ite_devices,	358	.devices = ite_devices,
351	},	359	},
352	{	360	{
353	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8771,	361	.vendor = SUPERIO_VENDOR_ITE, .devid = 0x8771,
354	.devices = ite_devices,	362	.devices = ite_devices,
355	},	363	},
356	{	364	{
357	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x1061, .mask = 0x00,	365	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x1061, .mask = 0x00,
358	.descr = "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. A)",	366	.descr = "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. A)",
359	.devices = nct5104_devices,	367	.devices = nct5104_devices,
360	},	368	},
361	{	369	{
362	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5200, .mask = 0xff,	370	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5200, .mask = 0xff,
363	.descr = "Winbond 83627HF/F/HG/G",	371	.descr = "Winbond 83627HF/F/HG/G",
364	.devices = nvt_devices,	372	.devices = nvt_devices,
365	},	373	},
366	{	374	{
367	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5900, .mask = 0xff,	375	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x5900, .mask = 0xff,
368	.descr = "Winbond 83627S",	376	.descr = "Winbond 83627S",
369	.devices = nvt_devices,	377	.devices = nvt_devices,
370	},	378	},
371	{	379	{
372	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6000, .mask = 0xff,	380	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6000, .mask = 0xff,
373	.descr = "Winbond 83697HF",	381	.descr = "Winbond 83697HF",
374	.devices = nvt_devices,	382	.devices = nvt_devices,
375	},	383	},
376	{	384	{
377	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6800, .mask = 0xff,	385	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x6800, .mask = 0xff,
378	.descr = "Winbond 83697UG",	386	.descr = "Winbond 83697UG",
379	.devices = nvt_devices,	387	.devices = nvt_devices,
380	},	388	},
381	{	389	{
382	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x7000, .mask = 0xff,	390	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x7000, .mask = 0xff,
383	.descr = "Winbond 83637HF",	391	.descr = "Winbond 83637HF",
384	.devices = nvt_devices,	392	.devices = nvt_devices,
385	},	393	},
386	{	394	{
387	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8200, .mask = 0xff,	395	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8200, .mask = 0xff,
388	.descr = "Winbond 83627THF",	396	.descr = "Winbond 83627THF",
389	.devices = nvt_devices,	397	.devices = nvt_devices,
390	},	398	},
391	{	399	{
392	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8500, .mask = 0xff,	400	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8500, .mask = 0xff,
393	.descr = "Winbond 83687THF",	401	.descr = "Winbond 83687THF",
394	.devices = nvt_devices,	402	.devices = nvt_devices,
395	},	403	},
396	{	404	{
397	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8800, .mask = 0xff,	405	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0x8800, .mask = 0xff,
398	.descr = "Winbond 83627EHF",	406	.descr = "Winbond 83627EHF",
399	.devices = nvt_devices,	407	.devices = nvt_devices,
400	},	408	},
401	{	409	{
402	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa000, .mask = 0xff,	410	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa000, .mask = 0xff,
403	.descr = "Winbond 83627DHG",	411	.descr = "Winbond 83627DHG",
404	.devices = w83627_devices,	412	.devices = w83627_devices,
405	},	413	},
406	{	414	{
407	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa200, .mask = 0xff,	415	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa200, .mask = 0xff,
408	.descr = "Winbond 83627UHG",	416	.descr = "Winbond 83627UHG",
409	.devices = nvt_devices,	417	.devices = nvt_devices,
410	},	418	},
411	{	419	{
412	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa500, .mask = 0xff,	420	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xa500, .mask = 0xff,
413	.descr = "Winbond 83667HG",	421	.descr = "Winbond 83667HG",
414	.devices = nvt_devices,	422	.devices = nvt_devices,
415	},	423	},
416	{	424	{
417	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb000, .mask = 0xff,	425	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb000, .mask = 0xff,
418	.descr = "Winbond 83627DHG-P",	426	.descr = "Winbond 83627DHG-P",
419	.devices = nvt_devices,	427	.devices = nvt_devices,
420	},	428	},
421	{	429	{
422	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb300, .mask = 0xff,	430	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb300, .mask = 0xff,
423	.descr = "Winbond 83667HG-B",	431	.descr = "Winbond 83667HG-B",
424	.devices = nvt_devices,	432	.devices = nvt_devices,
425	},	433	},
426	{	434	{
427	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb400, .mask = 0xff,	435	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xb400, .mask = 0xff,
428	.descr = "Nuvoton NCT6775",	436	.descr = "Nuvoton NCT6775",
429	.devices = nvt_devices,	437	.devices = nvt_devices,
430	},	438	},
431	{	439	{
432	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc300, .mask = 0xff,	440	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc300, .mask = 0xff,
433	.descr = "Nuvoton NCT6776",	441	.descr = "Nuvoton NCT6776",
434	.devices = nvt_devices,	442	.devices = nvt_devices,
435	},	443	},
436	{	444	{
437	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc400, .mask = 0xff,	445	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc400, .mask = 0xff,
438	.descr = "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. B+)",	446	.descr = "Nuvoton NCT5104D/NCT6102D/NCT6106D (rev. B+)",
439	.devices = nct5104_devices,	447	.devices = nct5104_devices,
440	},	448	},
441	{	449	{
442	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc500, .mask = 0xff,	450	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc500, .mask = 0xff,
443	.descr = "Nuvoton NCT6779D",	451	.descr = "Nuvoton NCT6779D",
444	.devices = nct67xx_devices,	452	.devices = nct67xx_devices,
445	},	453	},
446	{	454	{
447	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 1,	455	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 1,
448	.descr = "Nuvoton NCT6796D-E",	456	.descr = "Nuvoton NCT6796D-E",
449	.devices = nct67xx_devices,	457	.devices = nct67xx_devices,
450	},	458	},
451	{	459	{
452	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 2,	460	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd42a, .extid = 2,
453	.descr = "Nuvoton NCT5585D",	461	.descr = "Nuvoton NCT5585D",
454	.devices = nct5585_devices,	462	.devices = nct5585_devices,
455	},	463	},
456	{	464	{
457	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc800, .mask = 0xff,	465	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc800, .mask = 0xff,
458	.descr = "Nuvoton NCT6791",	466	.descr = "Nuvoton NCT6791",
459	.devices = nvt_devices,	467	.devices = nvt_devices,
460	},	468	},
461	{	469	{
462	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc900, .mask = 0xff,	470	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xc900, .mask = 0xff,
463	.descr = "Nuvoton NCT6792",	471	.descr = "Nuvoton NCT6792",
464	.devices = nvt_devices,	472	.devices = nvt_devices,
465	},	473	},
466	{	474	{
467	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd100, .mask = 0xff,	475	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd100, .mask = 0xff,
468	.descr = "Nuvoton NCT6793",	476	.descr = "Nuvoton NCT6793",
469	.devices = nvt_devices,	477	.devices = nvt_devices,
470	},	478	},
471	{	479	{
472	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd200, .mask = 0xff,	480	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd282,
473	.descr = "Nuvoton NCT6112D/NCT6114D/NCT6116D",	481	.descr = "Nuvoton NCT6112D", // 2 UART
474	.devices = nct611x_devices,	482	.devices = nct611x_devices,
475	},	483	},
		484	{
		485	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd280, .mask = 0x0003,
		486	.descr = "Nuvoton NCT6114D/NCT6116D", // 4/6 UART - 0xd281? 0xd283?
		487	.devices = nct611x_devices,
		488	},
		489	{
		490	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd2A4,
		491	.descr = "Nuvoton NCT6122D", // 2 UART
		492	.devices = nct612x_devices,
		493	},
		494	{
		495	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd284,
		496	.descr = "Nuvoton NCT6126D", // 6 UART
		497	.devices = nct612x_devices,
		498	},
476	{	499	{
477	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd300, .mask = 0xff,	500	.vendor = SUPERIO_VENDOR_NUVOTON, .devid = 0xd300, .mask = 0xff,
478	.descr = "Nuvoton NCT6795",	501	.descr = "Nuvoton NCT6795",
479	.devices = nvt_devices,	502	.devices = nvt_devices,
480	},	503	},
481	{	504	{
482	.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x1210, .mask = 0xff,	505	.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x1210, .mask = 0xff,
483	.descr = "Fintek F81803",	506	.descr = "Fintek F81803",
484	.devices = fintek_devices,	507	.devices = fintek_devices,
485	},	508	},
486	{	509	{
487	.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x0704,	510	.vendor = SUPERIO_VENDOR_FINTEK, .devid = 0x0704,
488	.descr = "Fintek F81865",	511	.descr = "Fintek F81865",
489	.devices = fintek_devices,	512	.devices = fintek_devices,
490	},	513	},
491	{ 0, 0 }	514	{ 0, 0 }
492	};	515	};
493		516
494	static const char *	517	static const char *
495	devtype_to_str(superio_dev_type_t type)	518	devtype_to_str(superio_dev_type_t type)
496	{	519	{
497	switch (type) {	520	switch (type) {
498	case SUPERIO_DEV_NONE:	521	case SUPERIO_DEV_NONE:
499	return ("none");	522	return ("none");
500	case SUPERIO_DEV_HWM:	523	case SUPERIO_DEV_HWM:
501	return ("HWM");	524	return ("HWM");
502	case SUPERIO_DEV_WDT:	525	case SUPERIO_DEV_WDT:
503	return ("WDT");	526	return ("WDT");
504	case SUPERIO_DEV_GPIO:	527	case SUPERIO_DEV_GPIO:
505	return ("GPIO");	528	return ("GPIO");
506	case SUPERIO_DEV_MAX:	529	case SUPERIO_DEV_MAX:
507	return ("invalid");	530	return ("invalid");
508	}	531	}
509	return ("invalid");	532	return ("invalid");
510	}	533	}
511		534
512	static int	535	static int
513	superio_detect(device_t dev, bool claim, struct siosc *sc)	536	superio_detect(device_t dev, bool claim, struct siosc *sc)
514	{	537	{
515	struct resource *res;	538	struct resource *res;
516	rman_res_t port;	539	rman_res_t port;
517	rman_res_t count;	540	rman_res_t count;
518	uint16_t devid;	541	uint16_t devid;
519	uint8_t revid;	542	uint8_t revid;
520	int error;	543	int error;
521	int rid;	544	int rid;
522	int i, m;	545	int i, m;
523	int prefer;	546	int prefer;
524		547
525	error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, &count);	548	error = bus_get_resource(dev, SYS_RES_IOPORT, 0, &port, &count);
526	if (error != 0)	549	if (error != 0)
527	return (error);	550	return (error);
528	if (port > UINT16_MAX \|\| count < NUMPORTS) {	551	if (port > UINT16_MAX \|\| count < NUMPORTS) {
529	device_printf(dev, "unexpected I/O range size\n");	552	device_printf(dev, "unexpected I/O range size\n");
530	return (ENXIO);	553	return (ENXIO);
531	}	554	}
532		555
533	/*	556	/*
534	* Make a temporary resource reservation for hardware probing.	557	* Make a temporary resource reservation for hardware probing.
535	* If we can't get the resources we need then	558	* If we can't get the resources we need then
536	* we need to abort. Possibly this indicates	559	* we need to abort. Possibly this indicates
537	* the resources were used by another device	560	* the resources were used by another device
538	* in which case the probe would have failed anyhow.	561	* in which case the probe would have failed anyhow.
539	*/	562	*/
540	rid = 0;	563	rid = 0;
541	res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);	564	res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, RF_ACTIVE);
542	if (res == NULL) {	565	if (res == NULL) {
543	if (claim)	566	if (claim)
544	device_printf(dev, "failed to allocate I/O resource\n");	567	device_printf(dev, "failed to allocate I/O resource\n");
545	return (ENXIO);	568	return (ENXIO);
546	}	569	}
547		570
548	prefer = 0;	571	prefer = 0;
549	resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer", &prefer);	572	resource_int_value(device_get_name(dev), device_get_unit(dev), "prefer", &prefer);
550	if (bootverbose && prefer > 0)	573	if (bootverbose && prefer > 0)
551	device_printf(dev, "prefer extid %d\n", prefer);	574	device_printf(dev, "prefer extid %d\n", prefer);
552		575
553	for (m = 0; methods_table[m] != NULL; m++) {	576	for (m = 0; methods_table[m] != NULL; m++) {
554	methods_table[m]->enter(res, port);	577	methods_table[m]->enter(res, port);
555	if (methods_table[m]->vendor == SUPERIO_VENDOR_ITE) {	578	if (methods_table[m]->vendor == SUPERIO_VENDOR_ITE) {
556	devid = sio_readw(res, 0x20);	579	devid = sio_readw(res, 0x20);
557	revid = sio_read(res, 0x22);	580	revid = sio_read(res, 0x22);
558	} else if (methods_table[m]->vendor == SUPERIO_VENDOR_NUVOTON) {	581	} else if (methods_table[m]->vendor == SUPERIO_VENDOR_NUVOTON) {
559	devid = sio_read(res, 0x20);	582	devid = sio_read(res, 0x20);
560	revid = sio_read(res, 0x21);	583	revid = sio_read(res, 0x21);
561	devid = (devid << 8) \| revid;	584	devid = (devid << 8) \| revid;
562	} else if (methods_table[m]->vendor == SUPERIO_VENDOR_FINTEK) {	585	} else if (methods_table[m]->vendor == SUPERIO_VENDOR_FINTEK) {
563	devid = sio_read(res, 0x20);	586	devid = sio_read(res, 0x20);
564	revid = sio_read(res, 0x21);	587	revid = sio_read(res, 0x21);
565	devid = (devid << 8) \| revid;	588	devid = (devid << 8) \| revid;
566	} else {	589	} else {
567	continue;	590	continue;
568	}	591	}
569	methods_table[m]->exit(res, port);	592	methods_table[m]->exit(res, port);
570	for (i = 0; superio_table[i].vendor != 0; i++) {	593	for (i = 0; superio_table[i].vendor != 0; i++) {
571	uint16_t mask;	594	uint16_t mask;
572		595
573	mask = superio_table[i].mask;	596	mask = superio_table[i].mask;
574	if (superio_table[i].vendor !=	597	if (superio_table[i].vendor !=