Attachment #47249 for bug #72442

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Lines 6-12 Link Here

(-)pearpc/Makefile (-6 / +8 lines)
6	#	6	#
7		7
8	PORTNAME= pearpc	8	PORTNAME= pearpc
9	PORTVERSION= 0.3.0	9	PORTVERSION= 0.3.1
10	CATEGORIES= emulators	10	CATEGORIES= emulators
11	MASTER_SITES= ${MASTER_SITE_SOURCEFORGE}	11	MASTER_SITES= ${MASTER_SITE_SOURCEFORGE}
12	MASTER_SITE_SUBDIR= ${PORTNAME}	12	MASTER_SITE_SUBDIR= ${PORTNAME}
Lines 42-47 Link Here
42	#CONFIGURE_ARGS+= --enable-ui=nogui	42	#CONFIGURE_ARGS+= --enable-ui=nogui
43	#.endif	43	#.endif
44		44
		45	.if defined(WITH_SDL)
		46	CONFIGURE_ARGS+= --enable-ui=sdl
		47	USE_SDL= sdl
		48	.else
		49	CONFIGURE_ARGS+= --enable-ui=x11
		50	.endif
		51
45	.include <bsd.port.pre.mk>	52	.include <bsd.port.pre.mk>
46		53
47	# jitc_x86 is avaible only on x86	54	# jitc_x86 is avaible only on x86
Lines 66-76 Link Here
66	@${ECHO_MSG} ""	73	@${ECHO_MSG} ""
67	@${ECHO_MSG} "You can do optimized build defining WITH_OPTIMIZED_CFLAGS=yes."	74	@${ECHO_MSG} "You can do optimized build defining WITH_OPTIMIZED_CFLAGS=yes."
68	@${ECHO_MSG} ""	75	@${ECHO_MSG} ""
69	.endif
70
71	post-patch:
72	.if ${OSVERSION} < 500000
73	@${REINPLACE_CMD} -e 's\|stdint.h\|inttypes.h\|' ${WRKSRC}/src/system/osapi/posix/types.h
74	.endif	76	.endif
75		77
76	post-configure:	78	post-configure:

Lines 1-2 Link Here

(-)pearpc/distinfo (-2 / +2 lines)
1	MD5 (pearpc-0.3.0.tar.gz) = 6d68187c78cae674a5efa6662c4cdb22	1	MD5 (pearpc-0.3.1.tar.gz) = d7ac0566f6ab884029e374ac68842932
2	SIZE (pearpc-0.3.0.tar.gz) = 814686	2	SIZE (pearpc-0.3.1.tar.gz) = 834258




--- src/cpu/cpu_jitc_x86/ppc_cpu.h.orig	Tue Oct  5 15:48:01 2004
+++ src/cpu/cpu_jitc_x86/ppc_cpu.h	Tue Oct  5 17:03:40 2004
@@ -112,7 +112,8 @@
 	uint32 current_code_base;
 } PACKED;
 
-enum PPC_Register {
+
+/*enum PPC_Register {
 	PPC_REG_NO = 0,
 	PPC_GPR0 = offsetof(PPC_CPU_State, gpr),
 	PPC_FPR1 = offsetof(PPC_CPU_State, fpr),
@@ -132,7 +133,27 @@
 	PPC_PVR = offsetof(PPC_CPU_State, pvr),
 	PPC_HID0 = offsetof(PPC_CPU_State, hid),
 	PPC_HID1 = offsetof(PPC_CPU_State, hid)+sizeof (uint32),
-};
+};*/
+#define PPC_Register size_t
+#define PPC_REG_NO 0
+#define PPC_GPR0  offsetof(PPC_CPU_State, gpr)
+#define PPC_FPR1  offsetof(PPC_CPU_State, fpr)
+#define PPC_CR  offsetof(PPC_CPU_State, cr)
+#define PPC_FPSCR  offsetof(PPC_CPU_State, fpscr)
+#define PPC_XER  offsetof(PPC_CPU_State, xer)
+#define PPC_LR  offsetof(PPC_CPU_State, lr)
+#define PPC_CTR  offsetof(PPC_CPU_State, ctr)
+#define PPC_MSR  offsetof(PPC_CPU_State, msr)
+#define PPC_SRR0  offsetof(PPC_CPU_State, srr)
+#define PPC_SRR1  offsetof(PPC_CPU_State, srr)+sizeof (uint32)
+#define PPC_DSISR  offsetof(PPC_CPU_State, dsisr)
+#define PPC_DAR  offsetof(PPC_CPU_State, dar)
+#define PPC_DEC  offsetof(PPC_CPU_State, dec)
+#define PPC_SDR1  offsetof(PPC_CPU_State, sdr1) 
+#define PPC_EAR  offsetof(PPC_CPU_State, ear)
+#define PPC_PVR  offsetof(PPC_CPU_State, pvr)
+#define PPC_HID0  offsetof(PPC_CPU_State, hid)
+#define PPC_HID1  offsetof(PPC_CPU_State, hid)+sizeof (uint32)
 
 enum PPC_CRx {
 	PPC_CR0=0,

Return to bug 72442

Line 0 Link Here

(-)pearpc/files/patch-gcc34 (+41 lines)
	1	--- src/cpu/cpu_jitc_x86/ppc_cpu.h.orig Tue Oct 5 15:48:01 2004
	2	+++ src/cpu/cpu_jitc_x86/ppc_cpu.h Tue Oct 5 17:03:40 2004
	3	@@ -112,7 +112,8 @@
	4	uint32 current_code_base;
	5	} PACKED;
	6
	7	-enum PPC_Register {
	8	+
	9	+/*enum PPC_Register {
	10	PPC_REG_NO = 0,
	11	PPC_GPR0 = offsetof(PPC_CPU_State, gpr),
	12	PPC_FPR1 = offsetof(PPC_CPU_State, fpr),
	13	@@ -132,7 +133,27 @@
	14	PPC_PVR = offsetof(PPC_CPU_State, pvr),
	15	PPC_HID0 = offsetof(PPC_CPU_State, hid),
	16	PPC_HID1 = offsetof(PPC_CPU_State, hid)+sizeof (uint32),
	17	-};
	18	+};*/
	19	+#define PPC_Register size_t
	20	+#define PPC_REG_NO 0
	21	+#define PPC_GPR0 offsetof(PPC_CPU_State, gpr)
	22	+#define PPC_FPR1 offsetof(PPC_CPU_State, fpr)
	23	+#define PPC_CR offsetof(PPC_CPU_State, cr)
	24	+#define PPC_FPSCR offsetof(PPC_CPU_State, fpscr)
	25	+#define PPC_XER offsetof(PPC_CPU_State, xer)
	26	+#define PPC_LR offsetof(PPC_CPU_State, lr)
	27	+#define PPC_CTR offsetof(PPC_CPU_State, ctr)
	28	+#define PPC_MSR offsetof(PPC_CPU_State, msr)
	29	+#define PPC_SRR0 offsetof(PPC_CPU_State, srr)
	30	+#define PPC_SRR1 offsetof(PPC_CPU_State, srr)+sizeof (uint32)
	31	+#define PPC_DSISR offsetof(PPC_CPU_State, dsisr)
	32	+#define PPC_DAR offsetof(PPC_CPU_State, dar)
	33	+#define PPC_DEC offsetof(PPC_CPU_State, dec)
	34	+#define PPC_SDR1 offsetof(PPC_CPU_State, sdr1)
	35	+#define PPC_EAR offsetof(PPC_CPU_State, ear)
	36	+#define PPC_PVR offsetof(PPC_CPU_State, pvr)
	37	+#define PPC_HID0 offsetof(PPC_CPU_State, hid)
	38	+#define PPC_HID1 offsetof(PPC_CPU_State, hid)+sizeof (uint32)
	39
	40	enum PPC_CRx {
	41	PPC_CR0=0,