|
Lines 7-16
Link Here
|
| 7 |
# |
7 |
# |
| 8 |
|
8 |
|
| 9 |
PORTNAME= iverilog |
9 |
PORTNAME= iverilog |
| 10 |
PORTVERSION= 0.7.20040606 |
10 |
PORTVERSION= 0.8 |
| 11 |
CATEGORIES= cad |
11 |
CATEGORIES= cad |
| 12 |
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/snapshots/ |
12 |
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v$(PORTVERSION)/ |
| 13 |
DISTNAME= verilog-20040606 |
13 |
DISTNAME= verilog-$(PORTVERSION) |
| 14 |
|
14 |
|
| 15 |
MAINTAINER= watchman@ludd.luth.se |
15 |
MAINTAINER= watchman@ludd.luth.se |
| 16 |
COMMENT= A Verilog simulation and synthesis tool |
16 |
COMMENT= A Verilog simulation and synthesis tool |