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Lines 93-98
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| 93 |
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93 |
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| 94 |
struct mtx *lock; |
94 |
struct mtx *lock; |
| 95 |
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95 |
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96 |
u_int32_t numchans; |
| 96 |
u_int32_t playchns; |
97 |
u_int32_t playchns; |
| 97 |
unsigned int bufsz; |
98 |
unsigned int bufsz; |
| 98 |
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99 |
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Lines 725-731
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| 725 |
intsrc = tr_rd(tr, TR_REG_MISCINT, 4); |
726 |
intsrc = tr_rd(tr, TR_REG_MISCINT, 4); |
| 726 |
if (intsrc & TR_INT_ADDR) { |
727 |
if (intsrc & TR_INT_ADDR) { |
| 727 |
chnum = 0; |
728 |
chnum = 0; |
| 728 |
while (chnum < 64) { |
729 |
while (chnum < tr->numchans) { |
| 729 |
mask = 0x00000001; |
730 |
mask = 0x00000001; |
| 730 |
active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); |
731 |
active = tr_rd(tr, (chnum < 32)? TR_REG_ADDRINTA : TR_REG_ADDRINTB, 4); |
| 731 |
bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); |
732 |
bufhalf = tr_rd(tr, (chnum < 32)? TR_REG_CSPF_A : TR_REG_CSPF_B, 4); |
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Lines 773-778
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| 773 |
tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); |
774 |
tr_wr(tr, SPA_REG_CODECST, SPA_RST_OFF, 4); |
| 774 |
break; |
775 |
break; |
| 775 |
case TDX_PCI_ID: |
776 |
case TDX_PCI_ID: |
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777 |
case ALI_PCI_ID: |
| 776 |
tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); |
778 |
tr_wr(tr, TDX_REG_CODECST, TDX_CDC_ON, 4); |
| 777 |
break; |
779 |
break; |
| 778 |
case TNX_PCI_ID: |
780 |
case TNX_PCI_ID: |
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Lines 846-851
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| 846 |
device_printf(dev, "unable to initialize the card\n"); |
848 |
device_printf(dev, "unable to initialize the card\n"); |
| 847 |
goto bad; |
849 |
goto bad; |
| 848 |
} |
850 |
} |
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851 |
if (tr->type == ALI_PCI_ID) |
| 852 |
tr->numchans = 32; |
| 853 |
else |
| 854 |
tr->numchans = 64; |
| 849 |
tr->playchns = 0; |
855 |
tr->playchns = 0; |
| 850 |
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856 |
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| 851 |
codec = AC97_CREATE(dev, tr, tr_ac97); |
857 |
codec = AC97_CREATE(dev, tr, tr_ac97); |