Attachment 152502 Details for Bug 197259 – Import llvm r227089 on top of clang 3.6.0

[patch] Import llvm r227089 on top of clang 3.6.0

import-llvm-r227089-1.diff (text/plain), 9.76 KB, created by Dimitry Andric on 2015-02-02 22:46:20 UTC

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Creator: Dimitry Andric

Created: 2015-02-02 22:46:20 UTC

Size: 9.76 KB

patch

obsolete

>Index: lib/Target/Mips/Mips64InstrInfo.td
>===================================================================
>--- lib/Target/Mips/Mips64InstrInfo.td
>+++ lib/Target/Mips/Mips64InstrInfo.td
>@@ -440,6 +440,16 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
> // bswap MipsPattern
> def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
> 
>+// Carry pattern
>+def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
>+              (DSUBu GPR64:$lhs, GPR64:$rhs)>;
>+let AdditionalPredicates = [NotDSP] in {
>+  def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
>+                (DADDu GPR64:$lhs, GPR64:$rhs)>;
>+  def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
>+                (DADDiu GPR64:$lhs, imm:$imm)>;
>+}
>+
> //===----------------------------------------------------------------------===//
> // Instruction aliases
> //===----------------------------------------------------------------------===//
>Index: lib/Target/Mips/MipsISelLowering.cpp
>===================================================================
>--- lib/Target/Mips/MipsISelLowering.cpp
>+++ lib/Target/Mips/MipsISelLowering.cpp
>@@ -261,6 +261,9 @@ MipsTargetLowering::MipsTargetLowering(const MipsT
>     setOperationAction(ISD::LOAD,               MVT::i64,   Custom);
>     setOperationAction(ISD::STORE,              MVT::i64,   Custom);
>     setOperationAction(ISD::FP_TO_SINT,         MVT::i64,   Custom);
>+    setOperationAction(ISD::SHL_PARTS,          MVT::i64,   Custom);
>+    setOperationAction(ISD::SRA_PARTS,          MVT::i64,   Custom);
>+    setOperationAction(ISD::SRL_PARTS,          MVT::i64,   Custom);
>   }
> 
>   if (!Subtarget.isGP64bit()) {
>@@ -2017,10 +2020,11 @@ SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDVa
> SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
>                                                 SelectionDAG &DAG) const {
>   SDLoc DL(Op);
>+  MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
>+
>   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
>   SDValue Shamt = Op.getOperand(2);
>-
>-  // if shamt < 32:
>+  // if shamt < (VT.bits):
>   //  lo = (shl lo, shamt)
>   //  hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
>   // else:
>@@ -2028,18 +2032,17 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SD
>   //  hi = (shl lo, shamt[4:0])
>   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
>                             DAG.getConstant(-1, MVT::i32));
>-  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo,
>-                                      DAG.getConstant(1, MVT::i32));
>-  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo,
>-                                     Not);
>-  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt);
>-  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
>-  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt);
>+  SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
>+                                      DAG.getConstant(1, VT));
>+  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
>+  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
>+  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
>+  SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
>   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
>                              DAG.getConstant(0x20, MVT::i32));
>-  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
>-                   DAG.getConstant(0, MVT::i32), ShiftLeftLo);
>-  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or);
>+  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
>+                   DAG.getConstant(0, VT), ShiftLeftLo);
>+  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
> 
>   SDValue Ops[2] = {Lo, Hi};
>   return DAG.getMergeValues(Ops, DL);
>@@ -2050,8 +2053,9 @@ SDValue MipsTargetLowering::lowerShiftRightParts(S
>   SDLoc DL(Op);
>   SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
>   SDValue Shamt = Op.getOperand(2);
>+  MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
> 
>-  // if shamt < 32:
>+  // if shamt < (VT.bits):
>   //  lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
>   //  if isSRA:
>   //    hi = (sra hi, shamt)
>@@ -2066,21 +2070,19 @@ SDValue MipsTargetLowering::lowerShiftRightParts(S
>   //   hi = 0
>   SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
>                             DAG.getConstant(-1, MVT::i32));
>-  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi,
>-                                     DAG.getConstant(1, MVT::i32));
>-  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not);
>-  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt);
>-  SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo);
>-  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32,
>-                                     Hi, Shamt);
>+  SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
>+                                     DAG.getConstant(1, VT));
>+  SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
>+  SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
>+  SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
>+  SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
>+                                     DL, VT, Hi, Shamt);
>   SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
>                              DAG.getConstant(0x20, MVT::i32));
>-  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi,
>-                                DAG.getConstant(31, MVT::i32));
>-  Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or);
>-  Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond,
>-                   IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32),
>-                   ShiftRightHi);
>+  SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT));
>+  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
>+  Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
>+                   IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi);
> 
>   SDValue Ops[2] = {Lo, Hi};
>   return DAG.getMergeValues(Ops, DL);
>Index: lib/Target/Mips/MipsSEISelDAGToDAG.cpp
>===================================================================
>--- lib/Target/Mips/MipsSEISelDAGToDAG.cpp
>+++ lib/Target/Mips/MipsSEISelDAGToDAG.cpp
>@@ -236,13 +236,31 @@ SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigne
>           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
>          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
> 
>+  unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu;
>+  if (Subtarget->isGP64bit()) {
>+    SLTuOp = Mips::SLTu64;
>+    ADDuOp = Mips::DADDu;
>+  }
>+
>   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
>   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
>   EVT VT = LHS.getValueType();
> 
>-  SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
>-  SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
>+  SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops);
>+
>+  if (Subtarget->isGP64bit()) {
>+    // On 64-bit targets, sltu produces an i64 but our backend currently says
>+    // that SLTu64 produces an i32. We need to fix this in the long run but for
>+    // now, just make the DAG type-correct by asserting the upper bits are zero.
>+    Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT,
>+                                   CurDAG->getTargetConstant(0, VT),
>+                                   SDValue(Carry, 0),
>+                                   CurDAG->getTargetConstant(Mips::sub_32, VT));
>+  }
>+
>+  SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT,
>                                             SDValue(Carry, 0), RHS);
>+
>   return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
>                               SDValue(AddCarry, 0));
> }
>@@ -641,7 +659,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selec
> 
>   case ISD::SUBE: {
>     SDValue InFlag = Node->getOperand(2);
>-    Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
>+    unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu;
>+    Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node);
>     return std::make_pair(true, Result);
>   }
> 
>@@ -649,7 +668,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selec
>     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
>       break;
>     SDValue InFlag = Node->getOperand(2);
>-    Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
>+    unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu;
>+    Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node);
>     return std::make_pair(true, Result);
>   }
> 
>Index: lib/Target/Mips/MipsSEISelLowering.cpp
>===================================================================
>--- lib/Target/Mips/MipsSEISelLowering.cpp
>+++ lib/Target/Mips/MipsSEISelLowering.cpp
>@@ -122,6 +122,8 @@ MipsSETargetLowering::MipsSETargetLowering(const M
>     setOperationAction(ISD::MUL,              MVT::i64, Custom);
> 
>   if (Subtarget.isGP64bit()) {
>+    setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Custom);
>+    setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Custom);
>     setOperationAction(ISD::MULHS,            MVT::i64, Custom);
>     setOperationAction(ISD::MULHU,            MVT::i64, Custom);
>     setOperationAction(ISD::SDIVREM,          MVT::i64, Custom);
>@@ -200,6 +202,8 @@ MipsSETargetLowering::MipsSETargetLowering(const M
>   if (Subtarget.hasMips64r6()) {
>     // MIPS64r6 replaces the accumulator-based multiplies with a three register
>     // instruction
>+    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
>+    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
>     setOperationAction(ISD::MUL, MVT::i64, Legal);
>     setOperationAction(ISD::MULHS, MVT::i64, Legal);
>     setOperationAction(ISD::MULHU, MVT::i64, Legal);

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Attachments on bug 197259: 152461 | 152462 | 152489 | 152490 | 152502 | 152522 | 152527 | 152528