Attachment 174474 Details for Bug 211699 – never read the slot_ctl register

[patch] never read the slot_ctl register

slot_ctl.diff (text/plain), 1.77 KB, created by Eric van Gyzen on 2016-09-07 15:15:19 UTC

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Creator: Eric van Gyzen

Created: 2016-09-07 15:15:19 UTC

Size: 1.77 KB

patch

obsolete

>diff --git a/sys/dev/pci/pci_pci.c b/sys/dev/pci/pci_pci.c
>index dedc55a..9de93c5 100644
>--- a/sys/dev/pci/pci_pci.c
>+++ b/sys/dev/pci/pci_pci.c
>@@ -932,6 +932,7 @@ pcib_probe_hotplug(struct pcib_softc *sc)
> 
> 	sc->pcie_link_cap = pcie_read_config(dev, PCIER_LINK_CAP, 4);
> 	sc->pcie_slot_cap = pcie_read_config(dev, PCIER_SLOT_CAP, 4);
>+	sc->pcie_slot_ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
> 
> 	if ((sc->pcie_slot_cap & PCIEM_SLOT_CAP_HPC) == 0)
> 		return;
>@@ -977,13 +978,20 @@ pcib_pcie_hotplug_command(struct pcib_softc *sc, uint16_t val, uint16_t mask)
> 	if (sc->flags & PCIB_HOTPLUG_CMD_PENDING)
> 		return;
> 
>-	ctl = pcie_read_config(dev, PCIER_SLOT_CTL, 2);
>+	/*
>+	 * A read from the PCIEM_SLOT_CTL_PCC bit should return
>+	 * the last value written; however, some chips behave differently,
>+	 * apparently returning the actual power state.  Save the last value
>+	 * written and use that saved value in the following logic.
>+	 */
>+	ctl = sc->pcie_slot_ctl;
> 	new = (ctl & ~mask) | val;
> 	if (new == ctl)
> 		return;
> 	if (bootverbose)
> 		device_printf(dev, "HotPlug command: %04x -> %04x\n", ctl, new);
> 	pcie_write_config(dev, PCIER_SLOT_CTL, new, 2);
>+	sc->pcie_slot_ctl = new;
> 	if (!(sc->pcie_slot_cap & PCIEM_SLOT_CAP_NCCS) &&
> 	    (ctl & new) & PCIEM_SLOT_CTL_CCIE) {
> 		sc->flags |= PCIB_HOTPLUG_CMD_PENDING;
>diff --git a/sys/dev/pci/pcib_private.h b/sys/dev/pci/pcib_private.h
>index 65aec8d..5d2b41c 100644
>--- a/sys/dev/pci/pcib_private.h
>+++ b/sys/dev/pci/pcib_private.h
>@@ -132,6 +132,7 @@ struct pcib_softc
>     uint16_t	bridgectl;	/* bridge control register */
>     uint16_t	pcie_link_sta;
>     uint16_t	pcie_slot_sta;
>+    uint16_t	pcie_slot_ctl;	/* last value written to SLOT_CTL register */
>     uint32_t	pcie_link_cap;
>     uint32_t	pcie_slot_cap;
>     struct resource *pcie_irq;

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Attachments on bug 211699: 173465 | 173466 | 173467 | 174218 | 174219 | 174474 | 174487 | 179483