Attachment 188407 Details for Bug 223971 – diff of cpuid-etallen output host and guest

[patch] diff of cpuid-etallen output host and guest

cpuid-etallen.diff (text/plain), 6.24 KB, created by Vladimir Druzenko on 2017-11-29 18:25:08 UTC

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Creator: Vladimir Druzenko

Created: 2017-11-29 18:25:08 UTC

Size: 6.24 KB

patch

obsolete

>--- cpuid-etallen.host	2017-11-29 21:09:22.909575000 +0300
>+++ cpuid-etallen.guest	2017-11-29 21:18:45.565030000 +0300
>@@ -34,33 +34,33 @@
>       page size extension                    = true
>       processor serial number                = false
>       CLFLUSH instruction                    = true
>-      debug store                            = true
>-      thermal monitor and clock ctrl         = true
>+      debug store                            = false
>+      thermal monitor and clock ctrl         = false
>       MMX Technology                         = true
>       FXSAVE/FXRSTOR                         = true
>       SSE extensions                         = true
>       SSE2 extensions                        = true
>-      self snoop                             = true
>+      self snoop                             = false
>       hyper-threading / multi-core supported = true
>-      therm. monitor                         = true
>+      therm. monitor                         = false
>       IA64                                   = false
>-      pending break event                    = true
>+      pending break event                    = false
>    feature information (1/ecx):
>       PNI/SSE3: Prescott New Instructions     = true
>       PCLMULDQ instruction                    = false
>-      64-bit debug store                      = true
>-      MONITOR/MWAIT                           = true
>-      CPL-qualified debug store               = true
>-      VMX: virtual machine extensions         = true
>+      64-bit debug store                      = false
>+      MONITOR/MWAIT                           = false
>+      CPL-qualified debug store               = false
>+      VMX: virtual machine extensions         = false
>       SMX: safer mode extensions              = false
>-      Enhanced Intel SpeedStep Technology     = true
>-      thermal monitor 2                       = true
>+      Enhanced Intel SpeedStep Technology     = false
>+      thermal monitor 2                       = false
>       SSSE3 extensions                        = true
>       context ID: adaptive or shared L1 data  = false
>       FMA instruction                         = false
>-      CMPXCHG16B instruction                  = true
>-      xTPR disable                            = true
>-      perfmon and debug                       = true
>+      CMPXCHG16B instruction                  = false
>+      xTPR disable                            = false
>+      perfmon and debug                       = false
>       process context identifiers             = false
>       direct cache access                     = false
>       SSE4.1 extensions                       = false
>@@ -124,7 +124,7 @@
>       cache level                          = 0x2 (2)
>       self-initializing cache level        = true
>       fully associative cache              = false
>-      extra threads sharing this cache     = 0x1 (1)
>+      extra threads sharing this cache     = 0x0 (0)
>       extra processor cores on this die    = 0x3 (3)
>       system coherency line size           = 0x3f (63)
>       physical line partitions             = 0x0 (0)
>@@ -135,12 +135,12 @@
>       complex cache indexing               = false
>       number of sets - 1 (s)               = 4095
>    MONITOR/MWAIT (5):
>-      smallest monitor-line size (bytes)       = 0x40 (64)
>-      largest monitor-line size (bytes)        = 0x40 (64)
>-      enum of Monitor-MWAIT exts supported     = true
>-      supports intrs as break-event for MWAIT  = true
>+      smallest monitor-line size (bytes)       = 0x0 (0)
>+      largest monitor-line size (bytes)        = 0x0 (0)
>+      enum of Monitor-MWAIT exts supported     = false
>+      supports intrs as break-event for MWAIT  = false
>       number of C0 sub C-states using MWAIT    = 0x0 (0)
>-      number of C1 sub C-states using MWAIT    = 0x2 (2)
>+      number of C1 sub C-states using MWAIT    = 0x0 (0)
>       number of C2 sub C-states using MWAIT    = 0x0 (0)
>       number of C3 sub C-states using MWAIT    = 0x0 (0)
>       number of C4 sub C-states using MWAIT    = 0x0 (0)
>@@ -148,7 +148,7 @@
>       number of C6 sub C-states using MWAIT    = 0x0 (0)
>       number of C7 sub C-states using MWAIT    = 0x0 (0)
>    Thermal and Power Management Features (6):
>-      digital thermometer                     = true
>+      digital thermometer                     = false
>       Intel Turbo Boost Technology            = false
>       ARAT always running APIC timer          = false
>       PLN power limit notification            = false
>@@ -160,8 +160,8 @@
>       HWP energy performance preference       = false
>       HWP package level request               = false
>       HDC base registers                      = false
>-      digital thermometer thresholds          = 0x2 (2)
>-      ACNT/MCNT supported performance measure = true
>+      digital thermometer thresholds          = 0x0 (0)
>+      ACNT/MCNT supported performance measure = false
>       ACNT2 available                         = false
>       performance-energy bias capability      = false
>    extended feature flags (7):
>@@ -209,10 +209,10 @@
>    Direct Cache Access Parameters (9):
>       PLATFORM_DCA_CAP MSR bits = 0
>    Architecture Performance Monitoring Features (0xa/eax):
>-      version ID                               = 0x2 (2)
>-      number of counters per logical processor = 0x2 (2)
>-      bit width of counter                     = 0x28 (40)
>-      length of EBX bit vector                 = 0x7 (7)
>+      version ID                               = 0x0 (0)
>+      number of counters per logical processor = 0x0 (0)
>+      bit width of counter                     = 0x0 (0)
>+      length of EBX bit vector                 = 0x0 (0)
>    Architecture Performance Monitoring Features (0xa/ebx):
>       core cycle event not available           = false
>       instruction retired event not available  = false
>@@ -222,8 +222,8 @@
>       branch inst retired event not available  = false
>       branch mispred retired event not avail   = false
>    Architecture Performance Monitoring Features (0xa/edx):
>-      number of fixed counters    = 0x3 (3)
>-      bit width of fixed counters = 0x28 (40)
>+      number of fixed counters    = 0x0 (0)
>+      bit width of fixed counters = 0x0 (0)
>    extended feature flags (0x80000001/edx):
>       SYSCALL and SYSRET instructions        = true
>       execution disable                      = true

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Attachments on bug 223971: 188402 | 188407 | 188408