Attachment 197700 Details for Bug 218579 – WOL patch for stable/11

[patch] WOL patch for stable/11

stable11-bge.diff (text/plain), 5.80 KB, created by Cy Schubert on 2018-10-02 01:02:48 UTC

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Creator: Cy Schubert

Created: 2018-10-02 01:02:48 UTC

Size: 5.80 KB

patch

obsolete

>Index: sys/dev/bge/if_bge.c
>===================================================================
>--- sys/dev/bge/if_bge.c	(revision 339079)
>+++ sys/dev/bge/if_bge.c	(working copy)
>@@ -489,6 +489,8 @@
> static void bge_stop_fw(struct bge_softc *);
> static int bge_reset(struct bge_softc *);
> static void bge_link_upd(struct bge_softc *);
>+static void bge_setwol(struct bge_softc *);
>+static void bge_clrwol(struct bge_softc *);
> 
> static void bge_ape_lock_init(struct bge_softc *);
> static void bge_ape_read_fw_ver(struct bge_softc *);
>@@ -933,6 +935,7 @@
> static void
> bge_ape_driver_state_change(struct bge_softc *sc, int kind)
> {
>+	struct ifnet *ifp;
> 	uint32_t apedata, event;
> 
> 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
>@@ -965,9 +968,27 @@
> 		event = BGE_APE_EVENT_STATUS_STATE_START;
> 		break;
> 	case BGE_RESET_SHUTDOWN:
>-		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
>-		    BGE_APE_HOST_DRVR_STATE_UNLOAD);
>-		event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
>+                /* XXX  Needs rewording
>+                 * With the interface we are currently using,
>+                 * APE does not track driver state.  Wiping
>+                 * out the HOST SEGMENT SIGNATURE forces
>+                 * the APE to assume OS absent status.
>+                 */
>+		APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 0);
>+
>+		ifp = sc->bge_ifp;
>+		if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
>+		    APE_WRITE_4(sc, BGE_APE_HOST_WOL_SPEED,
>+			BGE_APE_HOST_WOL_SPEED_AUTO);
>+		    APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
>+			BGE_FW_DRV_STATE_WOL);
>+		    event = BGE_APE_EVENT_STATUS_STATE_WOL;
>+		    bge_ifmedia_upd_locked(ifp);
>+		} else {
>+		    APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
>+			BGE_APE_HOST_DRVR_STATE_UNLOAD);
>+		    event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
>+		}
> 		break;
> 	case BGE_RESET_SUSPEND:
> 		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
>@@ -3756,7 +3777,7 @@
> 	if_setsendqready(ifp);
> 	if_sethwassist(ifp, sc->bge_csum_features);
> 	if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
>-	    IFCAP_VLAN_MTU);
>+	    IFCAP_VLAN_MTU | IFCAP_WOL_MAGIC);
> 	if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
> 		if_sethwassistbits(ifp, CSUM_TSO, 0);
> 		if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
>@@ -3764,6 +3785,8 @@
> #ifdef IFCAP_VLAN_HWCSUM
> 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
> #endif
>+	if (pci_find_cap(dev, PCIY_PMG, &reg) == 0)
>+		if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0);
> 	if_setcapenable(ifp, if_getcapabilities(ifp));
> #ifdef DEVICE_POLLING
> 	if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
>@@ -3948,6 +3971,9 @@
> 		ether_ifdetach(ifp);
> 		device_printf(sc->bge_dev, "couldn't set up irq\n");
> 	}
>+	BGE_LOCK(sc);
>+	bge_clrwol(sc);
>+	BGE_UNLOCK(sc);
> 
> fail:
> 	if (error)
>@@ -5861,6 +5887,9 @@
> 			}
> 		}
> #endif
>+		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
>+			(if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0)
>+				if_togglecapenable(ifp, IFCAP_WOL_MAGIC);
> 		if ((mask & IFCAP_TXCSUM) != 0 &&
> 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
> 			if_togglecapenable(ifp, IFCAP_TXCSUM);
>@@ -6088,6 +6117,7 @@
> 
> 	sc = device_get_softc(dev);
> 	BGE_LOCK(sc);
>+	bge_setwol(sc);
> 	bge_stop(sc);
> 	BGE_UNLOCK(sc);
> 
>@@ -6101,6 +6131,7 @@
> 
> 	sc = device_get_softc(dev);
> 	BGE_LOCK(sc);
>+	bge_setwol(sc);
> 	bge_stop(sc);
> 	BGE_UNLOCK(sc);
> 
>@@ -6116,11 +6147,13 @@
> 	sc = device_get_softc(dev);
> 	BGE_LOCK(sc);
> 	ifp = sc->bge_ifp;
>+	bge_reset(sc);
> 	if (if_getflags(ifp) & IFF_UP) {
> 		bge_init_locked(sc);
> 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
> 			bge_start_locked(ifp);
> 	}
>+	bge_clrwol(sc);
> 	BGE_UNLOCK(sc);
> 
> 	return (0);
>@@ -6802,3 +6835,57 @@
> 		return (if_get_counter_default(ifp, cnt));
> 	}
> }
>+ 
>+static void
>+bge_setwol(struct bge_softc *sc)
>+{
>+	struct ifnet *ifp;
>+	uint16_t pmstat;
>+	int pmc;
>+
>+	ifp = sc->bge_ifp;
>+	if ((if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) == 0)
>+		return;
>+	if (pci_find_cap(sc->bge_dev, PCIY_PMG, &pmc) != 0)
>+		return;
>+	if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) {
>+		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB);
>+		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB);
>+		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
>+		BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
>+		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
>+	}
>+	else {
>+		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB);
>+		BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB);
>+	}
>+
>+	/* Request PME if WOL is requested. */
>+	pmstat = pci_read_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, 2);
>+	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
>+	if ((if_getcapenable(ifp) & IFCAP_WOL) != 0)
>+		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
>+	pci_write_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
>+}
>+
>+static void
>+bge_clrwol(struct bge_softc *sc)
>+{
>+	struct ifnet *ifp;
>+	uint16_t pmstat;
>+	int pmc;
>+
>+	ifp = sc->bge_ifp;
>+	if ((if_getcapabilities(ifp) & IFCAP_WOL) == 0)
>+		return;
>+	if (pci_find_cap(sc->bge_dev, PCIY_PMG, &pmc) != 0)
>+		return;
>+	if ((if_getcapenable(ifp) & IFCAP_WOL) == 0)
>+		return;
>+	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_MAGIC_PKT_ENB);
>+	BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_ACPI_PWRON_ENB);
>+
>+	pmstat = pci_read_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, 2);
>+	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
>+	pci_write_config(sc->bge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
>+}
>Index: sys/dev/bge/if_bgereg.h
>===================================================================
>--- sys/dev/bge/if_bgereg.h	(revision 339079)
>+++ sys/dev/bge/if_bgereg.h	(working copy)
>@@ -457,7 +457,8 @@
> #define	BGE_PCICLOCKCTL_ALTCLK		0x00001000
> #define	BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
> #define	BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
>-#define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000
>+#define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000 /* Disable the 133 MHz
>+						    * phase-locked loop */
> #define	BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
> 
>

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Attachments on bug 218579: 186870 | 191147 | 197700 | 212388 | 248615 | 248888 | 248890 | 248891 | 249663 | 249664