Attachment 207680 Details for Bug 240485 – Patch (Revision 2)

[patch] Patch (Revision 2)

cannon-lake-i2c-r2.patch (text/plain), 5.02 KB, created by Neel Chauhan on 2019-09-21 14:37:44 UTC

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Creator: Neel Chauhan

Created: 2019-09-21 14:37:44 UTC

Size: 5.02 KB

patch

obsolete

>Index: ig4_iic.c
>===================================================================
>--- ig4_iic.c	(revision 352459)
>+++ ig4_iic.c	(working copy)
>@@ -526,7 +526,8 @@
> 	sx_init(&sc->call_lock, "IG4 call lock");
> 
> 	v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
>-	if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) {
>+	if ((sc->version == IG4_SKYLAKE || sc->version == IG4_CANNONLAKE) &&
>+	    (v & IG4_RESTORE_REQUIRED) ) {
> 		reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);
> 		reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
> 
>@@ -556,7 +557,8 @@
> 	if (sc->version == IG4_HASWELL) {
> 		v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
> 		v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
>-	} else if (sc->version == IG4_SKYLAKE) {
>+	} else if (sc->version == IG4_SKYLAKE ||
>+		   sc->version == IG4_CANNONLAKE) {
> 		v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
> 		v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
> 	}
>@@ -590,7 +592,7 @@
> 	reg_write(sc, IG4_REG_SS_SCL_LCNT, 125);
> 	reg_write(sc, IG4_REG_FS_SCL_HCNT, 100);
> 	reg_write(sc, IG4_REG_FS_SCL_LCNT, 125);
>-	if (sc->version == IG4_SKYLAKE)
>+	if (sc->version == IG4_SKYLAKE || sc->version == IG4_CANNONLAKE)
> 		reg_write(sc, IG4_REG_SDA_HOLD, 28);
> 
> 	/*
>@@ -622,7 +624,8 @@
> 	if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
> 		reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
> 		reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
>-	} else if (sc->version = IG4_SKYLAKE) {
>+	} else if (sc->version == IG4_SKYLAKE ||
>+		   sc->version == IG4_CANNONLAKE) {
> 		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
> 		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
> 	}
>@@ -784,13 +787,15 @@
> 	if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
> 		REGDUMP(sc, IG4_REG_RESETS_HSW);
> 		REGDUMP(sc, IG4_REG_GENERAL);
>-	} else if (sc->version == IG4_SKYLAKE) {
>+	} else if (sc->version == IG4_SKYLAKE ||
>+		   sc->version == IG4_CANNONLAKE) {
> 		REGDUMP(sc, IG4_REG_RESETS_SKL);
> 	}
> 	if (sc->version == IG4_HASWELL) {
> 		REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
> 		REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
>-	} else if (sc->version == IG4_SKYLAKE) {
>+	} else if (sc->version == IG4_SKYLAKE ||
>+		   sc->version == IG4_CANNONLAKE) {
> 		REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
> 		REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
> 	}
>Index: ig4_pci.c
>===================================================================
>--- ig4_pci.c	(revision 352459)
>+++ ig4_pci.c	(working copy)
>@@ -82,6 +82,16 @@
> #define PCI_CHIP_SKYLAKE_I2C_5		0x9d658086
> #define PCI_CHIP_KABYLAKE_I2C_0		0xa1608086
> #define PCI_CHIP_KABYLAKE_I2C_1		0xa1618086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_0	0x9dc58086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_1	0x9dc68086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_2	0x9de88086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_3	0x9de98086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_4	0x9dea8086
>+#define PCI_CHIP_CANNONLAKE_LP_I2C_5	0x9deb8086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_0	0xa3688086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_1	0xa3698086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_2	0xa36a8086
>+#define PCI_CHIP_CANNONLAKE_H_I2C_3	0xa36b8086
> #define PCI_CHIP_APL_I2C_0		0x5aac8086
> #define PCI_CHIP_APL_I2C_1		0x5aae8086
> #define PCI_CHIP_APL_I2C_2		0x5ab08086
>@@ -114,6 +124,16 @@
> 	{ PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE},
> 	{ PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE},
> 	{ PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE},
>+        { PCI_CHIP_CANNONLAKE_LP_I2C_0, "Intel Cannon Lake-LP I2C Controller-0", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_LP_I2C_1, "Intel Cannon Lake-LP I2C Controller-1", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_LP_I2C_2, "Intel Cannon Lake-LP I2C Controller-2", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_LP_I2C_3, "Intel Cannon Lake-LP I2C Controller-3", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_LP_I2C_4, "Intel Cannon Lake-LP I2C Controller-4", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_LP_I2C_5, "Intel Cannon Lake-LP I2C Controller-5", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_H_I2C_0, "Intel Cannon Lake-H I2C Controller-0", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_H_I2C_1, "Intel Cannon Lake-H I2C Controller-1", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_H_I2C_2, "Intel Cannon Lake-H I2C Controller-2", IG4_CANNONLAKE},
>+        { PCI_CHIP_CANNONLAKE_H_I2C_3, "Intel Cannon Lake-H I2C Controller-3", IG4_CANNONLAKE},
> 	{ PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL},
> 	{ PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL},
> 	{ PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL},
>Index: ig4_var.h
>===================================================================
>--- ig4_var.h	(revision 352459)
>+++ ig4_var.h	(working copy)
>@@ -47,7 +47,7 @@
> #define IG4_RBUFMASK	(IG4_RBUFSIZE - 1)
> 
> enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE };
>-enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL };
>+enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_CANNONLAKE, IG4_APL };
> 
> struct ig4iic_softc {
> 	device_t	dev;

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Attachments on bug 240485: 207365 | 207680 | 207704 | 207864 | 207905 | 208154