Attachment 214731 Details for Bug 204521 – can read scr

[patch] can read scr

can_read_short.diff (text/plain), 16.72 KB, created by Jesper Schmitz Mouridsen on 2020-05-21 17:17:52 UTC

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Creator: Jesper Schmitz Mouridsen

Created: 2020-05-21 17:17:52 UTC

Size: 16.72 KB

patch

obsolete

>diff --git a/rtsx.c b/rtsx.c
>index 8082c25..2693cca 100644
>--- a/rtsx.c
>+++ b/rtsx.c
>@@ -1,4 +1,4 @@
>-/*
>+ï»¿/*
>  *
>  * Base on OpenBSD /sys/dev/pci/rtsx_pci.c & /dev/ic/rtsx.c
>  *      on Linux   /drivers/mmc/host/rtsx_pci_sdmmc.c,
>@@ -81,6 +81,10 @@
> 
> /* The softc holds our per-instance data. */
> struct rtsx_softc {
>+    int rtsx_double_clk;
>+    int rtsx_ssc_depth;
>+    int rtsx_vpclk;
>+    int rtsx_pcie_caps;
> 	struct mtx	rtsx_mtx;		/* device mutex */
> 	device_t	rtsx_dev;		/* device */
> 	int		rtsx_flags;		/* device flags */
>@@ -167,6 +171,7 @@ static void	rtsx_init_cmd(struct rtsx_softc *sc, struct mmc_command *cmd);
> static void	rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg,
> 			      uint8_t mask, uint8_t data);
> static int	rtsx_send_cmd(struct rtsx_softc *sc, struct mmc_command *cmd);
>+static int rtsx_send_pci_cmd(struct rtsx_softc *sc);
> static void	rtsx_send_cmd_nowait(struct rtsx_softc *sc, struct mmc_command *cmd);
> static void	rtsx_req_done(struct rtsx_softc *sc);
> static void	rtsx_soft_reset(struct rtsx_softc *sc);
>@@ -509,6 +514,13 @@ device_printf(sc->rtsx_dev, "FLAGS\n");
> device_printf(sc->rtsx_dev, "A\n");
> 		rtsx_handle_card_present(sc);
> 	}
>+#if 0
>+    if (sc->rtsx_req == NULL) {
>+        device_printf(sc->rtsx_dev, "B\n");
>+#if 0 /* might have been SD int */
>+        device_printf(sc->rtsx_dev, "Spurious interrupt - no active request\n");
>+#endif
>+
> 	if (sc->rtsx_req == NULL) {
> device_printf(sc->rtsx_dev, "B\n");
> #if 0 /* might have been SD int */
>@@ -517,6 +529,7 @@ device_printf(sc->rtsx_dev, "B\n");
> 		RTSX_UNLOCK(sc);
> 		return;
> 	}
>+#endif
> 	if (status & (RTSX_TRANS_OK_INT | RTSX_TRANS_FAIL_INT)) {
> 		sc->rtsx_intr_status |= status;
> 		wakeup(&sc->rtsx_intr_status);
>@@ -605,7 +618,11 @@ rtsx_init(struct rtsx_softc *sc)
> 
> 	if (bootverbose)
> 		device_printf(sc->rtsx_dev, "rtsx_init() rtsx_flags = 0x%04x\n", sc->rtsx_flags);
>-
>+    /* Power on SSC clock. */
>+    RTSX_CLR(sc, RTSX_FPDCTL, RTSX_SSC_POWER_DOWN);
>+    error=0;
>+    if (sc->rtsx_flags & RTSX_F_5209)
>+        error = rtsx_write_phy(sc, 0x00, 0xB966);
> 	/* Enable interrupt write-clear (default is read-clear). */
> 	RTSX_CLR(sc, RTSX_NFTS_TX_CTRL, RTSX_INT_READ_CLR);
> 
>@@ -800,6 +817,29 @@ rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val)
> 		
> 	return (0);
> }
>+static int rtsx_pci_write_register(struct rtsx_softc *sc, u_int16_t addr, u_int8_t mask, u_int8_t data)
>+{
>+    printf("%s %s %d 0x%x 0x%x 0x%x\n",__FILE__,__FUNCTION__,__LINE__,addr,mask,data);
>+    int i;
>+    u_int32_t val = RTSX_HAIMR_WRITE_START;
>+
>+    val |= (u_int32_t)(addr & 0x3FFF) << 16;
>+    val |= (u_int32_t)mask << 8;
>+    val |= (u_int32_t)data;
>+
>+    WRITE4(sc, RTSX_HAIMR, val);
>+
>+    for (i = 0; i < RTSX_MAX_RW_REG_CNT; i++) {
>+        val = READ4(sc, RTSX_HAIMR);
>+        if ((val & RTSX_HAIMR_TRANS_END) == 0) {
>+            if (data != (u_int8_t)val)
>+                return -EIO;
>+            return 0;
>+        }
>+    }
>+
>+    return -ETIMEDOUT;
>+}
> 
> /*
>  * Set or change SDCLK frequency or disable the SD clock.
>@@ -808,60 +848,99 @@ rtsx_write_phy(struct rtsx_softc *sc, uint8_t addr, uint16_t val)
> static int
> rtsx_set_sd_clock(struct rtsx_softc *sc, uint32_t freq)
> {
>-	uint8_t n;
>-	int div;
>-	int mcu;
>-	int error = 0;
>+    switch (sc->rtsx_host.ios.timing) {
>+    case bus_timing_uhs_sdr104:
>+    case bus_timing_uhs_sdr50:
>+        sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_2M;
>+        sc->rtsx_vpclk = 1;
>+        sc->rtsx_double_clk = 0;
>+        break;
>+    case bus_timing_mmc_ddr52:
>+    case bus_timing_uhs_ddr50:
>+    case bus_timing_uhs_sdr25:
>+        sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_1M;
>+        break;
>+    default:
>+        sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_500K;
>+        break;
>+    }
>+    int err, clk;
>+    u_int8_t n, clk_divider, mcu_cnt, div;
>+    int initial_mode = (sc->rtsx_host.ios.clock <= 1000000) ? 1 : 0;
>+
>+    if (initial_mode) {
>+        clk_divider = RTSX_SD_CLK_DIVIDE_128;
>+        freq = 30000000;
>+    } else {
>+        clk_divider = RTSX_SD_CLK_DIVIDE_0;
>+    }
>+    err = rtsx_pci_write_register(sc, RTSX_SD_CFG1,
>+                                  RTSX_SD_CLK_DIVIDE_MASK, clk_divider);
>+    if (err < 0)
>+        return err;
> 
>-	if (bootverbose)
>-		device_printf(sc->rtsx_dev, "rtsx_set_sd_clock(%u)\n", freq);
> 
>-	if (freq == RTSX_SDCLK_OFF) {
>-		error = rtsx_stop_sd_clock(sc);
>-		goto done;
>-	}
> 
>-	/* Round down to a supported frequency. */
>-	if (freq >= RTSX_SDCLK_50MHZ)
>-		freq = RTSX_SDCLK_50MHZ;
>-	else if (freq >= RTSX_SDCLK_25MHZ)
>-		freq = RTSX_SDCLK_25MHZ;
>-	else
>-		freq = RTSX_SDCLK_400KHZ;
>+    freq /= 1000000;
>+    device_printf(sc->rtsx_dev, "Switch card clock to %dMHz\n", freq);
> 
>-	/*
>-	 * Configure the clock frequency.
>-	 */
>-	switch (freq) {
>-	case RTSX_SDCLK_400KHZ:
>-		n = 80; /* minimum */
>-		div = RTSX_CLK_DIV_8;
>-		mcu = 7;
>-		RTSX_SET(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_128);
>-		break;
>-	case RTSX_SDCLK_25MHZ:
>-		n = 100;
>-		div = RTSX_CLK_DIV_4;
>-		mcu = 7;
>-		RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK);
>-		break;
>-	case RTSX_SDCLK_50MHZ:
>-		n = 100;
>-		div = RTSX_CLK_DIV_2;
>-		mcu = 7;
>-		RTSX_CLR(sc, RTSX_SD_CFG1, RTSX_CLK_DIVIDE_MASK);
>-		break;
>-	default:
>-		error = EINVAL;
>-		goto done;
>-	}
>+    clk = freq;
>+    if (!initial_mode)
>+        clk = freq * 2;
>+    device_printf(sc->rtsx_dev, "Internal SSC clock: %dMHz (cur_clock = %d)\n",
>+                  clk, sc->rtsx_host.ios.clock);
> 
>-	/*
>-	 * Enable SD clock.
>-	 */
>-	error = rtsx_switch_sd_clock(sc, n, div, mcu);
>-done:
>-	return error;
>+
>+    n = (u_int8_t)(clk - 2);
>+    if ((clk <= 2) || (n > RTSX_MAX_DIV_N_PCR))
>+        return -EINVAL;
>+
>+    mcu_cnt = (u_int8_t)(125/clk + 3);
>+    if (mcu_cnt > 15)
>+        mcu_cnt = 15;
>+
>+    /* Make sure that the SSC clock div_n is not less than MIN_DIV_N_PCR */
>+    div = RTSX_CLK_DIV_1;
>+    while ((n < RTSX_MIN_DIV_N_PCR) && (div < RTSX_CLK_DIV_8)) {
>+        n = (n + 2) * 2 - 2;
>+        div++;
>+    }
>+    device_printf(sc->rtsx_dev, "n = %d, div = %d\n", n, div);
>+
>+    sc->rtsx_ssc_depth = (sc->rtsx_ssc_depth> 1) ? (sc->rtsx_ssc_depth - 1) : sc->rtsx_ssc_depth;
>+    if (div > RTSX_CLK_DIV_1) {
>+        if (sc->rtsx_ssc_depth > (div - 1))
>+            sc->rtsx_ssc_depth -= (div - 1);
>+        else
>+            sc->rtsx_ssc_depth = RTSX_SSC_DEPTH_4M;
>+    }
>+    RTSX_LOCK(sc);
>+    sc->rtsx_cmd_index=0;
>+
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CLK_CTL,
>+                  RTSX_CLK_LOW_FREQ, RTSX_CLK_LOW_FREQ);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CLK_DIV,
>+                  0xFF, (div << 4) | mcu_cnt);
>+    device_printf(sc->rtsx_dev,"ssc depth 0x%x\n",sc->rtsx_ssc_depth);
>+
>+
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SSC_CTL1, RTSX_SSC_RSTB, 0);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SSC_CTL2,
>+                  RTSX_SSC_DEPTH_MASK, sc->rtsx_ssc_depth);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SSC_DIV_N_0, 0xFF, n);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SSC_CTL1, RTSX_SSC_RSTB, RTSX_SSC_RSTB);
>+    err = rtsx_send_pci_cmd(sc);
>+    RTSX_UNLOCK(sc);
>+    if (err > 0)
>+        return err;
>+
>+    /* Wait SSC clock stable */
>+    DELAY(200);
>+    err = rtsx_pci_write_register(sc, RTSX_CLK_CTL, RTSX_CLK_LOW_FREQ, 0);
>+    if (err < 0)
>+        return err;
>+    sc->rtsx_host.ios.clock=freq;
>+    return 0;
> }
> 
> static int
>@@ -1293,7 +1372,31 @@ rtsx_push_cmd(struct rtsx_softc *sc, uint8_t cmd, uint16_t reg,
> 	---*/
> 
> }
>-
>+static int
>+rtsx_send_pci_cmd(struct rtsx_softc *sc)
>+{
>+    int error = 0;
>+
>+    if (bootverbose)
>+        device_printf(sc->rtsx_dev, "rtsx_send_pci_cmd()\n");
>+
>+    sc->rtsx_intr_status = 0;
>+
>+    /* Sync command DMA buffer. */
>+    bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREREAD);
>+    bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_PREWRITE);
>+    /* Tell the chip where the command buffer is and run the commands. */
>+    WRITE4(sc, RTSX_HCBAR, (uint32_t)sc->rtsx_cmd_buffer);
>+    WRITE4(sc, RTSX_HCBCTLR,
>+           ((sc->rtsx_cmd_index * 4 & 0x00ffffff) | RTSX_START_CMD | RTSX_HW_AUTO_RSP));
>+    if ((error = rtsx_wait_intr(sc, RTSX_TRANS_OK_INT, hz * sc->rtsx_timeout))) {
>+        printf("ERRPR 0x%x\n",*((u_int32_t*)sc->rtsx_cmd_dmamem));
>+        return error;
>+    }
>+    bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTREAD);
>+    bus_dmamap_sync(sc->rtsx_cmd_dma_tag, sc->rtsx_cmd_dmamap, BUS_DMASYNC_POSTWRITE);
>+    return (error);
>+}
> /* Run the command queue and wait for completion. */
> static int
> rtsx_send_cmd(struct rtsx_softc *sc, struct mmc_command *cmd)
>@@ -1464,92 +1567,74 @@ rtsx_send_req_get_resp(struct rtsx_softc *sc, struct mmc_command *cmd) {
> static int
> rtsx_xfer_short(struct rtsx_softc *sc, struct mmc_command *cmd)
> {
>-	uint8_t rsp_type;
>-	int read;
>-	int tmode;
>-	int error = 0;
>+    int err;
>+    u_int8_t trans_mode;
> 
>-	if (cmd->data->xfer_len == 0)
>-		cmd->data->xfer_len = (cmd->data->len > RTSX_MAX_DATA_BLKLEN) ?
>-			RTSX_MAX_DATA_BLKLEN : cmd->data->len;
>-				
>-	if (bootverbose)
>-		device_printf(sc->rtsx_dev, "rtsx_xfer_short(): %ld bytes with block size %ld\n",
>-			      cmd->data->len, cmd->data->xfer_len);
>+    device_printf(sc->rtsx_dev, "%s: SD/MMC CMD %d, arg = 0x%08x\n",
>+                  __FUNCTION__, cmd->opcode, cmd->arg);
>+    //buf = malloc(sizeof(u_int32_t)*cmd->data->len, M_RTSX,	M_NOWAIT);
> 
>-	if (cmd->data->len > 512) {
>-		device_printf(sc->rtsx_dev, "rtsx_xfer_short() length too large: %ld > 512\n",
>-			      cmd->data->len);
>-		cmd->error = MMC_ERR_FAILED;
>-		return ENOMEM;
>-	}
>+    if (cmd->data->flags & MMC_DATA_READ) {
>+        int initial_mode = (sc->rtsx_host.ios.clock <= 1000000) ? 1 : 0;
>+        if(initial_mode)
>+            rtsx_pci_write_register(sc, RTSX_SD_CFG1,
>+                                    RTSX_SD_CLK_DIVIDE_MASK, RTSX_SD_CLK_DIVIDE_0);
>+        else
>+            rtsx_pci_write_register(sc, RTSX_SD_CFG1,
>+                                    RTSX_SD_CLK_DIVIDE_MASK, RTSX_SD_CLK_DIVIDE_128);
> 
>-	rsp_type = rtsx_response_type(cmd->flags & MMC_RSP_MASK);
>-	if (rsp_type == 0) {
>-		device_printf(sc->rtsx_dev, "Unknown response type 0x%lx\n", (cmd->flags & MMC_RSP_MASK));
>-		cmd->error = MMC_ERR_FAILED;
>-		return (EINVAL);
>-	}
>-	
>-	read = ISSET(cmd->data->flags, MMC_DATA_READ);
>-	if (!read && cmd->data != NULL && cmd->data->len > 0) {
>-		error = rtsx_write_ppbuf(sc, cmd);
>-		if (error)
>-			return (error);
>-	}
>-	rtsx_init_cmd(sc, cmd);
> 
>-	/* Queue commands to configure data transfer size. */
>-	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L,
>-		      0xff, (cmd->data->xfer_len & 0xff));
>-	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H,
>-		      0xff, (cmd->data->xfer_len >> 8));
>-	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L,
>-		      0xff, ((cmd->data->len / cmd->data->xfer_len) & 0xff));
>-	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H,
>-		      0xff, ((cmd->data->len / cmd->data->xfer_len) >> 8));
> 
>-	/* Queue command to set response type. */
>-	/*--- from netbsd ---
>-	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
>-		      0xff, rsp_type);
>-	---*/
> 
>-	/* from linux: rtsx_pci_sdmmc.c sd_read_data() */
>-	rtsx_push_cmd(sc,  RTSX_WRITE_REG_CMD, RTSX_SD_CFG2,
>-		      0xff, RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 |
>-		      RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6);
>-	
>-	/* Use the ping-pong buffer (cmd buffer). */
>-	if (read)
>-		rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_CARD_DATA_SOURCE,
>-			      0x01, RTSX_PINGPONG_BUFFER);
> 
>-	/* Queue commands to perform SD transfer. */
>-	tmode = read ? RTSX_TM_NORMAL_READ : RTSX_TM_AUTO_WRITE2;
>-	rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
>-		      0xff, tmode | RTSX_SD_TRANSFER_START);
>-	rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
>-		      RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END);
> 
>-	/* Run the command queue and wait for completion. */
>-	if ((error = rtsx_send_cmd(sc, cmd)))
>-		return (error);
>+    }
> 
>-	if (read && cmd->data != NULL && cmd->data->len > 0) {
>-		error = rtsx_read_ppbuf(sc, cmd);
>-	}
>+    trans_mode = RTSX_SD_TM_NORMAL_READ;
>+
>+    sc->rtsx_cmd_index=0;
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD0, 0xFF,
>+                  RTSX_SD_CMD_START | cmd->opcode);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD1,     0xFF, cmd->arg >> 24);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD2, 0xFF, cmd->arg >> 16);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD3 , 0xFF, cmd->arg >> 8);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CMD4 , 0xFF, cmd->arg);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_L, 0xFF, 1);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BLOCK_CNT_H, 0xFF, 1 >> 8);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_L, 0xFF, cmd->data->len);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_BYTE_CNT_H, 0xFF, cmd->data->len >> 8);
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_CFG2, 0xFF,
>+                  RTSX_SD_CALCULATE_CRC7 | RTSX_SD_CHECK_CRC16 |
>+                  RTSX_SD_NO_WAIT_BUSY_END | RTSX_SD_CHECK_CRC7 | RTSX_SD_RSP_LEN_6);
>+
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD,
>+                  RTSX_CARD_DATA_SOURCE, 0x01, RTSX_PINGPONG_BUFFER);
>+
>+    rtsx_push_cmd(sc, RTSX_WRITE_REG_CMD, RTSX_SD_TRANSFER,
>+                  0xFF, trans_mode | RTSX_SD_TRANSFER_START);
>+    rtsx_push_cmd(sc, RTSX_CHECK_REG_CMD, RTSX_SD_TRANSFER,
>+                  RTSX_SD_TRANSFER_END, RTSX_SD_TRANSFER_END);
>+
>+    err = rtsx_send_pci_cmd(sc);
>+
>+    if (err != 0) {
>+        device_printf(sc->rtsx_dev,
>+                      "rtsx_pci_send_cmd fail (err = %d)\n", err);
>+        return err;
>+    }
> 
>-	if (bootverbose) {
>-		uint32_t *data = (uint32_t *)cmd->data->data;
>-		int i;
>-		int n = (cmd->data->len > 64) ? 8 : ((cmd->data->len - 1) / 4) + 1;
>-		device_printf(sc->rtsx_dev, "rtsx_xfer_short():\n");
>-		for (i = 0; i < n; i++)
>-			device_printf(sc->rtsx_dev, "\t\t\t0x%08x\n", data[i]);
>-	}
> 
>-	return (error);
>+    if(err==0) {
>+        err = rtsx_read_ppbuf(sc, cmd);
>+
>+        if (err > 0) {
>+            device_printf(sc->rtsx_dev,
>+                          "rtsx_pci_read_ppbuf fail (err = %d)\n", err);
>+            return err;
>+        }
>+        return err;
>+    }
>+    return err;
> }
> 
> /* Use ping-pong buffer (cmd buffer) for transfer */
>diff --git a/rtsxreg.h b/rtsxreg.h
>index f76f423..6612494 100644
>--- a/rtsxreg.h
>+++ b/rtsxreg.h
>@@ -56,6 +56,13 @@
> #define	RTSX_HAIMR		0x10
> #define	RTSX_HAIMR_WRITE	0x40000000
> #define	RTSX_HAIMR_BUSY		0x80000000
>+#define RTSX_MAX_RW_REG_CNT                     1024
>+#define   RTSX_HAIMR_TRANS_START                (0x01 << 31)
>+#define   RTSX_HAIMR_READ                       0x00
>+#define   RTSX_HAIMR_READ_START         (RTSX_HAIMR_TRANS_START | RTSX_HAIMR_READ)
>+#define   RTSX_HAIMR_WRITE_START                (RTSX_HAIMR_TRANS_START | RTSX_HAIMR_WRITE)
>+#define   RTSX_HAIMR_TRANS_END                  (RTSX_HAIMR_TRANS_START)
>+#define   RTSX_HAIMR_TRANS_END                  (RTSX_HAIMR_TRANS_START)
> 
> /* Interrupt enable register. */
> #define	RTSX_BIER		0x18
>@@ -84,7 +91,11 @@
> #define	RTSX_SD_PARTIAL_PWR_ON		0x01
> #define	RTSX_SD_PWR_OFF			0x03
> #define	RTSX_SD_PWR_MASK		0x03
>-
>+#define RTSX_LDO3318_PWR_MASK		0x06
>+#define RTSX_SD_PARTIAL_POWER_ON		0x01
>+#define   RTSX_SD_POWER_ON			0x00
>+#define   RTSX_SD_POWER_MASK			0x03
>+#define	RTSX_LDO3318_ON			0x00
> #define	RTSX_PMOS_STRG_MASK		0x10
> #define	RTSX_PMOS_STRG_400mA		0x00
> #define	RTSX_PMOS_STRG_800mA		0x10
>@@ -99,7 +110,7 @@
> #define	RTSX_MS_PWR_OFF			0x0C
> #define	RTSX_MS_PWR_ON			0x00
> #define	RTSX_MS_PARTIAL_PWR_ON		0x04
>-
>+#define	RTSX_SD_PARTIAL_PWR_ON		0x01
> #define RTSX_RTL8411B_PACKAGE		0xFD51
> #define RTSX_RTL8411B_QFN48		0x02
> 
>@@ -122,9 +133,23 @@
> #define RTSX_SDIO_BUS_CTRL		0x01
> #define RTSX_SDIO_CD_CTRL		0x02
> 
>-#define RTSX_CARD_PAD_CTL		0xFD73
>+#define RTSX_SSC_RSTB			0x80
>+#define    RTSX_SSC_DEPTH_4M			0x01
>+#define    RTSX_SSC_DEPTH_2M			0x02
>+#define    RTSX_SSC_DEPTH_1M			0x03
>+#define    RTSX_SSC_DEPTH_500K		0x04
>+#define    RTSX_SSC_DEPTH_250K		0x05
> 
>-/* Internal clock. */
>+
>+
>+#define RTSX_CARD_PAD_CTL		0xFD73
>+#define RTSX_SD_CLK_DIVIDE_0		0x00
>+#define RTSX_SD_CLK_DIVIDE_256		0xC0
>+#define RTSX_SD_CLK_DIVIDE_128		0x80
>+#define RTSX_CARD_PAD_CTL		0xFD73
>+#define RTSX_SD_CLK_DIVIDE_MASK		0xC0
>+#define RTSX_MAX_DIV_N_PCR		208
>+#define RTSX_MIN_DIV_N_PCR		80/* Internal clock. */
> #define	RTSX_CLK_CTL			0xFC02
> #define	RTSX_CLK_LOW_FREQ		0x01
> 
>@@ -401,7 +426,7 @@
> #define	RTSX_SPI_OUTPUT_EN		0x10
> #define	RTSX_CARD_OUTPUT_EN		(RTSX_XD_OUTPUT_EN|RTSX_SD_OUTPUT_EN|\
> 					 RTSX_MS_OUTPUT_EN)
>-
>+#define RTSX_SD_TM_NORMAL_READ		0x0C
> #define	RTSX_CARD_GPIO_DIR		0xFD57
> #define	RTSX_CARD_GPIO			0xFD58
> #define	RTSX_CARD_GPIO_LED_OFF		0x01
>@@ -415,6 +440,8 @@
> #define	RTSX_SD_MOD_SEL			0x02
> #define	RTSX_MS_MOD_SEL			0x03
> #define	RTSX_SPI_MOD_SEL		0x04
>+#define RTSX_CARD_SHARE_MASK  0x0F
>+#define RTSX_CARD_SHARE_48_SD           0x04
> 
> /* ping-pong buffer 2 */
> #define	RTSX_PPBUF_BASE2		0xFA00

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Attachments on bug 204521: 209887 | 214731 | 214733 | 214797 | 214840 | 214925 | 214987 | 214992 | 215518 | 215853 | 215874 | 215893 | 215894