Attachment 224620 Details for Bug 255556 – Add PCI IDs for Intel Apollo Lake Series HSUARTs.

[patch] Add PCI IDs for Intel Apollo Lake Series HSUARTs.

0001-Add-Apollo-Lake-SIO-LPSS-UARTs-PCI-IDs.patch (text/plain), 3.05 KB, created by Jose Luis Duran on 2021-05-02 21:27:57 UTC

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Creator: Jose Luis Duran

Created: 2021-05-02 21:27:57 UTC

Size: 3.05 KB

patch

obsolete

>From 2a889ffaa34714ed978a87fbc4307c1829bbad32 Mon Sep 17 00:00:00 2001
>From: Jose Luis Duran <jlduran@gmail.com>
>Date: Sun, 2 May 2021 21:20:25 -0000
>Subject: [PATCH] Add Apollo Lake SIO/LPSS UARTs PCI IDs
>
>Add PCI IDs for Intel Apollo Lake Series HSUARTs:
>
>    # pciconf -ll
>    drv   selector      class    rev  hdr  vendor device subven subdev
>    uart0@pci0:0:24:0:  118000   0b   00   8086   5abc   8086   7270
>    uart1@pci0:0:24:1:  118000   0b   00   8086   5abe   8086   7270
>    uart2@pci0:0:24:2:  118000   0b   00   8086   5ac0   8086   7270
>    uart3@pci0:0:24:3:  118000   0b   00   8086   5aee   8086   7270
>
>NB (Intel Document Number 336256-004US):
>1. The E3900 and A3900 Series Processors support four LPSS_UART ports,
>   while the N- and J- Series Processors support only LPSS_UART [2:1]
>   ports.
>2. The LPSS_UART1 port is dedicated for discrete Global Navigation
>   Satellite System (GNSS).  This port can be used for generic UART
>   functionality if GNSS is not used.
>3. The LPSS_UART2 port is dedicated for host OS debug.
>4. The LPSS_UART0 and LPSS_UART3 ports are for generic UART functionality.
>5. Only UART [1:0] ports support DMA.
>---
> sys/dev/uart/uart_bus_pci.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
>diff --git a/sys/dev/uart/uart_bus_pci.c b/sys/dev/uart/uart_bus_pci.c
>index fbd1d68b88c..707b82dc078 100644
>--- a/sys/dev/uart/uart_bus_pci.c
>+++ b/sys/dev/uart/uart_bus_pci.c
>@@ -135,17 +135,26 @@ static const struct pci_id pci_ns8250_ids[] = {
> { 0x8086, 0x108f, 0xffff, 0, "Intel AMT - SOL", 0x10 },
> { 0x8086, 0x19d8, 0xffff, 0, "Intel Denverton UART", 0x10 },
> { 0x8086, 0x1c3d, 0xffff, 0, "Intel AMT - KT Controller", 0x10 },
>-{ 0x8086, 0x1d3d, 0xffff, 0, "Intel C600/X79 Series Chipset KT Controller", 0x10 },
>+{ 0x8086, 0x1d3d, 0xffff, 0, "Intel C600/X79 Series Chipset KT Controller",
>+	0x10 },
> { 0x8086, 0x1e3d, 0xffff, 0, "Intel Panther Point KT Controller", 0x10 },
> { 0x8086, 0x228a, 0xffff, 0, "Intel Cherryview SIO HSUART#1", 0x10,
>-       24 * DEFAULT_RCLK, 2 },
>+	24 * DEFAULT_RCLK, 2 },
> { 0x8086, 0x228c, 0xffff, 0, "Intel Cherryview SIO HSUART#2", 0x10,
>-       24 * DEFAULT_RCLK, 2 },
>+	24 * DEFAULT_RCLK, 2 },
> { 0x8086, 0x2a07, 0xffff, 0, "Intel AMT - PM965/GM965 KT Controller", 0x10 },
> { 0x8086, 0x2a47, 0xffff, 0, "Mobile 4 Series Chipset KT Controller", 0x10 },
> { 0x8086, 0x2e17, 0xffff, 0, "4 Series Chipset Serial KT Controller", 0x10 },
> { 0x8086, 0x3b67, 0xffff, 0, "5 Series/3400 Series Chipset KT Controller",
> 	0x10 },
>+{ 0x8086, 0x5abc, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 0", 0x10,
>+	24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x5abe, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 1", 0x10,
>+	24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x5ac0, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 2", 0x10,
>+	24 * DEFAULT_RCLK, 2 },
>+{ 0x8086, 0x5aee, 0xffff, 0, "Intel Apollo Lake SIO/LPSS UART 3", 0x10,
>+	24 * DEFAULT_RCLK, 2 },
> { 0x8086, 0x8811, 0xffff, 0, "Intel EG20T Serial Port 0", 0x10 },
> { 0x8086, 0x8812, 0xffff, 0, "Intel EG20T Serial Port 1", 0x10 },
> { 0x8086, 0x8813, 0xffff, 0, "Intel EG20T Serial Port 2", 0x10 },
>-- 
>2.31.1
>

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Attachments on bug 255556: 224620