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Lines 183-188
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| 183 |
device_printf(dev, "%s\n",buf); |
183 |
device_printf(dev, "%s\n",buf); |
| 184 |
} |
184 |
} |
| 185 |
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185 |
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186 |
/* |
| 187 |
* According to the docs for the TI chipset, this will work with any YENTA |
| 188 |
* conforming card bus bridge. |
| 189 |
*/ |
| 190 |
static void |
| 191 |
ti12xx_legacy_init(device_t self) |
| 192 |
{ |
| 193 |
u_long bcr; /* to set interrupts */ |
| 194 |
u_short io_port; /* the io_port to map this slot on */ |
| 195 |
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| 196 |
/* |
| 197 |
* First, just to be "safe", we muck with the power registers |
| 198 |
* to put the chip into D0 power state. But read the power |
| 199 |
* management capabilities register first and only do it for |
| 200 |
* version 1 cards. |
| 201 |
*/ |
| 202 |
if ((pci_read_config(self, 0xa2, 2) & 0x7) == 0x1) { |
| 203 |
pci_write_config(self, 0xa4, |
| 204 |
pci_read_config(self, 0xa4, 2) & ~0x3, 2); |
| 205 |
} |
| 206 |
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| 207 |
/* |
| 208 |
* Only set legecay mode on first card. This will have |
| 209 |
* functions 0 and 1 and will probe as units 0 and 1. |
| 210 |
*/ |
| 211 |
if (device_get_unit(self) > 1) |
| 212 |
return; |
| 213 |
|
| 214 |
/* |
| 215 |
* Set legacy I/O address to 0x3e0. Only need to do this |
| 216 |
* for first function/unit. |
| 217 |
*/ |
| 218 |
if (device_get_unit(self) != 0) { |
| 219 |
io_port = PCIC_INDEX_0; |
| 220 |
pci_write_config(self, CLPD6832_LEGACY_16BIT_IOADDR, |
| 221 |
io_port & ~PCI_MAP_IO, 4); |
| 222 |
} |
| 223 |
|
| 224 |
/* |
| 225 |
* Set default operating mode (I/O port space, Parity error enable |
| 226 |
* and busmaster). |
| 227 |
*/ |
| 228 |
pci_write_config(self, PCI_COMMAND_STATUS_REG, |
| 229 |
pci_read_config(self, PCI_COMMAND_STATUS_REG, 2) | 0x47, 2); |
| 230 |
|
| 231 |
/* |
| 232 |
* Enable isa-style IRQ interrupts. |
| 233 |
*/ |
| 234 |
bcr = pci_read_config(self, 0x3e, 2); |
| 235 |
bcr |= 0x84; |
| 236 |
pci_write_config(self, 0x3e, bcr, 2); |
| 237 |
} |
| 238 |
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| 186 |
static void |
239 |
static void |
| 187 |
generic_cardbus_attach(device_t dev) |
240 |
generic_cardbus_attach(device_t dev) |
| 188 |
{ |
241 |
{ |
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Lines 333-346
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| 333 |
pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); |
386 |
pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); |
| 334 |
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387 |
|
| 335 |
switch (device_id) { |
388 |
switch (device_id) { |
| 336 |
case PCI_DEVICE_ID_PCIC_TI1130: |
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| 337 |
case PCI_DEVICE_ID_PCIC_TI1131: |
| 338 |
case PCI_DEVICE_ID_PCIC_TI1220: |
389 |
case PCI_DEVICE_ID_PCIC_TI1220: |
| 339 |
case PCI_DEVICE_ID_PCIC_TI1221: |
390 |
case PCI_DEVICE_ID_PCIC_TI1221: |
| 340 |
case PCI_DEVICE_ID_PCIC_TI1250: |
391 |
case PCI_DEVICE_ID_PCIC_TI1250: |
| 341 |
case PCI_DEVICE_ID_PCIC_TI1251: |
392 |
case PCI_DEVICE_ID_PCIC_TI1251: |
| 342 |
case PCI_DEVICE_ID_PCIC_TI1251B: |
393 |
case PCI_DEVICE_ID_PCIC_TI1251B: |
| 343 |
case PCI_DEVICE_ID_PCIC_TI1225: |
394 |
case PCI_DEVICE_ID_PCIC_TI1225: |
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395 |
ti12xx_legacy_init(dev); |
| 396 |
case PCI_DEVICE_ID_PCIC_TI1130: |
| 397 |
case PCI_DEVICE_ID_PCIC_TI1131: |
| 344 |
case PCI_DEVICE_ID_PCIC_TI1410: |
398 |
case PCI_DEVICE_ID_PCIC_TI1410: |
| 345 |
case PCI_DEVICE_ID_PCIC_TI1420: |
399 |
case PCI_DEVICE_ID_PCIC_TI1420: |
| 346 |
case PCI_DEVICE_ID_PCIC_TI1450: |
400 |
case PCI_DEVICE_ID_PCIC_TI1450: |