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Lines 55-60
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| 55 |
* 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) |
55 |
* 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) |
| 56 |
* 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) |
56 |
* 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) |
| 57 |
* 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) |
57 |
* 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) |
|
|
58 |
* 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI) |
| 58 |
* Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 |
59 |
* Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 |
| 59 |
* Dell on-board 3c920 10/100Mbps/RJ-45 |
60 |
* Dell on-board 3c920 10/100Mbps/RJ-45 |
| 60 |
* Dell Precision on-board 3c905B 10/100Mbps/RJ-45 |
61 |
* Dell Precision on-board 3c905B 10/100Mbps/RJ-45 |
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Lines 184-189
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| 184 |
"3Com 3cSOHO100-TX OfficeConnect" }, |
185 |
"3Com 3cSOHO100-TX OfficeConnect" }, |
| 185 |
{ TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, |
186 |
{ TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, |
| 186 |
"3Com 3c450-TX HomeConnect" }, |
187 |
"3Com 3c450-TX HomeConnect" }, |
|
|
188 |
{ TC_VENDORID, TC_DEVICEID_MINIPCI_556B, |
| 189 |
"3Com 3c556B MINIPCI-TX" }, |
| 187 |
{ 0, 0, NULL } |
190 |
{ 0, 0, NULL } |
| 188 |
}; |
191 |
}; |
| 189 |
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192 |
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Lines 530-535
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| 530 |
struct xl_softc *sc; |
533 |
struct xl_softc *sc; |
| 531 |
struct xl_mii_frame frame; |
534 |
struct xl_mii_frame frame; |
| 532 |
|
535 |
|
|
|
536 |
sc = device_get_softc(dev); |
| 537 |
|
| 533 |
/* |
538 |
/* |
| 534 |
* Pretend that PHYs are only available at MII address 24. |
539 |
* Pretend that PHYs are only available at MII address 24. |
| 535 |
* This is to guard against problems with certain 3Com ASIC |
540 |
* This is to guard against problems with certain 3Com ASIC |
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Lines 537-547
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| 537 |
* control registers at all MII addresses. This can cause |
542 |
* control registers at all MII addresses. This can cause |
| 538 |
* the miibus code to attach the same PHY several times over. |
543 |
* the miibus code to attach the same PHY several times over. |
| 539 |
*/ |
544 |
*/ |
| 540 |
if (phy != 24) |
545 |
if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) |
| 541 |
return(0); |
546 |
return(0); |
| 542 |
|
547 |
|
| 543 |
sc = device_get_softc(dev); |
|
|
| 544 |
|
| 545 |
bzero((char *)&frame, sizeof(frame)); |
548 |
bzero((char *)&frame, sizeof(frame)); |
| 546 |
|
549 |
|
| 547 |
frame.mii_phyaddr = phy; |
550 |
frame.mii_phyaddr = phy; |
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Lines 558-568
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| 558 |
struct xl_softc *sc; |
561 |
struct xl_softc *sc; |
| 559 |
struct xl_mii_frame frame; |
562 |
struct xl_mii_frame frame; |
| 560 |
|
563 |
|
| 561 |
if (phy != 24) |
|
|
| 562 |
return(0); |
| 563 |
|
| 564 |
sc = device_get_softc(dev); |
564 |
sc = device_get_softc(dev); |
| 565 |
|
565 |
|
|
|
566 |
if ((!(sc->xl_flags & XL_FLAG_PHYOK)) && phy != 24) |
| 567 |
return(0); |
| 568 |
|
| 566 |
bzero((char *)&frame, sizeof(frame)); |
569 |
bzero((char *)&frame, sizeof(frame)); |
| 567 |
|
570 |
|
| 568 |
frame.mii_phyaddr = phy; |
571 |
frame.mii_phyaddr = phy; |
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Lines 684-697
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| 684 |
{ |
687 |
{ |
| 685 |
int err = 0, i; |
688 |
int err = 0, i; |
| 686 |
u_int16_t word = 0, *ptr; |
689 |
u_int16_t word = 0, *ptr; |
| 687 |
|
690 |
#define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) |
|
|
691 |
/* WARNING! DANGER! |
| 692 |
* It's easy to accidentally overwrite the rom content! |
| 693 |
* Note: the 3c575 uses 8bit EEPROM offsets. |
| 694 |
*/ |
| 688 |
XL_SEL_WIN(0); |
695 |
XL_SEL_WIN(0); |
| 689 |
|
696 |
|
| 690 |
if (xl_eeprom_wait(sc)) |
697 |
if (xl_eeprom_wait(sc)) |
| 691 |
return(1); |
698 |
return(1); |
| 692 |
|
699 |
|
|
|
700 |
if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) |
| 701 |
off += 0x30; |
| 702 |
|
| 693 |
for (i = 0; i < cnt; i++) { |
703 |
for (i = 0; i < cnt; i++) { |
| 694 |
CSR_WRITE_2(sc, XL_W0_EE_CMD, XL_EE_READ | (off + i)); |
704 |
CSR_WRITE_2(sc, XL_W0_EE_CMD, XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); |
| 695 |
err = xl_eeprom_wait(sc); |
705 |
err = xl_eeprom_wait(sc); |
| 696 |
if (err) |
706 |
if (err) |
| 697 |
break; |
707 |
break; |
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Lines 982-988
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| 982 |
register int i; |
992 |
register int i; |
| 983 |
|
993 |
|
| 984 |
XL_SEL_WIN(0); |
994 |
XL_SEL_WIN(0); |
| 985 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET); |
995 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | |
|
|
996 |
((sc->xl_flags & XL_FLAG_WEIRDRESET)?0xFF:0)); |
| 986 |
|
997 |
|
| 987 |
for (i = 0; i < XL_TIMEOUT; i++) { |
998 |
for (i = 0; i < XL_TIMEOUT; i++) { |
| 988 |
DELAY(10); |
999 |
DELAY(10); |
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Lines 1184-1189
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| 1184 |
sc = device_get_softc(dev); |
1195 |
sc = device_get_softc(dev); |
| 1185 |
unit = device_get_unit(dev); |
1196 |
unit = device_get_unit(dev); |
| 1186 |
|
1197 |
|
|
|
1198 |
sc->xl_flags = 0; |
| 1199 |
switch (pci_get_device(dev)) { |
| 1200 |
case TC_DEVICEID_MINIPCI_556B: |
| 1201 |
sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET; |
| 1202 |
} |
| 1203 |
|
| 1187 |
/* |
1204 |
/* |
| 1188 |
* If this is a 3c905B, we have to check one extra thing. |
1205 |
* If this is a 3c905B, we have to check one extra thing. |
| 1189 |
* The 905B supports power management and may be placed in |
1206 |
* The 905B supports power management and may be placed in |
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Lines 1262-1273
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| 1262 |
sc->xl_btag = rman_get_bustag(sc->xl_res); |
1279 |
sc->xl_btag = rman_get_bustag(sc->xl_res); |
| 1263 |
sc->xl_bhandle = rman_get_bushandle(sc->xl_res); |
1280 |
sc->xl_bhandle = rman_get_bushandle(sc->xl_res); |
| 1264 |
|
1281 |
|
|
|
1282 |
if (sc->xl_flags & XL_FLAG_FUNCREG) { |
| 1283 |
rid = XL_PCI_FUNCMEM; |
| 1284 |
sc->xl_fres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, |
| 1285 |
0, ~0, 1, RF_ACTIVE); |
| 1286 |
|
| 1287 |
if (sc->xl_fres == NULL) { |
| 1288 |
printf ("xl%d: couldn't map ports/memory\n", unit); |
| 1289 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
| 1290 |
error = ENXIO; |
| 1291 |
goto fail; |
| 1292 |
} |
| 1293 |
|
| 1294 |
sc->xl_ftag = rman_get_bustag(sc->xl_fres); |
| 1295 |
sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); |
| 1296 |
} |
| 1297 |
|
| 1265 |
rid = 0; |
1298 |
rid = 0; |
| 1266 |
sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, |
1299 |
sc->xl_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, |
| 1267 |
RF_SHAREABLE | RF_ACTIVE); |
1300 |
RF_SHAREABLE | RF_ACTIVE); |
| 1268 |
|
1301 |
|
| 1269 |
if (sc->xl_irq == NULL) { |
1302 |
if (sc->xl_irq == NULL) { |
| 1270 |
printf("xl%d: couldn't map interrupt\n", unit); |
1303 |
printf("xl%d: couldn't map interrupt\n", unit); |
|
|
1304 |
bus_release_resource(dev, SYS_RES_MEMORY, XL_PCI_FUNCMEM, sc->xl_fres); |
| 1271 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
1305 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
| 1272 |
error = ENXIO; |
1306 |
error = ENXIO; |
| 1273 |
goto fail; |
1307 |
goto fail; |
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Lines 1278-1283
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| 1278 |
|
1312 |
|
| 1279 |
if (error) { |
1313 |
if (error) { |
| 1280 |
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); |
1314 |
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); |
|
|
1315 |
bus_release_resource(dev, SYS_RES_MEMORY, XL_PCI_FUNCMEM, sc->xl_fres); |
| 1281 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
1316 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
| 1282 |
printf("xl%d: couldn't set up irq\n", unit); |
1317 |
printf("xl%d: couldn't set up irq\n", unit); |
| 1283 |
goto fail; |
1318 |
goto fail; |
|
Lines 1293-1298
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|
| 1293 |
printf("xl%d: failed to read station address\n", sc->xl_unit); |
1328 |
printf("xl%d: failed to read station address\n", sc->xl_unit); |
| 1294 |
bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); |
1329 |
bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); |
| 1295 |
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); |
1330 |
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); |
|
|
1331 |
bus_release_resource(dev, SYS_RES_MEMORY, XL_PCI_FUNCMEM, sc->xl_fres); |
| 1296 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
1332 |
bus_release_resource(dev, XL_RES, XL_RID, sc->xl_res); |
| 1297 |
error = ENXIO; |
1333 |
error = ENXIO; |
| 1298 |
goto fail; |
1334 |
goto fail; |
|
Lines 2543-2548
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|
| 2543 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); |
2579 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); |
| 2544 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); |
2580 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); |
| 2545 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); |
2581 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); |
|
|
2582 |
if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); |
| 2546 |
|
2583 |
|
| 2547 |
/* Set the RX early threshold */ |
2584 |
/* Set the RX early threshold */ |
| 2548 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); |
2585 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); |
|
Lines 2812-2817
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|
| 2812 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); |
2849 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); |
| 2813 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); |
2850 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); |
| 2814 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); |
2851 |
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); |
|
|
2852 |
if (sc->xl_flags & XL_FLAG_FUNCREG) bus_space_write_4 (sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); |
| 2815 |
|
2853 |
|
| 2816 |
/* Stop the stats updater. */ |
2854 |
/* Stop the stats updater. */ |
| 2817 |
untimeout(xl_stats_update, sc, sc->xl_stat_ch); |
2855 |
untimeout(xl_stats_update, sc, sc->xl_stat_ch); |