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Lines 918-926
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| 918 |
printf(", %d bytes/line", regs[3] & 0xff); |
918 |
printf(", %d bytes/line", regs[3] & 0xff); |
| 919 |
printf(", %d lines/tag", (regs[3] >> 8) & 0xff); |
919 |
printf(", %d lines/tag", (regs[3] >> 8) & 0xff); |
| 920 |
print_AMD_assoc((regs[3] >> 16) & 0xff); |
920 |
print_AMD_assoc((regs[3] >> 16) & 0xff); |
| 921 |
if (amd_maxregs >= 0x80000006) { /* K6-III only */ |
921 |
if (amd_maxregs >= 0x80000006) { /* K6-III, K7 or later */ |
| 922 |
do_cpuid(0x80000006, regs); |
922 |
do_cpuid(0x80000006, regs); |
| 923 |
printf("L2 internal cache: %d kbytes", regs[2] >> 16); |
923 |
/* |
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924 |
* Duron Rev. A0 incorrectly reports L2 cache size as 1K when it's 64K. |
| 925 |
*/ |
| 926 |
if ((cpu_id & 0xFF0) == 0x630) { |
| 927 |
printf("L2 internal cache: 64 kbytes"); |
| 928 |
} else { |
| 929 |
printf("L2 internal cache: %d kbytes", regs[2] >> 16); |
| 930 |
} |
| 924 |
printf(", %d bytes/line", regs[2] & 0xff); |
931 |
printf(", %d bytes/line", regs[2] & 0xff); |
| 925 |
printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); |
932 |
printf(", %d lines/tag", (regs[2] >> 8) & 0x0f); |
| 926 |
print_AMD_assoc((regs[2] >> 12) & 0x0f); |
933 |
print_AMD_assoc((regs[2] >> 12) & 0x0f); |