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(-)src/sys/arm/conf/OPENRD (+90 lines)
Line 0 Link Here
1
#
2
# Custom kernel for Marvell OpenRD devices.
3
#
4
# 
5
#
6
7
ident		OPENRD
8
include		"../mv/kirkwood/std.db88f6xxx"
9
10
options 	SOC_MV_KIRKWOOD
11
makeoptions	MODULES_OVERRIDE=""
12
13
#makeoptions	DEBUG=-g		#Build kernel with gdb(1) debug symbols
14
makeoptions	WERROR="-Werror"
15
16
options 	SCHED_4BSD		#4BSD scheduler
17
options 	INET			#InterNETworking
18
options 	INET6			#IPv6 communications protocols
19
options 	FFS			#Berkeley Fast Filesystem
20
options 	NFSCLIENT		#Network Filesystem Client
21
options 	NFSLOCKD		#Network Lock Manager
22
options 	NFS_ROOT		#NFS usable as /, requires NFSCLIENT
23
options 	BOOTP
24
options 	BOOTP_NFSROOT
25
options 	BOOTP_NFSV3
26
options 	BOOTP_WIRED_TO=mge0
27
28
#options 	ROOTDEVNAME=\"ufs:/dev/da0a\"
29
30
options 	SYSVSHM			#SYSV-style shared memory
31
options 	SYSVMSG			#SYSV-style message queues
32
options 	SYSVSEM			#SYSV-style semaphores
33
options 	_KPOSIX_PRIORITY_SCHEDULING #Posix P1003_1B real-time extensions
34
options 	MUTEX_NOINLINE
35
options 	RWLOCK_NOINLINE
36
options 	NO_FFS_SNAPSHOT
37
options 	NO_SWAPPING
38
39
# Debugging
40
options 	ALT_BREAK_TO_DEBUGGER
41
options 	DDB
42
#options	DEADLKRES               #Enable the deadlock resolver
43
options 	DIAGNOSTIC
44
#options	INVARIANTS              #Enable calls of extra sanity checking
45
#options	INVARIANT_SUPPORT       #Extra sanity checks of internal structures, required by INVARIANTS
46
options 	KDB
47
options 	WITNESS                 #Enable checks to detect deadlocks and cycles
48
options 	WITNESS_SKIPSPIN        #Don't run witness on spinlocks for speed
49
#options	WITNESS_KDB
50
51
device		pci
52
53
# Pseudo devices
54
device		loop
55
device		md
56
device		pty
57
device		random
58
59
# Serial ports
60
device		uart
61
62
# Networking
63
device		ether
64
device		mge			# Marvell Gigabit Ethernet controller
65
device		mii
66
device		e1000phy
67
device		bpf
68
69
# USB
70
options 	USB_DEBUG	# enable debug msgs
71
device		usb
72
device		ehci
73
device		umass
74
device		scbus
75
device		pass
76
device		da
77
78
# I2C (TWSI)
79
device		iic
80
device		iicbus
81
82
# SATA
83
device		mvs
84
device		ata
85
device		atadisk
86
87
# Flattened Device Tree
88
options 	FDT
89
options 	FDT_DTB_STATIC
90
makeoptions	FDT_DTS_FILE=openrd.dts
(-)src/sys/boot/fdt/dts/openrd.dts (+354 lines)
Line 0 Link Here
1
/*
2
 * Copyright (c) 2009-2010 The FreeBSD Foundation
3
 * All rights reserved.
4
 *
5
 * This software was developed by Semihalf under sponsorship from
6
 * the FreeBSD Foundation.
7
 *
8
 * Redistribution and use in source and binary forms, with or without
9
 * modification, are permitted provided that the following conditions
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 * are met:
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 * 1. Redistributions of source code must retain the above copyright
12
 *    notice, this list of conditions and the following disclaimer.
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 * 2. Redistributions in binary form must reproduce the above copyright
14
 *    notice, this list of conditions and the following disclaimer in the
15
 *    documentation and/or other materials provided with the distribution.
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20
 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27
 * SUCH DAMAGE.
28
 *
29
 * OpenRD-Client/Ultimate Device Tree Source.
30
 *
31
 * $FreeBSD$
32
 */
33
34
/dts-v1/;
35
36
/ {
37
	model = "mrvl,OpenRD-CL";
38
	compatible = "OpenRD-CL";
39
	#address-cells = <1>;
40
	#size-cells = <1>;
41
42
	aliases {
43
		ethernet0 = &enet0;
44
		ethernet1 = &enet1;
45
		mpp = &MPP;
46
		pci0 = &pci0;
47
		serial0 = &serial0;
48
		serial1 = &serial1;
49
		soc = &SOC;
50
		sram = &SRAM;
51
	};
52
53
	cpus {
54
		#address-cells = <1>;
55
		#size-cells = <0>;
56
57
		cpu@0 {
58
			device_type = "cpu";
59
			compatible = "ARM,88FR131";
60
			reg = <0x0>;
61
			d-cache-line-size = <32>;	// 32 bytes
62
			i-cache-line-size = <32>;	// 32 bytes
63
			d-cache-size = <0x4000>;	// L1, 16K
64
			i-cache-size = <0x4000>;	// L1, 16K
65
			timebase-frequency = <0>;
66
			bus-frequency = <0>;
67
			clock-frequency = <0>;
68
		};
69
	};
70
71
	memory {
72
		device_type = "memory";
73
		reg = <0x0 0x20000000>;		// 512M@0x0
74
	};
75
76
	localbus@f1000000 {
77
		#address-cells = <2>;
78
		#size-cells = <1>;
79
		compatible = "mrvl,lbc";
80
81
		/* This reflects CPU decode windows setup. */
82
		ranges = <0x0 0x0f 0xf9300000 0x00100000
83
			  0x1 0x1e 0xfa000000 0x00100000
84
			  0x2 0x1d 0xfa100000 0x02000000
85
			  0x3 0x1b 0xfc100000 0x00000400>;
86
87
		nor@0,0 {
88
			#address-cells = <1>;
89
			#size-cells = <1>;
90
			compatible = "cfi-flash";
91
			reg = <0x0 0x0 0x00100000>;
92
			bank-width = <2>;
93
			device-width = <1>;
94
		};
95
96
		led@1,0 {
97
			#address-cells = <1>;
98
			#size-cells = <1>;
99
			compatible = "led";
100
			reg = <0x1 0x0 0x00100000>;
101
		};
102
103
		nor@2,0 {
104
			#address-cells = <1>;
105
			#size-cells = <1>;
106
			compatible = "cfi-flash";
107
			reg = <0x2 0x0 0x02000000>;
108
			bank-width = <2>;
109
			device-width = <1>;
110
		};
111
112
		nand@3,0 {
113
			#address-cells = <1>;
114
			#size-cells = <1>;
115
			reg = <0x3 0x0 0x00100000>;
116
			bank-width = <2>;
117
			device-width = <1>;
118
		};
119
	};
120
121
	SOC: soc88f6281@f1000000 {
122
		#address-cells = <1>;
123
		#size-cells = <1>;
124
		compatible = "simple-bus";
125
		ranges = <0x0 0xf1000000 0x00100000>;
126
		bus-frequency = <0>;
127
128
		PIC: pic@20200 {
129
			interrupt-controller;
130
			#address-cells = <0>;
131
			#interrupt-cells = <1>;
132
			reg = <0x20200 0x3c>;
133
			compatible = "mrvl,pic";
134
		};
135
136
		timer@20300 {
137
			compatible = "mrvl,timer";
138
			reg = <0x20300 0x30>;
139
			interrupts = <1>;
140
			interrupt-parent = <&PIC>;
141
			mrvl,has-wdt;
142
		};
143
144
		MPP: mpp@10000 {
145
			#pin-cells = <2>;
146
			compatible = "mrvl,mpp";
147
			reg = <0x10000 0x34>;
148
			pin-count = <50>;
149
			pin-map = <
150
				0  1		/* MPP[0]:  NF_IO[2] */
151
				1  1		/* MPP[1]:  NF_IO[3] */
152
				2  1		/* MPP[2]:  NF_IO[4] */
153
				3  1		/* MPP[3]:  NF_IO[5] */
154
				4  1		/* MPP[4]:  NF_IO[6] */
155
				5  1		/* MPP[5]:  NF_IO[7] */
156
				6  1		/* MPP[6]:  SYSRST_OUTn */
157
				7  0		/* MPP[7]:  GPO[7] */
158
				8  1		/* MPP[8]:  TW_SDA */
159
				9  1		/* MPP[9]:  TW_SCK */
160
				10 3		/* MPP[10]: UA0_TXD */
161
				11 3		/* MPP[11]: UA0_RXD */
162
				12 1		/* MPP[12]: SD_CLK */
163
				13 1		/* MPP[13]: SD_CMD */
164
				14 1		/* MPP[14]: SD_D[0] */
165
				15 1		/* MPP[15]: SD_D[1] */
166
				16 1		/* MPP[16]: SD_D[2] */
167
				17 1		/* MPP[17]: SD_D[3] */
168
				18 1		/* MPP[18]: NF_IO[0] */
169
				19 1		/* MPP[19]: NF_IO[1] */
170
				20 3		/* MPP[20]: GE1[0] */
171
				21 3		/* MPP[21]: GE1[1] */
172
				22 3		/* MPP[22]: GE1[2] */
173
				23 3		/* MPP[23]: GE1[3] */
174
				24 3		/* MPP[24]: GE1[4] */
175
				25 3		/* MPP[25]: GE1[5] */
176
				26 3		/* MPP[26]: GE1[6] */
177
				27 3		/* MPP[27]: GE1[7] */
178
				28 0		/* MPP[28]: GPIO[28] */
179
				29 1		/* MPP[29]: TSMP[9] */
180
				30 3		/* MPP[30]: GE1[10] */
181
				31 3		/* MPP[31]: GE1[11] */
182
				32 3		/* MPP[32]: GE1[12] */
183
				33 3		/* MPP[33]: GE1[13] */
184
				34 0		/* MPP[34]: GPIO[34] */
185
				35 2		/* MPP[35]: TDM_CH0_TX_QL */
186
				36 2		/* MPP[36]: TDM_SPI_CS1 */
187
				37 2		/* MPP[37]: TDM_CH2_TX_QL */
188
				38 2		/* MPP[38]: TDM_CH2_RX_QL */
189
				39 4		/* MPP[39]: AU_I2SBCLK */
190
				40 4		/* MPP[40]: AU_I2SDO */
191
				41 4		/* MPP[41]: AU_I2SLRCLK */
192
				42 4		/* MPP[42]: AU_I2SMCLK */
193
				43 4		/* MPP[43]: AU_I2SDI */
194
				44 4		/* MPP[44]: AU_EXTCLK */
195
				45 2		/* MPP[45]: TDM_PCLK */
196
				46 2		/* MPP[46]: TDM_FS */
197
				47 2		/* MPP[47]: TDM_DRX */
198
				48 2		/* MPP[48]: TDM_DTX */
199
				49 2>;		/* MPP[49]: TDM_CH0_TX_QL */
200
		};
201
202
		GPIO: gpio@10100 {
203
			#gpio-cells = <3>;
204
			compatible = "mrvl,gpio";
205
			reg = <0x10100 0x20>;
206
			gpio-controller;
207
			interrupts = <35 36 37 38 39 40 41>;
208
			interrupt-parent = <&PIC>;
209
		};
210
211
		rtc@10300 {
212
			compatible = "mrvl,rtc";
213
			reg = <0x10300 0x08>;
214
		};
215
216
		twsi@11000 {
217
			#address-cells = <1>;
218
			#size-cells = <0>;
219
			compatible = "mrvl,twsi";
220
			reg = <0x11000 0x20>;
221
			interrupts = <43>;
222
			interrupt-parent = <&PIC>;
223
		};
224
225
		enet0: ethernet@72000 {
226
			#address-cells = <1>;
227
			#size-cells = <1>;
228
			model = "V2";
229
			compatible = "mrvl,ge";
230
			reg = <0x72000 0x2000>;
231
			ranges = <0x0 0x72000 0x2000>;
232
			local-mac-address = [ 00 00 00 00 00 00 ];
233
			interrupts = <12 13 14 11 46>;
234
			interrupt-parent = <&PIC>;
235
236
			mdio@0 {
237
				#address-cells = <1>;
238
				#size-cells = <0>;
239
				compatible = "mrvl,mdio";
240
			};
241
		};
242
243
		enet1: ethernet@76000 {
244
			#address-cells = <1>;
245
			#size-cells = <1>;
246
			model = "V2";
247
			compatible = "mrvl,ge";
248
			reg = <0x76000 0x2000>;
249
			ranges = <0x0 0x76000 0x2000>;
250
			local-mac-address = [ 00 00 00 00 00 00 ];
251
			interrupts = <16 17 18 15 47>;
252
			interrupt-parent = <&PIC>;
253
254
			mdio@1 {
255
				#address-cells = <1>;
256
				#size-cells = <0>;
257
				compatible = "mrvl,mdio";
258
			};
259
		};
260
261
		serial0: serial@12000 {
262
			compatible = "ns16550";
263
			reg = <0x12000 0x20>;
264
			reg-shift = <2>;
265
			clock-frequency = <0>;
266
			interrupts = <33>;
267
			interrupt-parent = <&PIC>;
268
		};
269
270
		serial1: serial@12100 {
271
			compatible = "ns16550";
272
			reg = <0x12100 0x20>;
273
			reg-shift = <2>;
274
			clock-frequency = <0>;
275
			interrupts = <34>;
276
			interrupt-parent = <&PIC>;
277
		};
278
279
		crypto@30000 {
280
			compatible = "mrvl,cesa";
281
			reg = <0x30000 0x10000>;
282
			interrupts = <22>;
283
			interrupt-parent = <&PIC>;
284
		};
285
286
		usb@50000 {
287
			compatible = "mrvl,usb-ehci", "usb-ehci";
288
			reg = <0x50000 0x1000>;
289
			interrupts = <48 19>;
290
			interrupt-parent = <&PIC>;
291
		};
292
293
		xor@60000 {
294
			compatible = "mrvl,xor";
295
			reg = <0x60000 0x1000>;
296
			interrupts = <5 6 7 8>;
297
			interrupt-parent = <&PIC>;
298
		};
299
300
		sata@80000 {
301
			compatible = "mrvl,sata";
302
			reg = <0x80000 0x6000>;
303
			interrupts = <21>;
304
			interrupt-parent = <&PIC>;
305
		};
306
	};
307
308
	SRAM: sram@fd000000 {
309
		compatible = "mrvl,cesa-sram";
310
		reg = <0xfd000000 0x00100000>;
311
	};
312
313
	chosen {
314
		stdin  = "serial0";
315
		stdout = "serial0";
316
	};
317
318
	pci0: pcie@f1040000 {
319
		compatible = "mrvl,pcie";
320
		device_type = "pci";
321
		#interrupt-cells = <1>;
322
		#size-cells = <2>;
323
		#address-cells = <3>;
324
		reg = <0xf1040000 0x2000>;
325
		bus-range = <0 255>;
326
		ranges = <0x02000000 0x0 0xf4000000 0xf4000000 0x0 0x04000000
327
			  0x01000000 0x0 0x00000000 0xf1100000 0x0 0x00100000>;
328
		clock-frequency = <33333333>;
329
		interrupt-parent = <&PIC>;
330
		interrupts = <44>;
331
		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
332
		interrupt-map = <
333
			/* IDSEL 0x1 */
334
			0x0800 0x0 0x0 0x1 &PIC 0x9
335
			0x0800 0x0 0x0 0x2 &PIC 0x9
336
			0x0800 0x0 0x0 0x3 &PIC 0x9
337
			0x0800 0x0 0x0 0x4 &PIC 0x9
338
			>;
339
		pcie@0 {
340
			reg = <0x0 0x0 0x0 0x0 0x0>;
341
			#size-cells = <2>;
342
			#address-cells = <3>;
343
			device_type = "pci";
344
			ranges = <0x02000000 0x0 0xf4000000
345
				  0x02000000 0x0 0xf4000000
346
				  0x0 0x04040000
347
348
				  0x01000000 0x0 0x0
349
				  0x01000000 0x0 0x0
350
				  0x0 0x00100000>;
351
		};
352
	};
353
};
354
(-)src/sys/dev/mge/if_mge.c (-22 / +11 lines)
Lines 626-635 Link Here
626
mge_attach(device_t dev)
626
mge_attach(device_t dev)
627
{
627
{
628
	struct mge_softc *sc;
628
	struct mge_softc *sc;
629
	struct mii_softc *miisc;
630
	struct ifnet *ifp;
629
	struct ifnet *ifp;
631
	uint8_t hwaddr[ETHER_ADDR_LEN];
630
	uint8_t hwaddr[ETHER_ADDR_LEN];
632
	int i, error, phy;
631
	int i, error;
633
632
634
	sc = device_get_softc(dev);
633
	sc = device_get_softc(dev);
635
	sc->dev = dev;
634
	sc->dev = dev;
Lines 642-649 Link Here
642
	mge_ver_params(sc);
641
	mge_ver_params(sc);
643
642
644
	/* Get phy address from fdt */
643
	/* Get phy address from fdt */
645
	if (fdt_get_phyaddr(sc->node, &phy) != 0)
644
	if (fdt_get_phyaddr(sc->node, &sc->phyaddr) != 0)
646
		return (ENXIO);
645
		sc->phyaddr = -1;
647
646
648
	/* Initialize mutexes */
647
	/* Initialize mutexes */
649
	mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
648
	mtx_init(&sc->transmit_lock, device_get_nameunit(dev), "mge TX lock", MTX_DEF);
Lines 674-679 Link Here
674
	sc->tx_ic_time = 768;
673
	sc->tx_ic_time = 768;
675
	mge_add_sysctls(sc);
674
	mge_add_sysctls(sc);
676
675
676
	if (sc->phyaddr == -1)
677
		sc->phyaddr = MGE_READ(sc, MGE_REG_PHYDEV);
678
677
	/* Allocate network interface */
679
	/* Allocate network interface */
678
	ifp = sc->ifp = if_alloc(IFT_ETHER);
680
	ifp = sc->ifp = if_alloc(IFT_ETHER);
679
	if (ifp == NULL) {
681
	if (ifp == NULL) {
Lines 708-714 Link Here
708
710
709
	/* Attach PHY(s) */
711
	/* Attach PHY(s) */
710
	error = mii_attach(dev, &sc->miibus, ifp, mge_ifmedia_upd,
712
	error = mii_attach(dev, &sc->miibus, ifp, mge_ifmedia_upd,
711
	    mge_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
713
	    mge_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 0);
712
	if (error) {
714
	if (error) {
713
		device_printf(dev, "attaching PHYs failed\n");
715
		device_printf(dev, "attaching PHYs failed\n");
714
		mge_detach(dev);
716
		mge_detach(dev);
Lines 717-724 Link Here
717
	sc->mii = device_get_softc(sc->miibus);
719
	sc->mii = device_get_softc(sc->miibus);
718
720
719
	/* Tell the MAC where to find the PHY so autoneg works */
721
	/* Tell the MAC where to find the PHY so autoneg works */
720
	miisc = LIST_FIRST(&sc->mii->mii_phys);
722
	MGE_WRITE(sc, MGE_REG_PHYDEV, sc->phyaddr); 
721
	MGE_WRITE(sc, MGE_REG_PHYDEV, miisc->mii_phy);
722
723
723
	/* Attach interrupt handlers */
724
	/* Attach interrupt handlers */
724
	for (i = 0; i < 2; ++i) {
725
	for (i = 0; i < 2; ++i) {
Lines 868-875 Link Here
868
	struct mge_softc *sc = arg;
869
	struct mge_softc *sc = arg;
869
	struct mge_desc_wrapper *dw;
870
	struct mge_desc_wrapper *dw;
870
	volatile uint32_t reg_val;
871
	volatile uint32_t reg_val;
871
	int i, count;
872
	int i;
872
873
873
874
	MGE_GLOBAL_LOCK_ASSERT(sc);
874
	MGE_GLOBAL_LOCK_ASSERT(sc);
875
875
Lines 949-965 Link Here
949
	reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
949
	reg_val = MGE_READ(sc, MGE_PORT_SERIAL_CTRL);
950
	reg_val |= PORT_SERIAL_ENABLE;
950
	reg_val |= PORT_SERIAL_ENABLE;
951
	MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
951
	MGE_WRITE(sc, MGE_PORT_SERIAL_CTRL, reg_val);
952
	count = 0x100000;
953
	for (;;) {
954
		reg_val = MGE_READ(sc, MGE_PORT_STATUS);
955
		if (reg_val & MGE_STATUS_LINKUP)
956
			break;
957
		DELAY(100);
958
		if (--count == 0) {
959
			if_printf(sc->ifp, "Timeout on link-up\n");
960
			break;
961
		}
962
	}
963
952
964
	/* Setup interrupts coalescing */
953
	/* Setup interrupts coalescing */
965
	mge_set_rxic(sc);
954
	mge_set_rxic(sc);
Lines 1484-1491 Link Here
1484
1473
1485
	MGE_TRANSMIT_LOCK_ASSERT(sc);
1474
	MGE_TRANSMIT_LOCK_ASSERT(sc);
1486
1475
1487
	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1476
	if (IFM_SUBTYPE(sc->mii->mii_media_active) == IFM_NONE ||
1488
	    IFF_DRV_RUNNING)
1477
	    (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != IFF_DRV_RUNNING)
1489
		return;
1478
		return;
1490
1479
1491
	for (;;) {
1480
	for (;;) {
(-)src/sys/dev/mge/if_mgevar.h (+1 lines)
Lines 103-108 Link Here
103
	uint32_t	mge_tx_tok_cnt;
103
	uint32_t	mge_tx_tok_cnt;
104
	uint16_t	mge_mtu;
104
	uint16_t	mge_mtu;
105
	int		mge_ver;
105
	int		mge_ver;
106
	int		phyaddr;
106
};
107
};

Return to bug 156814