Attachment #119663 for bug #162280

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Lines 7-13 Link Here

(-)cad/iverilog/Makefile (-1 / +3 lines)
7	#	7	#
8		8
9	PORTNAME= iverilog	9	PORTNAME= iverilog
10	PORTVERSION= 0.9.4	10	PORTVERSION= 0.9.5
11	CATEGORIES= cad	11	CATEGORIES= cad
12	MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \	12	MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \
13	ftp://ftp.geda.seul.org/pub/geda/dist/	13	ftp://ftp.geda.seul.org/pub/geda/dist/
Lines 16-21 Link Here
16	MAINTAINER= niclas.zeising@gmail.com	16	MAINTAINER= niclas.zeising@gmail.com
17	COMMENT= A Verilog simulation and synthesis tool	17	COMMENT= A Verilog simulation and synthesis tool
18		18
		19	LICENSE= GPLv2
		20
19	GNU_CONFIGURE= yes	21	GNU_CONFIGURE= yes
20	USE_BISON= build	22	USE_BISON= build
21	USE_GMAKE= yes	23	USE_GMAKE= yes

Lines 1-2 Link Here

(-)cad/iverilog/distinfo (-2 / +2 lines)
1	SHA256 (verilog-0.9.4.tar.gz) = b4eac7276975cf2d7c2c94246f733dc187feb4d5944034d053c5094279511eb1	1	SHA256 (verilog-0.9.5.tar.gz) = c522b8b873f0cf77003db15c3df0f4a15b738ce4b060d1ca387c88e1b2be185d
2	SIZE (verilog-0.9.4.tar.gz) = 1200614	2	SIZE (verilog-0.9.5.tar.gz) = 1212112

Lines 12-15 Link Here

(-)cad/iverilog/pkg-descr (-1 / +1 lines)
12	year 2000. This is a fairly large and complex standard, so it will	12	year 2000. This is a fairly large and complex standard, so it will
13	take some time for it to get there, but that's the goal.	13	take some time for it to get there, but that's the goal.
14		14
15	WWW: http://www.icarus.com/eda/verilog/	15	WWW: http://iverilog.icarus.com/

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