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(-)ixgbe_vf.h (+7 lines)
Lines 39-44 Link Here
39
#define IXGBE_VF_MAX_TX_QUEUES	8
39
#define IXGBE_VF_MAX_TX_QUEUES	8
40
#define IXGBE_VF_MAX_RX_QUEUES	8
40
#define IXGBE_VF_MAX_RX_QUEUES	8
41
41
42
/* DCB define */
43
#define IXGBE_VF_MAX_TRAFFIC_CLASS	8
44
42
#define IXGBE_VFCTRL		0x00000
45
#define IXGBE_VFCTRL		0x00000
43
#define IXGBE_VFSTATUS		0x00008
46
#define IXGBE_VFSTATUS		0x00008
44
#define IXGBE_VFLINKS		0x00010
47
#define IXGBE_VFLINKS		0x00010
Lines 127-131 Link Here
127
				 u32 mc_addr_count, ixgbe_mc_addr_itr,
130
				 u32 mc_addr_count, ixgbe_mc_addr_itr,
128
				 bool clear);
131
				 bool clear);
129
s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
132
s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on);
133
void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size);
134
int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api);
135
int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
136
		       unsigned int *default_tc);
130
137
131
#endif /* __IXGBE_VF_H__ */
138
#endif /* __IXGBE_VF_H__ */
(-)ixgbe_common.c (-2 / +256 lines)
Lines 174-179 Link Here
174
	s32 ret_val = IXGBE_SUCCESS;
174
	s32 ret_val = IXGBE_SUCCESS;
175
	u32 reg = 0, reg_bp = 0;
175
	u32 reg = 0, reg_bp = 0;
176
	u16 reg_cu = 0;
176
	u16 reg_cu = 0;
177
	bool got_lock = FALSE;
177
178
178
	DEBUGFUNC("ixgbe_setup_fc");
179
	DEBUGFUNC("ixgbe_setup_fc");
179
180
Lines 297-303 Link Here
297
	 */
298
	 */
298
	if (hw->phy.media_type == ixgbe_media_type_backplane) {
299
	if (hw->phy.media_type == ixgbe_media_type_backplane) {
299
		reg_bp |= IXGBE_AUTOC_AN_RESTART;
300
		reg_bp |= IXGBE_AUTOC_AN_RESTART;
301
		/* Need the SW/FW semaphore around AUTOC writes if 82599 and
302
		 * LESM is on, likewise reset_pipeline requries the lock as
303
		 * it also writes AUTOC.
304
		 */
305
		if ((hw->mac.type == ixgbe_mac_82599EB) &&
306
		    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
307
			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
308
							IXGBE_GSSR_MAC_CSR_SM);
309
			if (ret_val != IXGBE_SUCCESS) {
310
				ret_val = IXGBE_ERR_SWFW_SYNC;
311
				goto out;
312
			}
313
			got_lock = TRUE;
314
		}
315
300
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
316
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
317
		if (hw->mac.type == ixgbe_mac_82599EB)
318
			ixgbe_reset_pipeline_82599(hw);
319
320
		if (got_lock)
321
			hw->mac.ops.release_swfw_sync(hw,
322
						      IXGBE_GSSR_MAC_CSR_SM);
301
	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
323
	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
302
		    (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
324
		    (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
303
		hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
325
		hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
Lines 680-685 Link Here
680
}
702
}
681
703
682
/**
704
/**
705
 *  ixgbe_read_pba_raw
706
 *  @hw: pointer to the HW structure
707
 *  @eeprom_buf: optional pointer to EEPROM image
708
 *  @eeprom_buf_size: size of EEPROM image in words
709
 *  @max_pba_block_size: PBA block size limit
710
 *  @pba: pointer to output PBA structure
711
 *
712
 *  Reads PBA from EEPROM image when eeprom_buf is not NULL.
713
 *  Reads PBA from physical EEPROM device when eeprom_buf is NULL.
714
 *
715
 **/
716
s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
717
		       u32 eeprom_buf_size, u16 max_pba_block_size,
718
		       struct ixgbe_pba *pba)
719
{
720
	s32 ret_val;
721
	u16 pba_block_size;
722
723
	if (pba == NULL)
724
		return IXGBE_ERR_PARAM;
725
726
	if (eeprom_buf == NULL) {
727
		ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
728
						     &pba->word[0]);
729
		if (ret_val)
730
			return ret_val;
731
	} else {
732
		if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
733
			pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
734
			pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
735
		} else {
736
			return IXGBE_ERR_PARAM;
737
		}
738
	}
739
740
	if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
741
		if (pba->pba_block == NULL)
742
			return IXGBE_ERR_PARAM;
743
744
		ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
745
						   eeprom_buf_size,
746
						   &pba_block_size);
747
		if (ret_val)
748
			return ret_val;
749
750
		if (pba_block_size > max_pba_block_size)
751
			return IXGBE_ERR_PARAM;
752
753
		if (eeprom_buf == NULL) {
754
			ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
755
							     pba_block_size,
756
							     pba->pba_block);
757
			if (ret_val)
758
				return ret_val;
759
		} else {
760
			if (eeprom_buf_size > (u32)(pba->word[1] +
761
					      pba->pba_block[0])) {
762
				memcpy(pba->pba_block,
763
				       &eeprom_buf[pba->word[1]],
764
				       pba_block_size * sizeof(u16));
765
			} else {
766
				return IXGBE_ERR_PARAM;
767
			}
768
		}
769
	}
770
771
	return IXGBE_SUCCESS;
772
}
773
774
/**
775
 *  ixgbe_write_pba_raw
776
 *  @hw: pointer to the HW structure
777
 *  @eeprom_buf: optional pointer to EEPROM image
778
 *  @eeprom_buf_size: size of EEPROM image in words
779
 *  @pba: pointer to PBA structure
780
 *
781
 *  Writes PBA to EEPROM image when eeprom_buf is not NULL.
782
 *  Writes PBA to physical EEPROM device when eeprom_buf is NULL.
783
 *
784
 **/
785
s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
786
			u32 eeprom_buf_size, struct ixgbe_pba *pba)
787
{
788
	s32 ret_val;
789
790
	if (pba == NULL)
791
		return IXGBE_ERR_PARAM;
792
793
	if (eeprom_buf == NULL) {
794
		ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
795
						      &pba->word[0]);
796
		if (ret_val)
797
			return ret_val;
798
	} else {
799
		if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
800
			eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
801
			eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
802
		} else {
803
			return IXGBE_ERR_PARAM;
804
		}
805
	}
806
807
	if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
808
		if (pba->pba_block == NULL)
809
			return IXGBE_ERR_PARAM;
810
811
		if (eeprom_buf == NULL) {
812
			ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
813
							      pba->pba_block[0],
814
							      pba->pba_block);
815
			if (ret_val)
816
				return ret_val;
817
		} else {
818
			if (eeprom_buf_size > (u32)(pba->word[1] +
819
					      pba->pba_block[0])) {
820
				memcpy(&eeprom_buf[pba->word[1]],
821
				       pba->pba_block,
822
				       pba->pba_block[0] * sizeof(u16));
823
			} else {
824
				return IXGBE_ERR_PARAM;
825
			}
826
		}
827
	}
828
829
	return IXGBE_SUCCESS;
830
}
831
832
/**
833
 *  ixgbe_get_pba_block_size
834
 *  @hw: pointer to the HW structure
835
 *  @eeprom_buf: optional pointer to EEPROM image
836
 *  @eeprom_buf_size: size of EEPROM image in words
837
 *  @pba_data_size: pointer to output variable
838
 *
839
 *  Returns the size of the PBA block in words. Function operates on EEPROM
840
 *  image if the eeprom_buf pointer is not NULL otherwise it accesses physical
841
 *  EEPROM device.
842
 *
843
 **/
844
s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
845
			     u32 eeprom_buf_size, u16 *pba_block_size)
846
{
847
	s32 ret_val;
848
	u16 pba_word[2];
849
	u16 length;
850
851
	DEBUGFUNC("ixgbe_get_pba_block_size");
852
853
	if (eeprom_buf == NULL) {
854
		ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
855
						     &pba_word[0]);
856
		if (ret_val)
857
			return ret_val;
858
	} else {
859
		if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
860
			pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
861
			pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
862
		} else {
863
			return IXGBE_ERR_PARAM;
864
		}
865
	}
866
867
	if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
868
		if (eeprom_buf == NULL) {
869
			ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
870
						      &length);
871
			if (ret_val)
872
				return ret_val;
873
		} else {
874
			if (eeprom_buf_size > pba_word[1])
875
				length = eeprom_buf[pba_word[1] + 0];
876
			else
877
				return IXGBE_ERR_PARAM;
878
		}
879
880
		if (length == 0xFFFF || length == 0)
881
			return IXGBE_ERR_PBA_SECTION;
882
	} else {
883
		/* PBA number in legacy format, there is no PBA Block. */
884
		length = 0;
885
	}
886
887
	if (pba_block_size != NULL)
888
		*pba_block_size = length;
889
890
	return IXGBE_SUCCESS;
891
}
892
893
/**
683
 *  ixgbe_get_mac_addr_generic - Generic get MAC address
894
 *  ixgbe_get_mac_addr_generic - Generic get MAC address
684
 *  @hw: pointer to hardware structure
895
 *  @hw: pointer to hardware structure
685
 *  @mac_addr: Adapter MAC address
896
 *  @mac_addr: Adapter MAC address
Lines 2965-2970 Link Here
2965
	bool link_up = 0;
3176
	bool link_up = 0;
2966
	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3177
	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2967
	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3178
	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3179
	s32 ret_val = IXGBE_SUCCESS;
2968
3180
2969
	DEBUGFUNC("ixgbe_blink_led_start_generic");
3181
	DEBUGFUNC("ixgbe_blink_led_start_generic");
2970
3182
Lines 2975-2984 Link Here
2975
	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
3187
	hw->mac.ops.check_link(hw, &speed, &link_up, FALSE);
2976
3188
2977
	if (!link_up) {
3189
	if (!link_up) {
3190
		/* Need the SW/FW semaphore around AUTOC writes if 82599 and
3191
		 * LESM is on.
3192
		 */
3193
		bool got_lock = FALSE;
3194
		if ((hw->mac.type == ixgbe_mac_82599EB) &&
3195
		    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3196
			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3197
							IXGBE_GSSR_MAC_CSR_SM);
3198
			if (ret_val != IXGBE_SUCCESS) {
3199
				ret_val = IXGBE_ERR_SWFW_SYNC;
3200
				goto out;
3201
			}
3202
			got_lock = TRUE;
3203
		}
3204
2978
		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3205
		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2979
		autoc_reg |= IXGBE_AUTOC_FLU;
3206
		autoc_reg |= IXGBE_AUTOC_FLU;
2980
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3207
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2981
		IXGBE_WRITE_FLUSH(hw);
3208
		IXGBE_WRITE_FLUSH(hw);
3209
3210
		if (got_lock)
3211
			hw->mac.ops.release_swfw_sync(hw,
3212
						      IXGBE_GSSR_MAC_CSR_SM);
2982
		msec_delay(10);
3213
		msec_delay(10);
2983
	}
3214
	}
2984
3215
Lines 2987-2993 Link Here
2987
	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3218
	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2988
	IXGBE_WRITE_FLUSH(hw);
3219
	IXGBE_WRITE_FLUSH(hw);
2989
3220
2990
	return IXGBE_SUCCESS;
3221
out:
3222
	return ret_val;
2991
}
3223
}
2992
3224
2993
/**
3225
/**
Lines 2999-3019 Link Here
2999
{
3231
{
3000
	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3232
	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3001
	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3233
	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3234
	s32 ret_val = IXGBE_SUCCESS;
3235
	bool got_lock = FALSE;
3002
3236
3003
	DEBUGFUNC("ixgbe_blink_led_stop_generic");
3237
	DEBUGFUNC("ixgbe_blink_led_stop_generic");
3238
	/* Need the SW/FW semaphore around AUTOC writes if 82599 and
3239
	 * LESM is on.
3240
	 */
3241
	if ((hw->mac.type == ixgbe_mac_82599EB) &&
3242
	    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3243
		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3244
						IXGBE_GSSR_MAC_CSR_SM);
3245
		if (ret_val != IXGBE_SUCCESS) {
3246
			ret_val = IXGBE_ERR_SWFW_SYNC;
3247
			goto out;
3248
		}
3249
		got_lock = TRUE;
3250
	}
3004
3251
3005
3252
3006
	autoc_reg &= ~IXGBE_AUTOC_FLU;
3253
	autoc_reg &= ~IXGBE_AUTOC_FLU;
3007
	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3254
	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3008
	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3255
	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3009
3256
3257
	if (hw->mac.type == ixgbe_mac_82599EB)
3258
		ixgbe_reset_pipeline_82599(hw);
3259
3260
	if (got_lock)
3261
		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3262
3010
	led_reg &= ~IXGBE_LED_MODE_MASK(index);
3263
	led_reg &= ~IXGBE_LED_MODE_MASK(index);
3011
	led_reg &= ~IXGBE_LED_BLINK(index);
3264
	led_reg &= ~IXGBE_LED_BLINK(index);
3012
	led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3265
	led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3013
	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3266
	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3014
	IXGBE_WRITE_FLUSH(hw);
3267
	IXGBE_WRITE_FLUSH(hw);
3015
3268
3016
	return IXGBE_SUCCESS;
3269
out:
3270
	return ret_val;
3017
}
3271
}
3018
3272
3019
/**
3273
/**
(-)ixgbe_common.h (+16 lines)
Lines 41-46 Link Here
41
		IXGBE_WRITE_REG(hw, reg, (u32) value); \
41
		IXGBE_WRITE_REG(hw, reg, (u32) value); \
42
		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
42
		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32)); \
43
	} while (0)
43
	} while (0)
44
#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW)
45
struct ixgbe_pba {
46
	u16 word[2];
47
	u16 *pba_block;
48
};
49
#endif
44
50
45
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
51
u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw);
46
52
Lines 52-57 Link Here
52
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
58
s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num);
53
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
59
s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
54
				  u32 pba_num_size);
60
				  u32 pba_num_size);
61
s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
62
		       u32 eeprom_buf_size, u16 max_pba_block_size,
63
		       struct ixgbe_pba *pba);
64
s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
65
			u32 eeprom_buf_size, struct ixgbe_pba *pba);
66
s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
67
			     u32 eeprom_buf_size, u16 *pba_block_size);
55
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
68
s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr);
56
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
69
s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw);
57
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
70
void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw);
Lines 138-141 Link Here
138
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
151
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
139
				 u8 build, u8 ver);
152
				 u8 build, u8 ver);
140
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
153
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
154
155
extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);
156
141
#endif /* IXGBE_COMMON */
157
#endif /* IXGBE_COMMON */
(-)ixgbe_82599.c (-28 / +141 lines)
Lines 135-143 Link Here
135
s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
135
s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
136
{
136
{
137
	s32 ret_val = IXGBE_SUCCESS;
137
	s32 ret_val = IXGBE_SUCCESS;
138
	u32 reg_anlp1 = 0;
139
	u32 i = 0;
140
	u16 list_offset, data_offset, data_value;
138
	u16 list_offset, data_offset, data_value;
139
	bool got_lock = FALSE;
141
140
142
	DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
141
	DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143
142
Lines 171-198 Link Here
171
		/* Delay obtaining semaphore again to allow FW access */
170
		/* Delay obtaining semaphore again to allow FW access */
172
		msec_delay(hw->eeprom.semaphore_delay);
171
		msec_delay(hw->eeprom.semaphore_delay);
173
172
174
		/* Now restart DSP by setting Restart_AN and clearing LMS */
173
		/* Need SW/FW semaphore around AUTOC writes if LESM on,
175
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
174
		 * likewise reset_pipeline requires lock as it also writes
176
				IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
175
		 * AUTOC.
177
				IXGBE_AUTOC_AN_RESTART));
176
		 */
177
		if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
178
			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
179
							IXGBE_GSSR_MAC_CSR_SM);
180
			if (ret_val != IXGBE_SUCCESS) {
181
				ret_val = IXGBE_ERR_SWFW_SYNC;
182
				goto setup_sfp_out;
183
			}
178
184
179
		/* Wait for AN to leave state 0 */
185
			got_lock = TRUE;
180
		for (i = 0; i < 10; i++) {
181
			msec_delay(4);
182
			reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
183
			if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
184
				break;
185
		}
186
		}
186
		if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
187
188
		/* Restart DSP and set SFI mode */
189
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
190
				IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
191
192
		ret_val = ixgbe_reset_pipeline_82599(hw);
193
194
		if (got_lock) {
195
			hw->mac.ops.release_swfw_sync(hw,
196
						      IXGBE_GSSR_MAC_CSR_SM);
197
			got_lock = FALSE;
198
		}
199
200
		if (ret_val) {
187
			DEBUGOUT("sfp module setup not complete\n");
201
			DEBUGOUT("sfp module setup not complete\n");
188
			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
202
			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
189
			goto setup_sfp_out;
203
			goto setup_sfp_out;
190
		}
204
		}
191
205
192
		/* Restart DSP by setting Restart_AN and return to SFI mode */
193
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
194
				IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
195
				IXGBE_AUTOC_AN_RESTART));
196
	}
206
	}
197
207
198
setup_sfp_out:
208
setup_sfp_out:
Lines 424-429 Link Here
424
	case IXGBE_DEV_ID_82599_SFP_FCOE:
434
	case IXGBE_DEV_ID_82599_SFP_FCOE:
425
	case IXGBE_DEV_ID_82599_SFP_EM:
435
	case IXGBE_DEV_ID_82599_SFP_EM:
426
	case IXGBE_DEV_ID_82599_SFP_SF2:
436
	case IXGBE_DEV_ID_82599_SFP_SF2:
437
	case IXGBE_DEV_ID_82599_SFP_SF_QP:
427
	case IXGBE_DEV_ID_82599EN_SFP:
438
	case IXGBE_DEV_ID_82599EN_SFP:
428
		media_type = ixgbe_media_type_fiber;
439
		media_type = ixgbe_media_type_fiber;
429
		break;
440
		break;
Lines 456-472 Link Here
456
	u32 links_reg;
467
	u32 links_reg;
457
	u32 i;
468
	u32 i;
458
	s32 status = IXGBE_SUCCESS;
469
	s32 status = IXGBE_SUCCESS;
470
	bool got_lock = FALSE;
459
471
460
	DEBUGFUNC("ixgbe_start_mac_link_82599");
472
	DEBUGFUNC("ixgbe_start_mac_link_82599");
461
473
462
474
475
	/*  reset_pipeline requires us to hold this lock as it writes to
476
	 *  AUTOC.
477
	 */
478
	if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
479
		status = hw->mac.ops.acquire_swfw_sync(hw,
480
						       IXGBE_GSSR_MAC_CSR_SM);
481
		if (status != IXGBE_SUCCESS)
482
			goto out;
483
484
		got_lock = TRUE;
485
	}
486
463
	/* Restart link */
487
	/* Restart link */
464
	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
488
	ixgbe_reset_pipeline_82599(hw);
465
	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
466
	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
467
489
490
	if (got_lock)
491
		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
492
468
	/* Only poll for autoneg to complete if specified to do so */
493
	/* Only poll for autoneg to complete if specified to do so */
469
	if (autoneg_wait_to_complete) {
494
	if (autoneg_wait_to_complete) {
495
		autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
470
		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
496
		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
471
		     IXGBE_AUTOC_LMS_KX4_KX_KR ||
497
		     IXGBE_AUTOC_LMS_KX4_KX_KR ||
472
		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
498
		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
Lines 490-495 Link Here
490
	/* Add delay to filter out noises during initial link setup */
516
	/* Add delay to filter out noises during initial link setup */
491
	msec_delay(50);
517
	msec_delay(50);
492
518
519
out:
493
	return status;
520
	return status;
494
}
521
}
495
522
Lines 842-853 Link Here
842
	u32 links_reg;
869
	u32 links_reg;
843
	u32 i;
870
	u32 i;
844
	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
871
	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
872
	bool got_lock = FALSE;
845
873
846
	DEBUGFUNC("ixgbe_setup_mac_link_82599");
874
	DEBUGFUNC("ixgbe_setup_mac_link_82599");
847
875
848
	/* Check to see if speed passed in is supported. */
876
	/* Check to see if speed passed in is supported. */
849
	status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
877
	status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
850
	if (status != IXGBE_SUCCESS)
878
	if (status)
851
		goto out;
879
		goto out;
852
880
853
	speed &= link_capabilities;
881
	speed &= link_capabilities;
Lines 868-879 Link Here
868
	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
896
	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
869
		/* Set KX4/KX/KR support according to speed requested */
897
		/* Set KX4/KX/KR support according to speed requested */
870
		autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
898
		autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
871
		if (speed & IXGBE_LINK_SPEED_10GB_FULL)
899
		if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
872
			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
900
			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
873
				autoc |= IXGBE_AUTOC_KX4_SUPP;
901
				autoc |= IXGBE_AUTOC_KX4_SUPP;
874
			if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
902
			if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
875
			    (hw->phy.smart_speed_active == FALSE))
903
			    (hw->phy.smart_speed_active == FALSE))
876
				autoc |= IXGBE_AUTOC_KR_SUPP;
904
				autoc |= IXGBE_AUTOC_KR_SUPP;
905
		}
877
		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
906
		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
878
			autoc |= IXGBE_AUTOC_KX_SUPP;
907
			autoc |= IXGBE_AUTOC_KX_SUPP;
879
	} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
908
	} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
Lines 899-908 Link Here
899
	}
928
	}
900
929
901
	if (autoc != start_autoc) {
930
	if (autoc != start_autoc) {
931
		/* Need SW/FW semaphore around AUTOC writes if LESM is on,
932
		 * likewise reset_pipeline requires us to hold this lock as
933
		 * it also writes to AUTOC.
934
		 */
935
		if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
936
			status = hw->mac.ops.acquire_swfw_sync(hw,
937
							IXGBE_GSSR_MAC_CSR_SM);
938
			if (status != IXGBE_SUCCESS) {
939
				status = IXGBE_ERR_SWFW_SYNC;
940
				goto out;
941
			}
942
943
			got_lock = TRUE;
944
		}
945
902
		/* Restart link */
946
		/* Restart link */
903
		autoc |= IXGBE_AUTOC_AN_RESTART;
904
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
947
		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
948
		ixgbe_reset_pipeline_82599(hw);
905
949
950
		if (got_lock) {
951
			hw->mac.ops.release_swfw_sync(hw,
952
						      IXGBE_GSSR_MAC_CSR_SM);
953
			got_lock = FALSE;
954
		}
955
906
		/* Only poll for autoneg to complete if specified to do so */
956
		/* Only poll for autoneg to complete if specified to do so */
907
		if (autoneg_wait_to_complete) {
957
		if (autoneg_wait_to_complete) {
908
			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
958
			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
Lines 1060-1069 Link Here
1060
		hw->mac.orig_autoc2 = autoc2;
1110
		hw->mac.orig_autoc2 = autoc2;
1061
		hw->mac.orig_link_settings_stored = TRUE;
1111
		hw->mac.orig_link_settings_stored = TRUE;
1062
	} else {
1112
	} else {
1063
		if (autoc != hw->mac.orig_autoc)
1113
		if (autoc != hw->mac.orig_autoc) {
1064
			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1114
			/* Need SW/FW semaphore around AUTOC writes if LESM is
1065
					IXGBE_AUTOC_AN_RESTART));
1115
			 * on, likewise reset_pipeline requires us to hold
1116
			 * this lock as it also writes to AUTOC.
1117
			 */
1118
			bool got_lock = FALSE;
1119
			if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1120
				status = hw->mac.ops.acquire_swfw_sync(hw,
1121
							IXGBE_GSSR_MAC_CSR_SM);
1122
				if (status != IXGBE_SUCCESS) {
1123
					status = IXGBE_ERR_SWFW_SYNC;
1124
					goto reset_hw_out;
1125
				}
1066
1126
1127
				got_lock = TRUE;
1128
			}
1129
1130
			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1131
			ixgbe_reset_pipeline_82599(hw);
1132
1133
			if (got_lock)
1134
				hw->mac.ops.release_swfw_sync(hw,
1135
						      IXGBE_GSSR_MAC_CSR_SM);
1136
		}
1137
1067
		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1138
		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1068
		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1139
		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1069
			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1140
			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
Lines 1167-1173 Link Here
1167
		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1238
		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1168
				   IXGBE_FDIRCTRL_INIT_DONE)
1239
				   IXGBE_FDIRCTRL_INIT_DONE)
1169
			break;
1240
			break;
1170
		usec_delay(10);
1241
		msec_delay(1);
1171
	}
1242
	}
1172
	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1243
	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1173
		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1244
		DEBUGOUT("Flow Director Signature poll time exceeded!\n");
Lines 2093-2099 Link Here
2093
 *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2164
 *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2094
 *  if the FW version is not supported.
2165
 *  if the FW version is not supported.
2095
 **/
2166
 **/
2096
static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2167
s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2097
{
2168
{
2098
	s32 status = IXGBE_ERR_EEPROM_VERSION;
2169
	s32 status = IXGBE_ERR_EEPROM_VERSION;
2099
	u16 fw_offset, fw_ptp_cfg_offset;
2170
	u16 fw_offset, fw_ptp_cfg_offset;
Lines 2242-2245 Link Here
2242
	return ret_val;
2313
	return ret_val;
2243
}
2314
}
2244
2315
2316
/**
2317
 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2318
 *
2319
 *  @hw: pointer to hardware structure
2320
 *
2321
 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2322
 * full pipeline reset
2323
 **/
2324
s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2325
{
2326
	s32 i, autoc_reg, ret_val;
2327
	s32 anlp1_reg = 0;
2245
2328
2329
	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2330
	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2331
	/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2332
	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2333
	/* Wait for AN to leave state 0 */
2334
	for (i = 0; i < 10; i++) {
2335
		msec_delay(4);
2336
		anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2337
		if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2338
			break;
2339
	}
2340
2341
	if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2342
		DEBUGOUT("auto negotiation not completed\n");
2343
		ret_val = IXGBE_ERR_RESET_FAILED;
2344
		goto reset_pipeline_out;
2345
	}
2346
2347
	ret_val = IXGBE_SUCCESS;
2348
2349
reset_pipeline_out:
2350
	/* Write AUTOC register with original LMS field and Restart_AN */
2351
	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2352
	IXGBE_WRITE_FLUSH(hw);
2353
2354
	return ret_val;
2355
}
2356
2357
2358
(-)ixgbe_82599.h (-1 lines)
Lines 61-65 Link Here
61
s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
61
s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
62
u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
62
u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
63
s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
63
s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
64
bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
65
#endif /* _IXGBE_82599_H_ */
64
#endif /* _IXGBE_82599_H_ */
(-)ixgbe_api.c (-46 / +43 lines)
Lines 93-145 Link Here
93
93
94
	DEBUGFUNC("ixgbe_set_mac_type\n");
94
	DEBUGFUNC("ixgbe_set_mac_type\n");
95
95
96
	if (hw->vendor_id == IXGBE_INTEL_VENDOR_ID) {
96
	switch (hw->device_id) {
97
		switch (hw->device_id) {
97
	case IXGBE_DEV_ID_82598:
98
		case IXGBE_DEV_ID_82598:
98
	case IXGBE_DEV_ID_82598_BX:
99
		case IXGBE_DEV_ID_82598_BX:
99
	case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
100
		case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
100
	case IXGBE_DEV_ID_82598AF_DUAL_PORT:
101
		case IXGBE_DEV_ID_82598AF_DUAL_PORT:
101
	case IXGBE_DEV_ID_82598AT:
102
		case IXGBE_DEV_ID_82598AT:
102
	case IXGBE_DEV_ID_82598AT2:
103
		case IXGBE_DEV_ID_82598AT2:
103
	case IXGBE_DEV_ID_82598EB_CX4:
104
		case IXGBE_DEV_ID_82598EB_CX4:
104
	case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
105
		case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
105
	case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
106
		case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
106
	case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
107
		case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
107
	case IXGBE_DEV_ID_82598EB_XF_LR:
108
		case IXGBE_DEV_ID_82598EB_XF_LR:
108
	case IXGBE_DEV_ID_82598EB_SFP_LOM:
109
		case IXGBE_DEV_ID_82598EB_SFP_LOM:
109
		hw->mac.type = ixgbe_mac_82598EB;
110
			hw->mac.type = ixgbe_mac_82598EB;
110
		break;
111
			break;
111
	case IXGBE_DEV_ID_82599_KX4:
112
		case IXGBE_DEV_ID_82599_KX4:
112
	case IXGBE_DEV_ID_82599_KX4_MEZZ:
113
		case IXGBE_DEV_ID_82599_KX4_MEZZ:
113
	case IXGBE_DEV_ID_82599_XAUI_LOM:
114
		case IXGBE_DEV_ID_82599_XAUI_LOM:
114
	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
115
		case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
115
	case IXGBE_DEV_ID_82599_KR:
116
		case IXGBE_DEV_ID_82599_KR:
116
	case IXGBE_DEV_ID_82599_SFP:
117
		case IXGBE_DEV_ID_82599_SFP:
117
	case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
118
		case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
118
	case IXGBE_DEV_ID_82599_SFP_FCOE:
119
		case IXGBE_DEV_ID_82599_SFP_FCOE:
119
	case IXGBE_DEV_ID_82599_SFP_EM:
120
		case IXGBE_DEV_ID_82599_SFP_EM:
120
	case IXGBE_DEV_ID_82599_SFP_SF2:
121
		case IXGBE_DEV_ID_82599_SFP_SF2:
121
	case IXGBE_DEV_ID_82599_SFP_SF_QP:
122
		case IXGBE_DEV_ID_82599EN_SFP:
122
	case IXGBE_DEV_ID_82599EN_SFP:
123
		case IXGBE_DEV_ID_82599_CX4:
123
	case IXGBE_DEV_ID_82599_CX4:
124
		case IXGBE_DEV_ID_82599_T3_LOM:
124
	case IXGBE_DEV_ID_82599_T3_LOM:
125
			hw->mac.type = ixgbe_mac_82599EB;
125
		hw->mac.type = ixgbe_mac_82599EB;
126
			break;
126
		break;
127
		case IXGBE_DEV_ID_82599_VF:
127
	case IXGBE_DEV_ID_82599_VF:
128
			hw->mac.type = ixgbe_mac_82599_vf;
128
		hw->mac.type = ixgbe_mac_82599_vf;
129
			break;
129
		break;
130
		case IXGBE_DEV_ID_X540_VF:
130
	case IXGBE_DEV_ID_X540_VF:
131
			hw->mac.type = ixgbe_mac_X540_vf;
131
		hw->mac.type = ixgbe_mac_X540_vf;
132
			break;
132
		break;
133
		case IXGBE_DEV_ID_X540T:
133
	case IXGBE_DEV_ID_X540T:
134
		case IXGBE_DEV_ID_X540T1:
134
	case IXGBE_DEV_ID_X540T1:
135
			hw->mac.type = ixgbe_mac_X540;
135
		hw->mac.type = ixgbe_mac_X540;
136
			break;
136
		break;
137
		default:
137
	default:
138
			ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
139
			break;
140
		}
141
	} else {
142
		ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
138
		ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
139
		break;
143
	}
140
	}
144
141
145
	DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
142
	DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n",
(-)ixgbe_api.h (+1 lines)
Lines 159-164 Link Here
159
					  union ixgbe_atr_input *mask);
159
					  union ixgbe_atr_input *mask);
160
u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
160
u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
161
				     union ixgbe_atr_hash_dword common);
161
				     union ixgbe_atr_hash_dword common);
162
bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
162
s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
163
s32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
163
			u8 *data);
164
			u8 *data);
164
s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
165
s32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr,
(-)ixgbe.c (-102 / +180 lines)
Lines 32-37 Link Here
32
******************************************************************************/
32
******************************************************************************/
33
/*$FreeBSD$*/
33
/*$FreeBSD$*/
34
34
35
35
#ifdef HAVE_KERNEL_OPTION_HEADERS
36
#ifdef HAVE_KERNEL_OPTION_HEADERS
36
#include "opt_inet.h"
37
#include "opt_inet.h"
37
#include "opt_inet6.h"
38
#include "opt_inet6.h"
Lines 47-53 Link Here
47
/*********************************************************************
48
/*********************************************************************
48
 *  Driver version
49
 *  Driver version
49
 *********************************************************************/
50
 *********************************************************************/
50
char ixgbe_driver_version[] = "2.4.8";
51
char ixgbe_driver_version[] = "2.4.10";
51
52
52
/*********************************************************************
53
/*********************************************************************
53
 *  PCI Device ID Table
54
 *  PCI Device ID Table
Lines 83-88 Link Here
83
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, 0, 0, 0},
84
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF2, 0, 0, 0},
84
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, 0, 0, 0},
85
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_FCOE, 0, 0, 0},
85
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, 0, 0, 0},
86
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599EN_SFP, 0, 0, 0},
87
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_82599_SFP_SF_QP, 0, 0, 0},
86
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, 0, 0, 0},
88
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T1, 0, 0, 0},
87
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, 0, 0, 0},
89
	{IXGBE_INTEL_VENDOR_ID, IXGBE_DEV_ID_X540T, 0, 0, 0},
88
	/* required last entry */
90
	/* required last entry */
Lines 104-116 Link Here
104
static int      ixgbe_attach(device_t);
106
static int      ixgbe_attach(device_t);
105
static int      ixgbe_detach(device_t);
107
static int      ixgbe_detach(device_t);
106
static int      ixgbe_shutdown(device_t);
108
static int      ixgbe_shutdown(device_t);
107
static void     ixgbe_start(struct ifnet *);
108
static void     ixgbe_start_locked(struct tx_ring *, struct ifnet *);
109
#if __FreeBSD_version >= 800000
109
#if __FreeBSD_version >= 800000
110
static int	ixgbe_mq_start(struct ifnet *, struct mbuf *);
110
static int	ixgbe_mq_start(struct ifnet *, struct mbuf *);
111
static int	ixgbe_mq_start_locked(struct ifnet *,
111
static int	ixgbe_mq_start_locked(struct ifnet *,
112
                    struct tx_ring *, struct mbuf *);
112
                    struct tx_ring *, struct mbuf *);
113
static void	ixgbe_qflush(struct ifnet *);
113
static void	ixgbe_qflush(struct ifnet *);
114
static void	ixgbe_deferred_mq_start(void *, int);
115
#else
116
static void     ixgbe_start(struct ifnet *);
117
static void     ixgbe_start_locked(struct tx_ring *, struct ifnet *);
114
#endif
118
#endif
115
static int      ixgbe_ioctl(struct ifnet *, u_long, caddr_t);
119
static int      ixgbe_ioctl(struct ifnet *, u_long, caddr_t);
116
static void	ixgbe_init(void *);
120
static void	ixgbe_init(void *);
Lines 164-170 Link Here
164
static void	ixgbe_add_rx_process_limit(struct adapter *, const char *,
168
static void	ixgbe_add_rx_process_limit(struct adapter *, const char *,
165
		    const char *, int *, int);
169
		    const char *, int *, int);
166
static bool	ixgbe_tx_ctx_setup(struct tx_ring *, struct mbuf *);
170
static bool	ixgbe_tx_ctx_setup(struct tx_ring *, struct mbuf *);
167
static bool	ixgbe_tso_setup(struct tx_ring *, struct mbuf *, u32 *);
171
static bool	ixgbe_tso_setup(struct tx_ring *, struct mbuf *, u32 *, u32 *);
168
static void	ixgbe_set_ivar(struct adapter *, u8, u8, s8);
172
static void	ixgbe_set_ivar(struct adapter *, u8, u8, s8);
169
static void	ixgbe_configure_ivars(struct adapter *);
173
static void	ixgbe_configure_ivars(struct adapter *);
170
static u8 *	ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *);
174
static u8 *	ixgbe_mc_array_itr(struct ixgbe_hw *, u8 **, u32 *);
Lines 536-542 Link Here
536
	case IXGBE_ERR_SFP_NOT_SUPPORTED:
540
	case IXGBE_ERR_SFP_NOT_SUPPORTED:
537
		device_printf(dev,"Unsupported SFP+ Module\n");
541
		device_printf(dev,"Unsupported SFP+ Module\n");
538
		error = EIO;
542
		error = EIO;
539
		device_printf(dev,"Hardware Initialization Failure\n");
540
		goto err_late;
543
		goto err_late;
541
	case IXGBE_ERR_SFP_NOT_PRESENT:
544
	case IXGBE_ERR_SFP_NOT_PRESENT:
542
		device_printf(dev,"No SFP+ Module found\n");
545
		device_printf(dev,"No SFP+ Module found\n");
Lines 631-636 Link Here
631
{
634
{
632
	struct adapter *adapter = device_get_softc(dev);
635
	struct adapter *adapter = device_get_softc(dev);
633
	struct ix_queue *que = adapter->queues;
636
	struct ix_queue *que = adapter->queues;
637
	struct tx_ring	*txr = adapter->tx_rings;
634
	u32	ctrl_ext;
638
	u32	ctrl_ext;
635
639
636
	INIT_DEBUGOUT("ixgbe_detach: begin");
640
	INIT_DEBUGOUT("ixgbe_detach: begin");
Lines 645-652 Link Here
645
	ixgbe_stop(adapter);
649
	ixgbe_stop(adapter);
646
	IXGBE_CORE_UNLOCK(adapter);
650
	IXGBE_CORE_UNLOCK(adapter);
647
651
648
	for (int i = 0; i < adapter->num_queues; i++, que++) {
652
	for (int i = 0; i < adapter->num_queues; i++, que++, txr++) {
649
		if (que->tq) {
653
		if (que->tq) {
654
#if __FreeBSD_version >= 800000
655
			taskqueue_drain(que->tq, &txr->txq_task);
656
#endif
650
			taskqueue_drain(que->tq, &que->que_task);
657
			taskqueue_drain(que->tq, &que->que_task);
651
			taskqueue_free(que->tq);
658
			taskqueue_free(que->tq);
652
		}
659
		}
Lines 708-713 Link Here
708
}
715
}
709
716
710
717
718
#if __FreeBSD_version < 800000
711
/*********************************************************************
719
/*********************************************************************
712
 *  Transmit entry point
720
 *  Transmit entry point
713
 *
721
 *
Lines 726-740 Link Here
726
734
727
	IXGBE_TX_LOCK_ASSERT(txr);
735
	IXGBE_TX_LOCK_ASSERT(txr);
728
736
729
	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING|IFF_DRV_OACTIVE)) !=
737
	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
730
	    IFF_DRV_RUNNING)
731
		return;
738
		return;
732
	if (!adapter->link_active)
739
	if (!adapter->link_active)
733
		return;
740
		return;
734
741
735
	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
742
	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
736
		if (txr->tx_avail <= IXGBE_QUEUE_MIN_FREE) {
743
		if (txr->tx_avail <= IXGBE_QUEUE_MIN_FREE)
737
			txr->queue_status |= IXGBE_QUEUE_DEPLETED;
738
			break;
744
			break;
739
                }
745
                }
740
746
Lines 745-752 Link Here
745
		if (ixgbe_xmit(txr, &m_head)) {
751
		if (ixgbe_xmit(txr, &m_head)) {
746
			if (m_head != NULL)
752
			if (m_head != NULL)
747
				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
753
				IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
748
			if (txr->tx_avail <= IXGBE_QUEUE_MIN_FREE)
749
				txr->queue_status |= IXGBE_QUEUE_DEPLETED;
750
			break;
754
			break;
751
		}
755
		}
752
		/* Send a copy of the frame to the BPF listener */
756
		/* Send a copy of the frame to the BPF listener */
Lines 779-785 Link Here
779
	return;
783
	return;
780
}
784
}
781
785
782
#if __FreeBSD_version >= 800000
786
#else /* __FreeBSD_version >= 800000 */
783
/*
787
/*
784
** Multiqueue Transmit driver
788
** Multiqueue Transmit driver
785
**
789
**
Lines 795-813 Link Here
795
	/* Which queue to use */
799
	/* Which queue to use */
796
	if ((m->m_flags & M_FLOWID) != 0)
800
	if ((m->m_flags & M_FLOWID) != 0)
797
		i = m->m_pkthdr.flowid % adapter->num_queues;
801
		i = m->m_pkthdr.flowid % adapter->num_queues;
798
	else
799
		i = curcpu % adapter->num_queues;
800
802
801
	txr = &adapter->tx_rings[i];
803
	txr = &adapter->tx_rings[i];
802
	que = &adapter->queues[i];
804
	que = &adapter->queues[i];
803
805
804
	if (((txr->queue_status & IXGBE_QUEUE_DEPLETED) == 0) &&
806
	if (IXGBE_TX_TRYLOCK(txr)) {
805
	    IXGBE_TX_TRYLOCK(txr)) {
806
		err = ixgbe_mq_start_locked(ifp, txr, m);
807
		err = ixgbe_mq_start_locked(ifp, txr, m);
807
		IXGBE_TX_UNLOCK(txr);
808
		IXGBE_TX_UNLOCK(txr);
808
	} else {
809
	} else {
809
		err = drbr_enqueue(ifp, txr->br, m);
810
		err = drbr_enqueue(ifp, txr->br, m);
810
		taskqueue_enqueue(que->tq, &que->que_task);
811
		taskqueue_enqueue(que->tq, &txr->txq_task);
811
	}
812
	}
812
813
813
	return (err);
814
	return (err);
Lines 821-827 Link Here
821
        int             enqueued, err = 0;
822
        int             enqueued, err = 0;
822
823
823
	if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) ||
824
	if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) ||
824
	    (txr->queue_status == IXGBE_QUEUE_DEPLETED) ||
825
	    adapter->link_active == 0) {
825
	    adapter->link_active == 0) {
826
		if (m != NULL)
826
		if (m != NULL)
827
			err = drbr_enqueue(ifp, txr->br, m);
827
			err = drbr_enqueue(ifp, txr->br, m);
Lines 851-862 Link Here
851
		ETHER_BPF_MTAP(ifp, next);
851
		ETHER_BPF_MTAP(ifp, next);
852
		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
852
		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
853
			break;
853
			break;
854
		if (txr->tx_avail < IXGBE_TX_OP_THRESHOLD)
855
			ixgbe_txeof(txr);
856
		if (txr->tx_avail < IXGBE_TX_OP_THRESHOLD) {
857
			txr->queue_status |= IXGBE_QUEUE_DEPLETED;
858
			break;
859
		}
860
		next = drbr_dequeue(ifp, txr->br);
854
		next = drbr_dequeue(ifp, txr->br);
861
	}
855
	}
862
856
Lines 873-878 Link Here
873
}
867
}
874
868
875
/*
869
/*
870
 * Called from a taskqueue to drain queued tx packets
871
 */
872
static void
873
ixgbe_deferred_mq_start(void *arg, int pending)
874
{
875
	struct tx_ring	*txr = arg;
876
	struct adapter	*adapter = txr->adapter;
877
	struct ifnet   *ifp = adapter->ifp;
878
879
	IXGBE_TX_LOCK(txr);
880
	if (!drbr_empty(ifp, txr->br))
881
		ixgbe_mq_start_locked(ifp, txr, NULL);
882
	IXGBE_TX_UNLOCK(txr);
883
}
884
885
/*
876
** Flush all ring buffers
886
** Flush all ring buffers
877
*/
887
*/
878
static void
888
static void
Lines 992-997 Link Here
992
			ifp->if_capenable ^= IFCAP_HWCSUM;
1002
			ifp->if_capenable ^= IFCAP_HWCSUM;
993
		if (mask & IFCAP_TSO4)
1003
		if (mask & IFCAP_TSO4)
994
			ifp->if_capenable ^= IFCAP_TSO4;
1004
			ifp->if_capenable ^= IFCAP_TSO4;
1005
#if __FreeBSD_version >= 900505
1006
		if (mask & IFCAP_TSO6)
1007
			ifp->if_capenable ^= IFCAP_TSO6;
1008
#endif
995
		if (mask & IFCAP_LRO)
1009
		if (mask & IFCAP_LRO)
996
			ifp->if_capenable ^= IFCAP_LRO;
1010
			ifp->if_capenable ^= IFCAP_LRO;
997
		if (mask & IFCAP_VLAN_HWTAGGING)
1011
		if (mask & IFCAP_VLAN_HWTAGGING)
Lines 1056-1062 Link Here
1056
1070
1057
	/* Set the various hardware offload abilities */
1071
	/* Set the various hardware offload abilities */
1058
	ifp->if_hwassist = 0;
1072
	ifp->if_hwassist = 0;
1059
	if (ifp->if_capenable & IFCAP_TSO4)
1073
	if (ifp->if_capenable & IFCAP_TSO)
1060
		ifp->if_hwassist |= CSUM_TSO;
1074
		ifp->if_hwassist |= CSUM_TSO;
1061
	if (ifp->if_capenable & IFCAP_TXCSUM) {
1075
	if (ifp->if_capenable & IFCAP_TXCSUM) {
1062
		ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP);
1076
		ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP);
Lines 1145-1151 Link Here
1145
		 * from the Intel linux driver 3.8.21.
1159
		 * from the Intel linux driver 3.8.21.
1146
		 * Prefetching enables tx line rate even with 1 queue.
1160
		 * Prefetching enables tx line rate even with 1 queue.
1147
		 */
1161
		 */
1148
		txdctl |= (16 << 0) | (1 << 8);
1162
		txdctl |= (32 << 0) | (1 << 8);
1149
		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl);
1163
		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), txdctl);
1150
	}
1164
	}
1151
1165
Lines 1390-1396 Link Here
1390
			ixgbe_start_locked(txr, ifp);
1404
			ixgbe_start_locked(txr, ifp);
1391
#endif
1405
#endif
1392
		IXGBE_TX_UNLOCK(txr);
1406
		IXGBE_TX_UNLOCK(txr);
1393
		if (more || (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
1407
		if (more) {
1394
			taskqueue_enqueue(que->tq, &que->que_task);
1408
			taskqueue_enqueue(que->tq, &que->que_task);
1395
			return;
1409
			return;
1396
		}
1410
		}
Lines 1648-1654 Link Here
1648
			ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
1662
			ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
1649
			break;
1663
			break;
1650
		case IXGBE_LINK_SPEED_1GB_FULL:
1664
		case IXGBE_LINK_SPEED_1GB_FULL:
1651
			ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
1665
			ifmr->ifm_active |= adapter->optics | IFM_FDX;
1652
			break;
1666
			break;
1653
		case IXGBE_LINK_SPEED_10GB_FULL:
1667
		case IXGBE_LINK_SPEED_10GB_FULL:
1654
			ifmr->ifm_active |= adapter->optics | IFM_FDX;
1668
			ifmr->ifm_active |= adapter->optics | IFM_FDX;
Lines 1776-1785 Link Here
1776
	}
1790
	}
1777
1791
1778
	/* Make certain there are enough descriptors */
1792
	/* Make certain there are enough descriptors */
1779
	if (nsegs > txr->tx_avail - 2) {
1793
	if ((nsegs + 1) > txr->tx_avail - 2) {
1780
		txr->no_desc_avail++;
1794
		txr->no_desc_avail++;
1781
		error = ENOBUFS;
1795
		bus_dmamap_unload(txr->txtag, map);
1782
		goto xmit_fail;
1796
		return (ENOBUFS);
1783
	}
1797
	}
1784
	m_head = *m_headp;
1798
	m_head = *m_headp;
1785
1799
Lines 1789-1797 Link Here
1789
	** a packet.
1803
	** a packet.
1790
	*/
1804
	*/
1791
	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1805
	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1792
		if (ixgbe_tso_setup(txr, m_head, &paylen)) {
1806
		if (ixgbe_tso_setup(txr, m_head, &paylen, &olinfo_status)) {
1793
			cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
1807
			cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
1794
			olinfo_status |= IXGBE_TXD_POPTS_IXSM << 8;
1795
			olinfo_status |= IXGBE_TXD_POPTS_TXSM << 8;
1808
			olinfo_status |= IXGBE_TXD_POPTS_TXSM << 8;
1796
			olinfo_status |= paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
1809
			olinfo_status |= paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
1797
			++adapter->tso_tx;
1810
			++adapter->tso_tx;
Lines 1870-1879 Link Here
1870
1883
1871
	return (0);
1884
	return (0);
1872
1885
1873
xmit_fail:
1874
	bus_dmamap_unload(txr->txtag, txbuf->map);
1875
	return (error);
1876
1877
}
1886
}
1878
1887
1879
static void
1888
static void
Lines 1992-2004 Link Here
1992
{
2001
{
1993
	struct adapter	*adapter = arg;
2002
	struct adapter	*adapter = arg;
1994
	device_t	dev = adapter->dev;
2003
	device_t	dev = adapter->dev;
1995
	struct ifnet	*ifp = adapter->ifp;
1996
	struct ix_queue *que = adapter->queues;
2004
	struct ix_queue *que = adapter->queues;
1997
	struct tx_ring	*txr = adapter->tx_rings;
2005
	struct tx_ring	*txr = adapter->tx_rings;
1998
	int		hung, busy, paused;
2006
	int		hung = 0, paused = 0;
1999
2007
2000
	mtx_assert(&adapter->core_mtx, MA_OWNED);
2008
	mtx_assert(&adapter->core_mtx, MA_OWNED);
2001
	hung = busy = paused = 0;
2002
2009
2003
	/* Check for pluggable optics */
2010
	/* Check for pluggable optics */
2004
	if (adapter->sfp_probe)
2011
	if (adapter->sfp_probe)
Lines 2017-2043 Link Here
2017
2024
2018
	/*
2025
	/*
2019
	** Check the TX queues status
2026
	** Check the TX queues status
2020
	**      - central locked handling of OACTIVE
2021
	**      - watchdog only if all queues show hung
2027
	**      - watchdog only if all queues show hung
2022
	*/          
2028
	*/          
2023
	for (int i = 0; i < adapter->num_queues; i++, que++, txr++) {
2029
	for (int i = 0; i < adapter->num_queues; i++, que++, txr++) {
2024
		if ((txr->queue_status & IXGBE_QUEUE_HUNG) &&
2030
		if ((txr->queue_status & IXGBE_QUEUE_HUNG) &&
2025
		    (paused == 0))
2031
		    (paused == 0))
2026
			++hung;
2032
			++hung;
2027
		if (txr->queue_status & IXGBE_QUEUE_DEPLETED)
2028
			++busy;
2029
		if ((txr->queue_status & IXGBE_QUEUE_IDLE) == 0)
2033
		if ((txr->queue_status & IXGBE_QUEUE_IDLE) == 0)
2030
			taskqueue_enqueue(que->tq, &que->que_task);
2034
			taskqueue_enqueue(que->tq, &que->que_task);
2031
        }
2035
        }
2032
	/* Only truely watchdog if all queues show hung */
2036
	/* Only truely watchdog if all queues show hung */
2033
        if (hung == adapter->num_queues)
2037
        if (hung == adapter->num_queues)
2034
                goto watchdog;
2038
                goto watchdog;
2035
	/* Only turn off the stack flow when ALL are depleted */
2036
        if (busy == adapter->num_queues)
2037
                ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2038
        else if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) &&
2039
            (busy < adapter->num_queues))
2040
                ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2041
2039
2042
out:
2040
out:
2043
	ixgbe_rearm_queues(adapter, adapter->que_mask);
2041
	ixgbe_rearm_queues(adapter, adapter->que_mask);
Lines 2066-2072 Link Here
2066
ixgbe_update_link_status(struct adapter *adapter)
2064
ixgbe_update_link_status(struct adapter *adapter)
2067
{
2065
{
2068
	struct ifnet	*ifp = adapter->ifp;
2066
	struct ifnet	*ifp = adapter->ifp;
2069
	struct tx_ring *txr = adapter->tx_rings;
2070
	device_t dev = adapter->dev;
2067
	device_t dev = adapter->dev;
2071
2068
2072
2069
Lines 2087-2095 Link Here
2087
				device_printf(dev,"Link is Down\n");
2084
				device_printf(dev,"Link is Down\n");
2088
			if_link_state_change(ifp, LINK_STATE_DOWN);
2085
			if_link_state_change(ifp, LINK_STATE_DOWN);
2089
			adapter->link_active = FALSE;
2086
			adapter->link_active = FALSE;
2090
			for (int i = 0; i < adapter->num_queues;
2091
			    i++, txr++)
2092
				txr->queue_status = IXGBE_QUEUE_IDLE;
2093
		}
2087
		}
2094
	}
2088
	}
2095
2089
Lines 2192-2197 Link Here
2192
		return;
2186
		return;
2193
	}
2187
	}
2194
2188
2189
	if (layer & IXGBE_PHYSICAL_LAYER_1000BASE_SX) {
2190
		adapter->optics = IFM_1000_SX;
2191
		return;
2192
	}
2193
2195
	if (layer & (IXGBE_PHYSICAL_LAYER_10GBASE_LR |
2194
	if (layer & (IXGBE_PHYSICAL_LAYER_10GBASE_LR |
2196
	    IXGBE_PHYSICAL_LAYER_10GBASE_LRM)) {
2195
	    IXGBE_PHYSICAL_LAYER_10GBASE_LRM)) {
2197
		adapter->optics = IFM_10G_LR;
2196
		adapter->optics = IFM_10G_LR;
Lines 2229-2234 Link Here
2229
{
2228
{
2230
	device_t dev = adapter->dev;
2229
	device_t dev = adapter->dev;
2231
	struct		ix_queue *que = adapter->queues;
2230
	struct		ix_queue *que = adapter->queues;
2231
#if __FreeBSD_version >= 800000
2232
	struct tx_ring *txr = adapter->tx_rings;
2233
#endif
2232
	int error, rid = 0;
2234
	int error, rid = 0;
2233
2235
2234
	/* MSI RID at 1 */
2236
	/* MSI RID at 1 */
Lines 2248-2253 Link Here
2248
	 * Try allocating a fast interrupt and the associated deferred
2250
	 * Try allocating a fast interrupt and the associated deferred
2249
	 * processing contexts.
2251
	 * processing contexts.
2250
	 */
2252
	 */
2253
#if __FreeBSD_version >= 800000
2254
	TASK_INIT(&txr->txq_task, 0, ixgbe_deferred_mq_start, txr);
2255
#endif
2251
	TASK_INIT(&que->que_task, 0, ixgbe_handle_que, que);
2256
	TASK_INIT(&que->que_task, 0, ixgbe_handle_que, que);
2252
	que->tq = taskqueue_create_fast("ixgbe_que", M_NOWAIT,
2257
	que->tq = taskqueue_create_fast("ixgbe_que", M_NOWAIT,
2253
            taskqueue_thread_enqueue, &que->tq);
2258
            taskqueue_thread_enqueue, &que->tq);
Lines 2294-2302 Link Here
2294
{
2299
{
2295
	device_t        dev = adapter->dev;
2300
	device_t        dev = adapter->dev;
2296
	struct 		ix_queue *que = adapter->queues;
2301
	struct 		ix_queue *que = adapter->queues;
2302
	struct tx_ring	*txr = adapter->tx_rings;
2297
	int 		error, rid, vector = 0;
2303
	int 		error, rid, vector = 0;
2298
2304
2299
	for (int i = 0; i < adapter->num_queues; i++, vector++, que++) {
2305
	for (int i = 0; i < adapter->num_queues; i++, vector++, que++, txr++) {
2300
		rid = vector + 1;
2306
		rid = vector + 1;
2301
		que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2307
		que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2302
		    RF_SHAREABLE | RF_ACTIVE);
2308
		    RF_SHAREABLE | RF_ACTIVE);
Lines 2326-2331 Link Here
2326
		if (adapter->num_queues > 1)
2332
		if (adapter->num_queues > 1)
2327
			bus_bind_intr(dev, que->res, i);
2333
			bus_bind_intr(dev, que->res, i);
2328
2334
2335
#if __FreeBSD_version >= 800000
2336
		TASK_INIT(&txr->txq_task, 0, ixgbe_deferred_mq_start, txr);
2337
#endif
2329
		TASK_INIT(&que->que_task, 0, ixgbe_handle_que, que);
2338
		TASK_INIT(&que->que_task, 0, ixgbe_handle_que, que);
2330
		que->tq = taskqueue_create_fast("ixgbe_que", M_NOWAIT,
2339
		que->tq = taskqueue_create_fast("ixgbe_que", M_NOWAIT,
2331
		    taskqueue_thread_enqueue, &que->tq);
2340
		    taskqueue_thread_enqueue, &que->tq);
Lines 2569-2580 Link Here
2569
	ifp->if_softc = adapter;
2578
	ifp->if_softc = adapter;
2570
	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2579
	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2571
	ifp->if_ioctl = ixgbe_ioctl;
2580
	ifp->if_ioctl = ixgbe_ioctl;
2572
	ifp->if_start = ixgbe_start;
2573
#if __FreeBSD_version >= 800000
2581
#if __FreeBSD_version >= 800000
2574
	ifp->if_transmit = ixgbe_mq_start;
2582
	ifp->if_transmit = ixgbe_mq_start;
2575
	ifp->if_qflush = ixgbe_qflush;
2583
	ifp->if_qflush = ixgbe_qflush;
2584
#else
2585
	ifp->if_start = ixgbe_start;
2586
	IFQ_SET_MAXLEN(&ifp->if_snd, adapter->num_tx_desc - 2);
2576
#endif
2587
#endif
2577
	ifp->if_snd.ifq_maxlen = adapter->num_tx_desc - 2;
2578
2588
2579
	ether_ifattach(ifp, adapter->hw.mac.addr);
2589
	ether_ifattach(ifp, adapter->hw.mac.addr);
2580
2590
Lines 2586-2592 Link Here
2586
	 */
2596
	 */
2587
	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2597
	ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2588
2598
2589
	ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4 | IFCAP_VLAN_HWCSUM;
2599
	ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO | IFCAP_VLAN_HWCSUM;
2590
	ifp->if_capabilities |= IFCAP_JUMBO_MTU;
2600
	ifp->if_capabilities |= IFCAP_JUMBO_MTU;
2591
	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
2601
	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
2592
			     |  IFCAP_VLAN_HWTSO
2602
			     |  IFCAP_VLAN_HWTSO
Lines 3258-3263 Link Here
3258
		case ETHERTYPE_IPV6:
3268
		case ETHERTYPE_IPV6:
3259
			ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
3269
			ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
3260
			ip_hlen = sizeof(struct ip6_hdr);
3270
			ip_hlen = sizeof(struct ip6_hdr);
3271
			/* XXX-BZ this will go badly in case of ext hdrs. */
3261
			ipproto = ip6->ip6_nxt;
3272
			ipproto = ip6->ip6_nxt;
3262
			type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV6;
3273
			type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV6;
3263
			break;
3274
			break;
Lines 3316-3332 Link Here
3316
 *
3327
 *
3317
 **********************************************************************/
3328
 **********************************************************************/
3318
static bool
3329
static bool
3319
ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen)
3330
ixgbe_tso_setup(struct tx_ring *txr, struct mbuf *mp, u32 *paylen,
3331
    u32 *olinfo_status)
3320
{
3332
{
3321
	struct adapter *adapter = txr->adapter;
3333
	struct adapter *adapter = txr->adapter;
3322
	struct ixgbe_adv_tx_context_desc *TXD;
3334
	struct ixgbe_adv_tx_context_desc *TXD;
3323
	struct ixgbe_tx_buf        *tx_buffer;
3335
	struct ixgbe_tx_buf        *tx_buffer;
3324
	u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3336
	u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3325
	u32 mss_l4len_idx = 0;
3337
	u32 mss_l4len_idx = 0, len;
3326
	u16 vtag = 0;
3338
	u16 vtag = 0, eh_type;
3327
	int ctxd, ehdrlen,  hdrlen, ip_hlen, tcp_hlen;
3339
	int ctxd, ehdrlen, ip_hlen, tcp_hlen;
3328
	struct ether_vlan_header *eh;
3340
	struct ether_vlan_header *eh;
3341
#if ((__FreeBSD_version >= 900505) && defined(INET6))
3342
	struct ip6_hdr *ip6;
3343
#endif
3344
#ifdef INET
3329
	struct ip *ip;
3345
	struct ip *ip;
3346
#endif
3330
	struct tcphdr *th;
3347
	struct tcphdr *th;
3331
3348
3332
3349
Lines 3335-3366 Link Here
3335
	 * Jump over vlan headers if already present
3352
	 * Jump over vlan headers if already present
3336
	 */
3353
	 */
3337
	eh = mtod(mp, struct ether_vlan_header *);
3354
	eh = mtod(mp, struct ether_vlan_header *);
3338
	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) 
3355
	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
3339
		ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3356
		ehdrlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3340
	else
3357
		eh_type = eh->evl_proto;
3358
	} else {
3341
		ehdrlen = ETHER_HDR_LEN;
3359
		ehdrlen = ETHER_HDR_LEN;
3360
		eh_type = eh->evl_encap_proto;
3361
	}
3342
3362
3343
        /* Ensure we have at least the IP+TCP header in the first mbuf. */
3363
        /* Ensure we have at least the IP+TCP header in the first mbuf. */
3344
        if (mp->m_len < ehdrlen + sizeof(struct ip) + sizeof(struct tcphdr))
3364
	len = ehdrlen + sizeof(struct tcphdr);
3345
		return FALSE;
3365
	switch (ntohs(eh_type)) {
3366
#if ((__FreeBSD_version >= 900505) && defined(INET6))
3367
	case ETHERTYPE_IPV6:
3368
		if (mp->m_len < len + sizeof(struct ip6_hdr))
3369
			return FALSE;
3370
		ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
3371
		/* XXX-BZ For now we do not pretend to support ext. hdrs. */
3372
		if (ip6->ip6_nxt != IPPROTO_TCP)
3373
			return FALSE;
3374
		ip_hlen = sizeof(struct ip6_hdr);
3375
		th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
3376
		th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
3377
		type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV6;
3378
		break;
3379
#endif
3380
#ifdef INET
3381
	case ETHERTYPE_IP:
3382
		if (mp->m_len < len + sizeof(struct ip))
3383
			return FALSE;
3384
		ip = (struct ip *)(mp->m_data + ehdrlen);
3385
		if (ip->ip_p != IPPROTO_TCP)
3386
			return FALSE;
3387
		ip->ip_sum = 0;
3388
		ip_hlen = ip->ip_hl << 2;
3389
		th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
3390
		th->th_sum = in_pseudo(ip->ip_src.s_addr,
3391
		    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3392
		type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3393
		/* Tell transmit desc to also do IPv4 checksum. */
3394
		*olinfo_status |= IXGBE_TXD_POPTS_IXSM << 8;
3395
		break;
3396
#endif
3397
	default:
3398
		panic("%s: CSUM_TSO but no supported IP version (0x%04x)",
3399
		    __func__, ntohs(eh_type));
3400
		break;
3401
	}
3346
3402
3347
	ctxd = txr->next_avail_desc;
3403
	ctxd = txr->next_avail_desc;
3348
	tx_buffer = &txr->tx_buffers[ctxd];
3404
	tx_buffer = &txr->tx_buffers[ctxd];
3349
	TXD = (struct ixgbe_adv_tx_context_desc *) &txr->tx_base[ctxd];
3405
	TXD = (struct ixgbe_adv_tx_context_desc *) &txr->tx_base[ctxd];
3350
3406
3351
	ip = (struct ip *)(mp->m_data + ehdrlen);
3352
	if (ip->ip_p != IPPROTO_TCP)
3353
		return FALSE;   /* 0 */
3354
	ip->ip_sum = 0;
3355
	ip_hlen = ip->ip_hl << 2;
3356
	th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
3357
	th->th_sum = in_pseudo(ip->ip_src.s_addr,
3358
	    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
3359
	tcp_hlen = th->th_off << 2;
3407
	tcp_hlen = th->th_off << 2;
3360
	hdrlen = ehdrlen + ip_hlen + tcp_hlen;
3361
3408
3362
	/* This is used in the transmit desc in encap */
3409
	/* This is used in the transmit desc in encap */
3363
	*paylen = mp->m_pkthdr.len - hdrlen;
3410
	*paylen = mp->m_pkthdr.len - ehdrlen - ip_hlen - tcp_hlen;
3364
3411
3365
	/* VLAN MACLEN IPLEN */
3412
	/* VLAN MACLEN IPLEN */
3366
	if (mp->m_flags & M_VLANTAG) {
3413
	if (mp->m_flags & M_VLANTAG) {
Lines 3375-3384 Link Here
3375
	/* ADV DTYPE TUCMD */
3422
	/* ADV DTYPE TUCMD */
3376
	type_tucmd_mlhl |= IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
3423
	type_tucmd_mlhl |= IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
3377
	type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3424
	type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3378
	type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3379
	TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl);
3425
	TXD->type_tucmd_mlhl |= htole32(type_tucmd_mlhl);
3380
3426
3381
3382
	/* MSS L4LEN IDX */
3427
	/* MSS L4LEN IDX */
3383
	mss_l4len_idx |= (mp->m_pkthdr.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT);
3428
	mss_l4len_idx |= (mp->m_pkthdr.tso_segsz << IXGBE_ADVTXD_MSS_SHIFT);
3384
	mss_l4len_idx |= (tcp_hlen << IXGBE_ADVTXD_L4LEN_SHIFT);
3429
	mss_l4len_idx |= (tcp_hlen << IXGBE_ADVTXD_L4LEN_SHIFT);
Lines 3620-3629 Link Here
3620
	if ((!processed) && ((ticks - txr->watchdog_time) > IXGBE_WATCHDOG))
3665
	if ((!processed) && ((ticks - txr->watchdog_time) > IXGBE_WATCHDOG))
3621
		txr->queue_status = IXGBE_QUEUE_HUNG;
3666
		txr->queue_status = IXGBE_QUEUE_HUNG;
3622
3667
3623
	/* With a minimum free clear the depleted state bit.  */
3624
	if (txr->tx_avail > IXGBE_TX_CLEANUP_THRESHOLD)
3625
		txr->queue_status &= ~IXGBE_QUEUE_DEPLETED;
3626
3627
	if (txr->tx_avail == adapter->num_tx_desc) {
3668
	if (txr->tx_avail == adapter->num_tx_desc) {
3628
		txr->queue_status = IXGBE_QUEUE_IDLE;
3669
		txr->queue_status = IXGBE_QUEUE_IDLE;
3629
		return (FALSE);
3670
		return (FALSE);
Lines 3698-3718 Link Here
3698
			mp = rxbuf->m_pack;
3739
			mp = rxbuf->m_pack;
3699
3740
3700
		mp->m_pkthdr.len = mp->m_len = adapter->rx_mbuf_sz;
3741
		mp->m_pkthdr.len = mp->m_len = adapter->rx_mbuf_sz;
3701
		/* Get the memory mapping */
3742
3702
		error = bus_dmamap_load_mbuf_sg(rxr->ptag,
3743
		/* If we're dealing with an mbuf that was copied rather
3703
		    rxbuf->pmap, mp, pseg, &nsegs, BUS_DMA_NOWAIT);
3744
		 * than replaced, there's no need to go through busdma.
3704
		if (error != 0) {
3745
		 */
3705
			printf("Refresh mbufs: payload dmamap load"
3746
		if ((rxbuf->flags & IXGBE_RX_COPY) == 0) {
3706
			    " failure - %d\n", error);
3747
			/* Get the memory mapping */
3707
			m_free(mp);
3748
			error = bus_dmamap_load_mbuf_sg(rxr->ptag,
3708
			rxbuf->m_pack = NULL;
3749
			    rxbuf->pmap, mp, pseg, &nsegs, BUS_DMA_NOWAIT);
3709
			goto update;
3750
			if (error != 0) {
3751
				printf("Refresh mbufs: payload dmamap load"
3752
				    " failure - %d\n", error);
3753
				m_free(mp);
3754
				rxbuf->m_pack = NULL;
3755
				goto update;
3756
			}
3757
			rxbuf->m_pack = mp;
3758
			bus_dmamap_sync(rxr->ptag, rxbuf->pmap,
3759
			    BUS_DMASYNC_PREREAD);
3760
			rxbuf->paddr = rxr->rx_base[i].read.pkt_addr =
3761
			    htole64(pseg[0].ds_addr);
3762
		} else {
3763
			rxr->rx_base[i].read.pkt_addr = rxbuf->paddr;
3764
			rxbuf->flags &= ~IXGBE_RX_COPY;
3710
		}
3765
		}
3711
		rxbuf->m_pack = mp;
3712
		bus_dmamap_sync(rxr->ptag, rxbuf->pmap,
3713
		    BUS_DMASYNC_PREREAD);
3714
		rxr->rx_base[i].read.pkt_addr =
3715
		    htole64(pseg[0].ds_addr);
3716
3766
3717
		refreshed = TRUE;
3767
		refreshed = TRUE;
3718
		/* Next is precalculated */
3768
		/* Next is precalculated */
Lines 4025-4030 Link Here
4025
	rxr->next_to_refresh = 0;
4075
	rxr->next_to_refresh = 0;
4026
	rxr->lro_enabled = FALSE;
4076
	rxr->lro_enabled = FALSE;
4027
	rxr->rx_split_packets = 0;
4077
	rxr->rx_split_packets = 0;
4078
	rxr->rx_copies = 0;
4028
	rxr->rx_bytes = 0;
4079
	rxr->rx_bytes = 0;
4029
	rxr->discard = FALSE;
4080
	rxr->discard = FALSE;
4030
	rxr->vtag_strip = FALSE;
4081
	rxr->vtag_strip = FALSE;
Lines 4319-4333 Link Here
4319
{
4370
{
4320
                 
4371
                 
4321
        /*
4372
        /*
4322
         * ATM LRO is only for IPv4/TCP packets and TCP checksum of the packet
4373
         * ATM LRO is only for IP/TCP packets and TCP checksum of the packet
4323
         * should be computed by hardware. Also it should not have VLAN tag in
4374
         * should be computed by hardware. Also it should not have VLAN tag in
4324
         * ethernet header.
4375
         * ethernet header.  In case of IPv6 we do not yet support ext. hdrs.
4325
         */
4376
         */
4326
        if (rxr->lro_enabled &&
4377
        if (rxr->lro_enabled &&
4327
            (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
4378
            (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
4328
            (ptype & IXGBE_RXDADV_PKTTYPE_ETQF) == 0 &&
4379
            (ptype & IXGBE_RXDADV_PKTTYPE_ETQF) == 0 &&
4329
            (ptype & (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)) ==
4380
            ((ptype & (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP)) ==
4330
            (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP) &&
4381
            (IXGBE_RXDADV_PKTTYPE_IPV4 | IXGBE_RXDADV_PKTTYPE_TCP) ||
4382
            (ptype & (IXGBE_RXDADV_PKTTYPE_IPV6 | IXGBE_RXDADV_PKTTYPE_TCP)) ==
4383
            (IXGBE_RXDADV_PKTTYPE_IPV6 | IXGBE_RXDADV_PKTTYPE_TCP)) &&
4331
            (m->m_pkthdr.csum_flags & (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) ==
4384
            (m->m_pkthdr.csum_flags & (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) ==
4332
            (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) {
4385
            (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) {
4333
                /*
4386
                /*
Lines 4580-4593 Link Here
4580
			** that determines what we are
4633
			** that determines what we are
4581
			*/
4634
			*/
4582
			sendmp = rbuf->fmp;
4635
			sendmp = rbuf->fmp;
4583
			rbuf->m_pack = rbuf->fmp = NULL;
4584
4636
4585
			if (sendmp != NULL) {  /* secondary frag */
4637
			if (sendmp != NULL) {  /* secondary frag */
4638
				rbuf->m_pack = rbuf->fmp = NULL;
4586
				mp->m_flags &= ~M_PKTHDR;
4639
				mp->m_flags &= ~M_PKTHDR;
4587
				sendmp->m_pkthdr.len += mp->m_len;
4640
				sendmp->m_pkthdr.len += mp->m_len;
4588
			} else {
4641
			} else {
4642
				/*
4643
				 * Optimize.  This might be a small packet,
4644
				 * maybe just a TCP ACK.  Do a fast copy that
4645
				 * is cache aligned into a new mbuf, and
4646
				 * leave the old mbuf+cluster for re-use.
4647
				 */
4648
				if (eop && plen <= IXGBE_RX_COPY_LEN) {
4649
					sendmp = m_gethdr(M_DONTWAIT, MT_DATA);
4650
					if (sendmp != NULL) {
4651
						sendmp->m_data +=
4652
						    IXGBE_RX_COPY_ALIGN;
4653
						ixgbe_bcopy(mp->m_data,
4654
						    sendmp->m_data, plen);
4655
						sendmp->m_len = plen;
4656
						rxr->rx_copies++;
4657
						rbuf->flags |= IXGBE_RX_COPY;
4658
					}
4659
				}
4660
				if (sendmp == NULL) {
4661
					rbuf->m_pack = rbuf->fmp = NULL;
4662
					sendmp = mp;
4663
				}
4664
4589
				/* first desc of a non-ps chain */
4665
				/* first desc of a non-ps chain */
4590
				sendmp = mp;
4591
				sendmp->m_flags |= M_PKTHDR;
4666
				sendmp->m_flags |= M_PKTHDR;
4592
				sendmp->m_pkthdr.len = mp->m_len;
4667
				sendmp->m_pkthdr.len = mp->m_len;
4593
				if (staterr & IXGBE_RXD_STAT_VP) {
4668
				if (staterr & IXGBE_RXD_STAT_VP) {
Lines 5438-5443 Link Here
5438
		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes",
5513
		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes",
5439
				CTLFLAG_RD, &rxr->rx_bytes,
5514
				CTLFLAG_RD, &rxr->rx_bytes,
5440
				"Queue Bytes Received");
5515
				"Queue Bytes Received");
5516
		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_copies",
5517
				CTLFLAG_RD, &rxr->rx_copies,
5518
				"Copied RX Frames");
5441
		SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "lro_queued",
5519
		SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "lro_queued",
5442
				CTLFLAG_RD, &lro->lro_queued, 0,
5520
				CTLFLAG_RD, &lro->lro_queued, 0,
5443
				"LRO Queued");
5521
				"LRO Queued");
(-)ixgbe.h (+18 lines)
Lines 154-159 Link Here
154
#define IXGBE_FC_HI		0x20000
154
#define IXGBE_FC_HI		0x20000
155
#define IXGBE_FC_LO		0x10000
155
#define IXGBE_FC_LO		0x10000
156
156
157
/*
158
 * Used for optimizing small rx mbufs.  Effort is made to keep the copy
159
 * small and aligned for the CPU L1 cache.
160
 * 
161
 * MHLEN is typically 168 bytes, giving us 8-byte alignment.  Getting
162
 * 32 byte alignment needed for the fast bcopy results in 8 bytes being
163
 * wasted.  Getting 64 byte alignment, which _should_ be ideal for
164
 * modern Intel CPUs, results in 40 bytes wasted and a significant drop
165
 * in observed efficiency of the optimization, 97.9% -> 81.8%.
166
 */
167
#define IXGBE_RX_COPY_LEN	160
168
#define IXGBE_RX_COPY_ALIGN	(MHLEN - IXGBE_RX_COPY_LEN)
169
157
/* Keep older OS drivers building... */
170
/* Keep older OS drivers building... */
158
#if !defined(SYSCTL_ADD_UQUAD)
171
#if !defined(SYSCTL_ADD_UQUAD)
159
#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
172
#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
Lines 245-250 Link Here
245
	struct mbuf	*fmp;
258
	struct mbuf	*fmp;
246
	bus_dmamap_t	hmap;
259
	bus_dmamap_t	hmap;
247
	bus_dmamap_t	pmap;
260
	bus_dmamap_t	pmap;
261
	u_int		flags;
262
#define IXGBE_RX_COPY	0x01
263
	uint64_t	paddr;
248
};
264
};
249
265
250
/*
266
/*
Lines 298-303 Link Here
298
	char			mtx_name[16];
314
	char			mtx_name[16];
299
#if __FreeBSD_version >= 800000
315
#if __FreeBSD_version >= 800000
300
	struct buf_ring		*br;
316
	struct buf_ring		*br;
317
	struct task		txq_task;
301
#endif
318
#endif
302
#ifdef IXGBE_FDIR
319
#ifdef IXGBE_FDIR
303
	u16			atr_sample;
320
	u16			atr_sample;
Lines 339-344 Link Here
339
	/* Soft stats */
356
	/* Soft stats */
340
	u64			rx_irq;
357
	u64			rx_irq;
341
	u64			rx_split_packets;
358
	u64			rx_split_packets;
359
	u64			rx_copies;
342
	u64			rx_packets;
360
	u64			rx_packets;
343
	u64 			rx_bytes;
361
	u64 			rx_bytes;
344
	u64 			rx_discarded;
362
	u64 			rx_discarded;
(-)ixgbe_type.h (-4 / +7 lines)
Lines 38-46 Link Here
38
#include "ixgbe_osdep.h"
38
#include "ixgbe_osdep.h"
39
39
40
40
41
/* Vendor ID */
42
#define IXGBE_INTEL_VENDOR_ID			0x8086
43
44
/* Device IDs */
41
/* Device IDs */
45
#define IXGBE_DEV_ID_82598			0x10B6
42
#define IXGBE_DEV_ID_82598			0x10B6
46
#define IXGBE_DEV_ID_82598_BX			0x1508
43
#define IXGBE_DEV_ID_82598_BX			0x1508
Lines 62-72 Link Here
62
#define IXGBE_DEV_ID_82599_CX4			0x10F9
59
#define IXGBE_DEV_ID_82599_CX4			0x10F9
63
#define IXGBE_DEV_ID_82599_SFP			0x10FB
60
#define IXGBE_DEV_ID_82599_SFP			0x10FB
64
#define IXGBE_SUBDEV_ID_82599_SFP		0x11A9
61
#define IXGBE_SUBDEV_ID_82599_SFP		0x11A9
62
#define IXGBE_SUBDEV_ID_82599_RNDC		0x1F72
65
#define IXGBE_SUBDEV_ID_82599_560FLR		0x17D0
63
#define IXGBE_SUBDEV_ID_82599_560FLR		0x17D0
64
#define IXGBE_SUBDEV_ID_82599_ECNA_DP		0x0470
66
#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE	0x152A
65
#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE	0x152A
67
#define IXGBE_DEV_ID_82599_SFP_FCOE		0x1529
66
#define IXGBE_DEV_ID_82599_SFP_FCOE		0x1529
68
#define IXGBE_DEV_ID_82599_SFP_EM		0x1507
67
#define IXGBE_DEV_ID_82599_SFP_EM		0x1507
69
#define IXGBE_DEV_ID_82599_SFP_SF2		0x154D
68
#define IXGBE_DEV_ID_82599_SFP_SF2		0x154D
69
#define IXGBE_DEV_ID_82599_SFP_SF_QP		0x154A
70
#define IXGBE_DEV_ID_82599EN_SFP		0x1557
70
#define IXGBE_DEV_ID_82599EN_SFP		0x1557
71
#define IXGBE_DEV_ID_82599_XAUI_LOM		0x10FC
71
#define IXGBE_DEV_ID_82599_XAUI_LOM		0x10FC
72
#define IXGBE_DEV_ID_82599_T3_LOM		0x151C
72
#define IXGBE_DEV_ID_82599_T3_LOM		0x151C
Lines 1014-1019 Link Here
1014
#define IXGBE_RSCCTL_MAXDESC_4	0x04
1014
#define IXGBE_RSCCTL_MAXDESC_4	0x04
1015
#define IXGBE_RSCCTL_MAXDESC_8	0x08
1015
#define IXGBE_RSCCTL_MAXDESC_8	0x08
1016
#define IXGBE_RSCCTL_MAXDESC_16	0x0C
1016
#define IXGBE_RSCCTL_MAXDESC_16	0x0C
1017
#define IXGBE_RSCCTL_TS_DIS	0x02
1017
1018
1018
/* RSCDBU Bit Masks */
1019
/* RSCDBU Bit Masks */
1019
#define IXGBE_RSCDBU_RSCSMALDIS_MASK	0x0000007F
1020
#define IXGBE_RSCDBU_RSCSMALDIS_MASK	0x0000007F
Lines 1026-1032 Link Here
1026
#define IXGBE_RDRXCTL_DMAIDONE		0x00000008 /* DMA init cycle done */
1027
#define IXGBE_RDRXCTL_DMAIDONE		0x00000008 /* DMA init cycle done */
1027
#define IXGBE_RDRXCTL_AGGDIS		0x00010000 /* Aggregation disable */
1028
#define IXGBE_RDRXCTL_AGGDIS		0x00010000 /* Aggregation disable */
1028
#define IXGBE_RDRXCTL_RSCFRSTSIZE	0x003E0000 /* RSC First packet size */
1029
#define IXGBE_RDRXCTL_RSCFRSTSIZE	0x003E0000 /* RSC First packet size */
1029
#define IXGBE_RDRXCTL_RSCLLIDIS		0x00800000 /* Disabl RSC compl on LLI */
1030
#define IXGBE_RDRXCTL_RSCLLIDIS		0x00800000 /* Disable RSC compl on LLI*/
1030
#define IXGBE_RDRXCTL_RSCACKC		0x02000000 /* must set 1 when RSC ena */
1031
#define IXGBE_RDRXCTL_RSCACKC		0x02000000 /* must set 1 when RSC ena */
1031
#define IXGBE_RDRXCTL_FCOE_WRFIX	0x04000000 /* must set 1 when RSC ena */
1032
#define IXGBE_RDRXCTL_FCOE_WRFIX	0x04000000 /* must set 1 when RSC ena */
1032
1033
Lines 1590-1595 Link Here
1590
#define IXGBE_ESDP_SDP7		0x00000080 /* SDP7 Data Value */
1591
#define IXGBE_ESDP_SDP7		0x00000080 /* SDP7 Data Value */
1591
#define IXGBE_ESDP_SDP0_DIR	0x00000100 /* SDP0 IO direction */
1592
#define IXGBE_ESDP_SDP0_DIR	0x00000100 /* SDP0 IO direction */
1592
#define IXGBE_ESDP_SDP1_DIR	0x00000200 /* SDP1 IO direction */
1593
#define IXGBE_ESDP_SDP1_DIR	0x00000200 /* SDP1 IO direction */
1594
#define IXGBE_ESDP_SDP2_DIR	0x00000400 /* SDP1 IO direction */
1593
#define IXGBE_ESDP_SDP3_DIR	0x00000800 /* SDP3 IO direction */
1595
#define IXGBE_ESDP_SDP3_DIR	0x00000800 /* SDP3 IO direction */
1594
#define IXGBE_ESDP_SDP4_DIR	0x00001000 /* SDP4 IO direction */
1596
#define IXGBE_ESDP_SDP4_DIR	0x00001000 /* SDP4 IO direction */
1595
#define IXGBE_ESDP_SDP5_DIR	0x00002000 /* SDP5 IO direction */
1597
#define IXGBE_ESDP_SDP5_DIR	0x00002000 /* SDP5 IO direction */
Lines 3142-3147 Link Here
3142
	u16 subsystem_vendor_id;
3144
	u16 subsystem_vendor_id;
3143
	u8 revision_id;
3145
	u8 revision_id;
3144
	bool adapter_stopped;
3146
	bool adapter_stopped;
3147
	int api_version;
3145
	bool force_full_reset;
3148
	bool force_full_reset;
3146
	bool allow_unsupported_sfp;
3149
	bool allow_unsupported_sfp;
3147
};
3150
};
(-)ixgbe_mbx.h (+12 lines)
Lines 84-92 Link Here
84
#define IXGBE_VF_SET_MAC_ADDR	0x02 /* VF requests PF to set MAC addr */
84
#define IXGBE_VF_SET_MAC_ADDR	0x02 /* VF requests PF to set MAC addr */
85
#define IXGBE_VF_SET_MULTICAST	0x03 /* VF requests PF to set MC addr */
85
#define IXGBE_VF_SET_MULTICAST	0x03 /* VF requests PF to set MC addr */
86
#define IXGBE_VF_SET_VLAN	0x04 /* VF requests PF to set VLAN */
86
#define IXGBE_VF_SET_VLAN	0x04 /* VF requests PF to set VLAN */
87
88
/* mailbox API, version 1.0 VF requests */
87
#define IXGBE_VF_SET_LPE	0x05 /* VF requests PF to set VMOLR.LPE */
89
#define IXGBE_VF_SET_LPE	0x05 /* VF requests PF to set VMOLR.LPE */
88
#define IXGBE_VF_SET_MACVLAN	0x06 /* VF requests PF for unicast filter */
90
#define IXGBE_VF_SET_MACVLAN	0x06 /* VF requests PF for unicast filter */
91
#define IXGBE_VF_API_NEGOTIATE	0x08 /* negotiate API version */
89
92
93
/* mailbox API, version 1.1 VF requests */
94
#define IXGBE_VF_GET_QUEUES	0x09 /* get queue configuration */
95
96
/* GET_QUEUES return data indices within the mailbox */
97
#define IXGBE_VF_TX_QUEUES	1	/* number of Tx queues supported */
98
#define IXGBE_VF_RX_QUEUES	2	/* number of Rx queues supported */
99
#define IXGBE_VF_TRANS_VLAN	3	/* Indication of port vlan */
100
#define IXGBE_VF_DEF_QUEUE	4	/* Default queue offset */
101
90
/* length of permanent address message returned from PF */
102
/* length of permanent address message returned from PF */
91
#define IXGBE_VF_PERMADDR_MSG_LEN	4
103
#define IXGBE_VF_PERMADDR_MSG_LEN	4
92
/* word in permanent address message with the current multicast type */
104
/* word in permanent address message with the current multicast type */
(-)ixgbe_x540.c (+2 lines)
Lines 116-121 Link Here
116
	mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
116
	mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
117
	mac->ops.check_link = &ixgbe_check_mac_link_generic;
117
	mac->ops.check_link = &ixgbe_check_mac_link_generic;
118
118
119
119
	mac->mcft_size		= 128;
120
	mac->mcft_size		= 128;
120
	mac->vft_size		= 128;
121
	mac->vft_size		= 128;
121
	mac->num_rar_entries	= 128;
122
	mac->num_rar_entries	= 128;
Lines 973-975 Link Here
973
	return IXGBE_SUCCESS;
974
	return IXGBE_SUCCESS;
974
}
975
}
975
976
977
(-)ixgbe_vf.c (+67 lines)
Lines 142-147 Link Here
142
	/* Call adapter stop to disable tx/rx and clear interrupts */
142
	/* Call adapter stop to disable tx/rx and clear interrupts */
143
	hw->mac.ops.stop_adapter(hw);
143
	hw->mac.ops.stop_adapter(hw);
144
144
145
145
	DEBUGOUT("Issuing a function level reset to MAC\n");
146
	DEBUGOUT("Issuing a function level reset to MAC\n");
146
147
147
	ctrl = IXGBE_VFREAD_REG(hw, IXGBE_VFCTRL) | IXGBE_CTRL_RST;
148
	ctrl = IXGBE_VFREAD_REG(hw, IXGBE_VFCTRL) | IXGBE_CTRL_RST;
Lines 272-277 Link Here
272
	return vector;
273
	return vector;
273
}
274
}
274
275
276
static void ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw,
277
					u32 *msg, u16 size)
278
{
279
	struct ixgbe_mbx_info *mbx = &hw->mbx;
280
	u32 retmsg[IXGBE_VFMAILBOX_SIZE];
281
	s32 retval = mbx->ops.write_posted(hw, msg, size, 0);
282
283
	if (!retval)
284
		mbx->ops.read_posted(hw, retmsg, size, 0);
285
}
286
275
/**
287
/**
276
 *  ixgbe_set_rar_vf - set device MAC address
288
 *  ixgbe_set_rar_vf - set device MAC address
277
 *  @hw: pointer to hardware structure
289
 *  @hw: pointer to hardware structure
Lines 514-516 Link Here
514
	return IXGBE_SUCCESS;
526
	return IXGBE_SUCCESS;
515
}
527
}
516
528
529
/**
530
 *  ixgbevf_rlpml_set_vf - Set the maximum receive packet length
531
 *  @hw: pointer to the HW structure
532
 *  @max_size: value to assign to max frame size
533
 **/
534
void ixgbevf_rlpml_set_vf(struct ixgbe_hw *hw, u16 max_size)
535
{
536
	u32 msgbuf[2];
537
538
	msgbuf[0] = IXGBE_VF_SET_LPE;
539
	msgbuf[1] = max_size;
540
	ixgbevf_write_msg_read_ack(hw, msgbuf, 2);
541
}
542
543
/**
544
 *  ixgbevf_negotiate_api_version - Negotiate supported API version
545
 *  @hw: pointer to the HW structure
546
 *  @api: integer containing requested API version
547
 **/
548
int ixgbevf_negotiate_api_version(struct ixgbe_hw *hw, int api)
549
{
550
	int err;
551
	u32 msg[3];
552
553
	/* Negotiate the mailbox API version */
554
	msg[0] = IXGBE_VF_API_NEGOTIATE;
555
	msg[1] = api;
556
	msg[2] = 0;
557
	err = hw->mbx.ops.write_posted(hw, msg, 3, 0);
558
559
	if (!err)
560
		err = hw->mbx.ops.read_posted(hw, msg, 3, 0);
561
562
	if (!err) {
563
		msg[0] &= ~IXGBE_VT_MSGTYPE_CTS;
564
565
		/* Store value and return 0 on success */
566
		if (msg[0] == (IXGBE_VF_API_NEGOTIATE | IXGBE_VT_MSGTYPE_ACK)) {
567
			hw->api_version = api;
568
			return 0;
569
		}
570
571
		err = IXGBE_ERR_INVALID_ARGUMENT;
572
	}
573
574
	return err;
575
}
576
577
int ixgbevf_get_queues(struct ixgbe_hw *hw, unsigned int *num_tcs,
578
		       unsigned int *default_tc)
579
{
580
	UNREFERENCED_3PARAMETER(hw, num_tcs, default_tc);
581
	return IXGBE_SUCCESS;
582
}
583
(-)ixgbe_osdep.h (+27 lines)
Lines 69-80 Link Here
69
	#define DEBUGOUT1(S,A)      printf(S "\n",A)
69
	#define DEBUGOUT1(S,A)      printf(S "\n",A)
70
	#define DEBUGOUT2(S,A,B)    printf(S "\n",A,B)
70
	#define DEBUGOUT2(S,A,B)    printf(S "\n",A,B)
71
	#define DEBUGOUT3(S,A,B,C)  printf(S "\n",A,B,C)
71
	#define DEBUGOUT3(S,A,B,C)  printf(S "\n",A,B,C)
72
	#define DEBUGOUT4(S,A,B,C,D)  printf(S "\n",A,B,C,D)
73
	#define DEBUGOUT5(S,A,B,C,D,E)  printf(S "\n",A,B,C,D,E)
74
	#define DEBUGOUT6(S,A,B,C,D,E,F)  printf(S "\n",A,B,C,D,E,F)
72
	#define DEBUGOUT7(S,A,B,C,D,E,F,G)  printf(S "\n",A,B,C,D,E,F,G)
75
	#define DEBUGOUT7(S,A,B,C,D,E,F,G)  printf(S "\n",A,B,C,D,E,F,G)
73
#else
76
#else
74
	#define DEBUGOUT(S)
77
	#define DEBUGOUT(S)
75
	#define DEBUGOUT1(S,A)
78
	#define DEBUGOUT1(S,A)
76
	#define DEBUGOUT2(S,A,B)
79
	#define DEBUGOUT2(S,A,B)
77
	#define DEBUGOUT3(S,A,B,C)
80
	#define DEBUGOUT3(S,A,B,C)
81
	#define DEBUGOUT4(S,A,B,C,D)
82
	#define DEBUGOUT5(S,A,B,C,D,E)
78
	#define DEBUGOUT6(S,A,B,C,D,E,F)
83
	#define DEBUGOUT6(S,A,B,C,D,E,F)
79
	#define DEBUGOUT7(S,A,B,C,D,E,F,G)
84
	#define DEBUGOUT7(S,A,B,C,D,E,F,G)
80
#endif
85
#endif
Lines 86-91 Link Here
86
#define CMD_MEM_WRT_INVALIDATE          0x0010  /* BIT_4 */
91
#define CMD_MEM_WRT_INVALIDATE          0x0010  /* BIT_4 */
87
#define PCI_COMMAND_REGISTER            PCIR_COMMAND
92
#define PCI_COMMAND_REGISTER            PCIR_COMMAND
88
93
94
/* Shared code dropped this define.. */
95
#define IXGBE_INTEL_VENDOR_ID		0x8086
96
89
/* Bunch of defines for shared code bogosity */
97
/* Bunch of defines for shared code bogosity */
90
#define UNREFERENCED_PARAMETER(_p)
98
#define UNREFERENCED_PARAMETER(_p)
91
#define UNREFERENCED_1PARAMETER(_p)
99
#define UNREFERENCED_1PARAMETER(_p)
Lines 143-148 Link Here
143
#define prefetch(x)
151
#define prefetch(x)
144
#endif
152
#endif
145
153
154
/*
155
 * Optimized bcopy thanks to Luigi Rizzo's investigative work.  Assumes
156
 * non-overlapping regions and 32-byte padding on both src and dst.
157
 */
158
static __inline int
159
ixgbe_bcopy(void *_src, void *_dst, int l)
160
{
161
	uint64_t *src = _src;
162
	uint64_t *dst = _dst;
163
164
	for (; l > 0; l -= 32) {
165
		*dst++ = *src++;
166
		*dst++ = *src++;
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		*dst++ = *src++;
168
		*dst++ = *src++;
169
	}
170
	return (0);
171
}
172
146
struct ixgbe_osdep
173
struct ixgbe_osdep
147
{
174
{
148
	bus_space_tag_t    mem_bus_space_tag;
175
	bus_space_tag_t    mem_bus_space_tag;

Return to bug 176281