Attachment 133819 Details for Bug 178357 – address_sizes.diff

[patch] address_sizes.diff

address_sizes.diff (text/plain), 2.85 KB, created by Sofian Brabez on 2013-05-05 23:50:00 UTC

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Creator: Sofian Brabez

Created: 2013-05-05 23:50:00 UTC

Size: 2.85 KB

patch

obsolete

>Index: amd64/amd64/identcpu.c
>===================================================================
>--- amd64/amd64/identcpu.c	(revision 250287)
>+++ amd64/amd64/identcpu.c	(working copy)
>@@ -109,6 +109,12 @@
> SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD, 
>     &hw_clockrate, 0, "CPU instruction clock rate");
> 
>+SYSCTL_UINT(_machdep, OID_AUTO, cpu_physical_address_bits, CTLFLAG_RD,
>+    &cpu_pma_bits, 0, "CPU physical address bits");
>+
>+SYSCTL_UINT(_machdep, OID_AUTO, cpu_virtual_address_bits, CTLFLAG_RD,
>+    &cpu_vma_bits, 0, "CPU virtual address bits");
>+
> static eventhandler_tag tsc_post_tag;
> 
> static char cpu_brand[48];
>@@ -516,6 +522,16 @@
> 	cpu_feature = regs[3];
> 	cpu_feature2 = regs[2];
> 
>+	/* Intel CPUID Specification chapter 5.2.7 
>+	 * eax=0x80000008
>+	 * */
>+	do_cpuid(0x80000008, regs);
>+
>+	/* upper bits are virtual size */
>+	cpu_vma_bits = ((regs[0] >> 8) & 0xFF);
>+	/* lower bits are physical size */
>+	cpu_pma_bits = (regs[0] & 0xFF);
>+
> 	/*
> 	 * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
> 	 * function number again if it is set from BIOS.  It is necessary
>Index: amd64/amd64/initcpu.c
>===================================================================
>--- amd64/amd64/initcpu.c	(revision 250287)
>+++ amd64/amd64/initcpu.c	(working copy)
>@@ -66,10 +66,12 @@
> u_int	cpu_high;		/* Highest arg to CPUID */
> u_int	cpu_exthigh;		/* Highest arg to extended CPUID */
> u_int	cpu_id;			/* Stepping ID */
>+u_int	cpu_pma_bits;		/* CPU physical address bits */
> u_int	cpu_procinfo;		/* HyperThreading Info / Brand Index / CLFUSH */
> u_int	cpu_procinfo2;		/* Multicore info */
> char	cpu_vendor[20];		/* CPU Origin code */
> u_int	cpu_vendor_id;		/* CPU vendor ID */
>+u_int	cpu_vma_bits;		/* CPU virtual address bits */
> u_int	cpu_fxsr;		/* SSE enabled */
> u_int	cpu_mxcsr_mask;		/* Valid bits in mxcsr */
> u_int	cpu_clflush_line_size = 32;
>Index: amd64/include/md_var.h
>===================================================================
>--- amd64/include/md_var.h	(revision 250287)
>+++ amd64/include/md_var.h	(working copy)
>@@ -54,10 +54,12 @@
> extern	u_int	cpu_id;
> extern	u_int	cpu_max_ext_state_size;
> extern	u_int	cpu_mxcsr_mask;
>+extern u_int	cpu_pma_bits;
> extern	u_int	cpu_procinfo;
> extern	u_int	cpu_procinfo2;
> extern	char	cpu_vendor[];
> extern	u_int	cpu_vendor_id;
>+extern u_int	cpu_vma_bits;
> extern	char	ctx_switch_xsave[];
> extern	char	kstack[];
> extern	char	sigcode[];
>Index: compat/linprocfs/linprocfs.c
>===================================================================
>--- compat/linprocfs/linprocfs.c	(revision 250287)
>+++ compat/linprocfs/linprocfs.c	(working copy)
>@@ -310,6 +310,12 @@
> 		    fqmhz, fqkhz, fqmhz, fqkhz);
> 	}
> 
>+	if (cpu_vma_bits != 0 && cpu_vma_bits != 0) {
>+		sbuf_printf(sb,
>+		    "address sizes\t: %u bits physical, %u bits virtual\n",
>+		    cpu_pma_bits, cpu_vma_bits);
>+	}
>+
> 	return (0);
> }
> #endif /* __i386__ || __amd64__ */

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