Attachment #134397 for bug #179065

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--- ./cpuid.c.orig	2002-01-01 22:14:51.000000000 -0800
+++ ./cpuid.c	2013-05-28 13:14:27.000000000 -0700
@@ -3,34 +3,56 @@
  * Updated 24 Apr 2001 to latest Intel CPUID spec
  * Updated 22 Dec 2001 to decode Intel flag 28, hyper threading

+  "Mobile Intel Pentium III processor-M",
+  "Mobile Intel Celeron processor",
+  /* 8 */
+  "Intel Pentium 4 processor",
   "Intel Pentium 4 processor",
+  "Intel Pentium 4 processor",
+  "Intel Celeron processor",
+  "Intel Xeon processor",
+  "Intel Xeon processor MP",

 };
 
 #define cpuid(in,a,b,c,d)\
@@ -89,7 +111,7 @@
   exit(0);
 }
 

   "FPU    Floating Point Unit",
   "VME    Virtual 8086 Mode Enhancements",
   "DE     Debugging Extensions",
@@ -121,7 +143,66 @@
   "HT     Hyper Threading",
   "TM     Thermal monitor",
   "30     reserved",

+  "XSAVE    XSAVE/XSTOR states",
+  "OSXSAVE  OS-enabled extended state managerment",
+  "AVX      AVX extensions",
+  "F16C     Half-precision conversions",
+  "RDRAND   RDRAND Instruction",
+  NULL
+};
+
+char *Intel_ext_feature_flags[32] = {

 };
 
 /* Intel-specific information */
@@ -131,22 +212,31 @@
   if(maxi >= 1){
     /* Family/model/type etc */
     int clf,apic_id,feature_flags;

 
     printf("Type %d - ",type);
     switch(type){
@@ -183,10 +273,6 @@
       printf("Pentium 4");
     }
     printf("\n");

     printf("Model %d - ",model);
     switch(family){
     case 3:
@@ -253,33 +339,72 @@
       case 8:
 	printf("Pentium III/Pentium III Xeon - internal L2 cache");
 	break;

       if(maxe >= 0x80000004){
 	int i;
 
@@ -303,12 +428,48 @@
       printf("Hyper threading siblings: %d\n",siblings);
     }
 

     printf("\n");
   }
   if(maxi >= 2){
@@ -396,18 +557,66 @@
   case 0x4:
     printf("Data TLB: 4MB pages, 4-way set assoc, 8 entries\n");
     break;

   case 0x40:
     printf("No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n");
     break;
@@ -426,23 +635,67 @@
   case 0x45:
     printf("2nd-level cache: 2MB, 4-way set assoc, 32 byte line size\n");
     break;

     break;
   case 0x66:
     printf("1st-level data cache: 8KB, 4-way set assoc, 64 byte line size\n");
@@ -454,25 +707,37 @@
     printf("1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n");
     break;
   case 0x70:

     break;
   case 0x82:
     printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n");
@@ -486,44 +751,189 @@
   case 0x85:
     printf("2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n");
     break;

 };
 
 char *Assoc[] = {
@@ -657,10 +1067,16 @@
 	printf("Global Paging Extensions\n");
       } else {
 	if(edx & (1<<i)){

Return to bug 179065

Lines 1-5 Link Here

(-)misc/cpuid/files/patch-cpuid.c (-15 / +17 lines)
1	--- cpuid.c	1	--- ./cpuid.c.orig 2002-01-01 22:14:51.000000000 -0800
2	+++ cpuid.c	2	+++ ./cpuid.c 2013-05-28 13:14:27.000000000 -0700
3	@@ -3,34 +3,56 @@	3	@@ -3,34 +3,56 @@
4	* Updated 24 Apr 2001 to latest Intel CPUID spec	4	* Updated 24 Apr 2001 to latest Intel CPUID spec
5	* Updated 22 Dec 2001 to decode Intel flag 28, hyper threading	5	* Updated 22 Dec 2001 to decode Intel flag 28, hyper threading
Lines 45-52 Link Here
45	+ "Mobile Intel Pentium III processor-M",	45	+ "Mobile Intel Pentium III processor-M",
46	+ "Mobile Intel Celeron processor",	46	+ "Mobile Intel Celeron processor",
47	+ /* 8 */	47	+ /* 8 */
		48	+ "Intel Pentium 4 processor",
48	"Intel Pentium 4 processor",	49	"Intel Pentium 4 processor",
49	+ "Intel Pentium 4 processor",
50	+ "Intel Celeron processor",	50	+ "Intel Celeron processor",
51	+ "Intel Xeon processor",	51	+ "Intel Xeon processor",
52	+ "Intel Xeon processor MP",	52	+ "Intel Xeon processor MP",
Lines 65-71 Link Here
65	};	65	};
66		66
67	#define cpuid(in,a,b,c,d)\	67	#define cpuid(in,a,b,c,d)\
68	@@ -89,7 +110,7 @@	68	@@ -89,7 +111,7 @@
69	exit(0);	69	exit(0);
70	}	70	}
71		71
Lines 74-80 Link Here
74	"FPU Floating Point Unit",	74	"FPU Floating Point Unit",
75	"VME Virtual 8086 Mode Enhancements",	75	"VME Virtual 8086 Mode Enhancements",
76	"DE Debugging Extensions",	76	"DE Debugging Extensions",
77	@@ -121,7 +142,64 @@	77	@@ -121,7 +143,66 @@
78	"HT Hyper Threading",	78	"HT Hyper Threading",
79	"TM Thermal monitor",	79	"TM Thermal monitor",
80	"30 reserved",	80	"30 reserved",
Lines 112-118 Link Here
112	+ "XSAVE XSAVE/XSTOR states",	112	+ "XSAVE XSAVE/XSTOR states",
113	+ "OSXSAVE OS-enabled extended state managerment",	113	+ "OSXSAVE OS-enabled extended state managerment",
114	+ "AVX AVX extensions",	114	+ "AVX AVX extensions",
115	+ NULL, NULL, NULL	115	+ "F16C Half-precision conversions",
		116	+ "RDRAND RDRAND Instruction",
		117	+ NULL
116	+};	118	+};
117	+	119	+
118	+char *Intel_ext_feature_flags[32] = {	120	+char *Intel_ext_feature_flags[32] = {
Lines 140-146 Link Here
140	};	142	};
141		143
142	/* Intel-specific information */	144	/* Intel-specific information */
143	@@ -131,22 +209,31 @@	145	@@ -131,22 +212,31 @@
144	if(maxi >= 1){	146	if(maxi >= 1){
145	/* Family/model/type etc */	147	/* Family/model/type etc */
146	int clf,apic_id,feature_flags;	148	int clf,apic_id,feature_flags;
Lines 179-185 Link Here
179		181
180	printf("Type %d - ",type);	182	printf("Type %d - ",type);
181	switch(type){	183	switch(type){
182	@@ -183,10 +270,6 @@	184	@@ -183,10 +273,6 @@
183	printf("Pentium 4");	185	printf("Pentium 4");
184	}	186	}
185	printf("\n");	187	printf("\n");
Lines 190-196 Link Here
190	printf("Model %d - ",model);	192	printf("Model %d - ",model);
191	switch(family){	193	switch(family){
192	case 3:	194	case 3:
193	@@ -253,33 +336,72 @@	195	@@ -253,33 +339,72 @@
194	case 8:	196	case 8:
195	printf("Pentium III/Pentium III Xeon - internal L2 cache");	197	printf("Pentium III/Pentium III Xeon - internal L2 cache");
196	break;	198	break;
Lines 270-276 Link Here
270	if(maxe >= 0x80000004){	272	if(maxe >= 0x80000004){
271	int i;	273	int i;
272		274
273	@@ -303,12 +425,48 @@	275	@@ -303,12 +428,48 @@
274	printf("Hyper threading siblings: %d\n",siblings);	276	printf("Hyper threading siblings: %d\n",siblings);
275	}	277	}
276		278
Lines 320-326 Link Here
320	printf("\n");	322	printf("\n");
321	}	323	}
322	if(maxi >= 2){	324	if(maxi >= 2){
323	@@ -396,18 +554,66 @@	325	@@ -396,18 +557,66 @@
324	case 0x4:	326	case 0x4:
325	printf("Data TLB: 4MB pages, 4-way set assoc, 8 entries\n");	327	printf("Data TLB: 4MB pages, 4-way set assoc, 8 entries\n");
326	break;	328	break;
Lines 387-393 Link Here
387	case 0x40:	389	case 0x40:
388	printf("No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n");	390	printf("No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n");
389	break;	391	break;
390	@@ -426,23 +632,67 @@	392	@@ -426,23 +635,67 @@
391	case 0x45:	393	case 0x45:
392	printf("2nd-level cache: 2MB, 4-way set assoc, 32 byte line size\n");	394	printf("2nd-level cache: 2MB, 4-way set assoc, 32 byte line size\n");
393	break;	395	break;
Lines 461-467 Link Here
461	break;	463	break;
462	case 0x66:	464	case 0x66:
463	printf("1st-level data cache: 8KB, 4-way set assoc, 64 byte line size\n");	465	printf("1st-level data cache: 8KB, 4-way set assoc, 64 byte line size\n");
464	@@ -454,25 +704,37 @@	466	@@ -454,25 +707,37 @@
465	printf("1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n");	467	printf("1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n");
466	break;	468	break;
467	case 0x70:	469	case 0x70:
Lines 504-510 Link Here
504	break;	506	break;
505	case 0x82:	507	case 0x82:
506	printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n");	508	printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n");
507	@@ -486,44 +748,189 @@	509	@@ -486,44 +751,189 @@
508	case 0x85:	510	case 0x85:
509	printf("2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n");	511	printf("2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n");
510	break;	512	break;
Lines 726-732 Link Here
726	};	728	};
727		729
728	char *Assoc[] = {	730	char *Assoc[] = {
729	@@ -657,10 +1064,16 @@	731	@@ -657,10 +1067,16 @@
730	printf("Global Paging Extensions\n");	732	printf("Global Paging Extensions\n");
731	} else {	733	} else {
732	if(edx & (1<<i)){	734	if(edx & (1<<i)){