Attachment 134397 Details for Bug 179065 – file.diff

[patch] file.diff

file.diff (text/plain), 3.40 KB, created by Arthur Mesh on 2013-05-28 21:30:00 UTC

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Creator: Arthur Mesh

Created: 2013-05-28 21:30:00 UTC

Size: 3.40 KB

patch

obsolete

>Index: misc/cpuid/files/patch-cpuid.c
>===================================================================
>--- misc/cpuid/files/patch-cpuid.c	(revision 319319)
>+++ misc/cpuid/files/patch-cpuid.c	(working copy)
>@@ -1,5 +1,5 @@
>---- cpuid.c
>-+++ cpuid.c
>+--- ./cpuid.c.orig	2002-01-01 22:14:51.000000000 -0800
>++++ ./cpuid.c	2013-05-28 13:14:27.000000000 -0700
> @@ -3,34 +3,56 @@
>   * Updated 24 Apr 2001 to latest Intel CPUID spec
>   * Updated 22 Dec 2001 to decode Intel flag 28, hyper threading
>@@ -45,8 +45,8 @@
> +  "Mobile Intel Pentium III processor-M",
> +  "Mobile Intel Celeron processor",
> +  /* 8 */
>++  "Intel Pentium 4 processor",
>    "Intel Pentium 4 processor",
>-+  "Intel Pentium 4 processor",
> +  "Intel Celeron processor",
> +  "Intel Xeon processor",
> +  "Intel Xeon processor MP",
>@@ -65,7 +65,7 @@
>  };
>  
>  #define cpuid(in,a,b,c,d)\
>-@@ -89,7 +110,7 @@
>+@@ -89,7 +111,7 @@
>    exit(0);
>  }
>  
>@@ -74,7 +74,7 @@
>    "FPU    Floating Point Unit",
>    "VME    Virtual 8086 Mode Enhancements",
>    "DE     Debugging Extensions",
>-@@ -121,7 +142,64 @@
>+@@ -121,7 +143,66 @@
>    "HT     Hyper Threading",
>    "TM     Thermal monitor",
>    "30     reserved",
>@@ -112,7 +112,9 @@
> +  "XSAVE    XSAVE/XSTOR states",
> +  "OSXSAVE  OS-enabled extended state managerment",
> +  "AVX      AVX extensions",
>-+  NULL, NULL, NULL
>++  "F16C     Half-precision conversions",
>++  "RDRAND   RDRAND Instruction",
>++  NULL
> +};
> +
> +char *Intel_ext_feature_flags[32] = {
>@@ -140,7 +142,7 @@
>  };
>  
>  /* Intel-specific information */
>-@@ -131,22 +209,31 @@
>+@@ -131,22 +212,31 @@
>    if(maxi >= 1){
>      /* Family/model/type etc */
>      int clf,apic_id,feature_flags;
>@@ -179,7 +181,7 @@
>  
>      printf("Type %d - ",type);
>      switch(type){
>-@@ -183,10 +270,6 @@
>+@@ -183,10 +273,6 @@
>        printf("Pentium 4");
>      }
>      printf("\n");
>@@ -190,7 +192,7 @@
>      printf("Model %d - ",model);
>      switch(family){
>      case 3:
>-@@ -253,33 +336,72 @@
>+@@ -253,33 +339,72 @@
>        case 8:
>  	printf("Pentium III/Pentium III Xeon - internal L2 cache");
>  	break;
>@@ -270,7 +272,7 @@
>        if(maxe >= 0x80000004){
>  	int i;
>  
>-@@ -303,12 +425,48 @@
>+@@ -303,12 +428,48 @@
>        printf("Hyper threading siblings: %d\n",siblings);
>      }
>  
>@@ -320,7 +322,7 @@
>      printf("\n");
>    }
>    if(maxi >= 2){
>-@@ -396,18 +554,66 @@
>+@@ -396,18 +557,66 @@
>    case 0x4:
>      printf("Data TLB: 4MB pages, 4-way set assoc, 8 entries\n");
>      break;
>@@ -387,7 +389,7 @@
>    case 0x40:
>      printf("No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache\n");
>      break;
>-@@ -426,23 +632,67 @@
>+@@ -426,23 +635,67 @@
>    case 0x45:
>      printf("2nd-level cache: 2MB, 4-way set assoc, 32 byte line size\n");
>      break;
>@@ -461,7 +463,7 @@
>      break;
>    case 0x66:
>      printf("1st-level data cache: 8KB, 4-way set assoc, 64 byte line size\n");
>-@@ -454,25 +704,37 @@
>+@@ -454,25 +707,37 @@
>      printf("1st-level data cache: 32KB, 4-way set assoc, 64 byte line size\n");
>      break;
>    case 0x70:
>@@ -504,7 +506,7 @@
>      break;
>    case 0x82:
>      printf("2nd-level cache: 256KB, 8-way set assoc, 32 byte line size\n");
>-@@ -486,44 +748,189 @@
>+@@ -486,44 +751,189 @@
>    case 0x85:
>      printf("2nd-level cache: 2MB, 8-way set assoc, 32 byte line size\n");
>      break;
>@@ -726,7 +728,7 @@
>  };
>  
>  char *Assoc[] = {
>-@@ -657,10 +1064,16 @@
>+@@ -657,10 +1067,16 @@
>  	printf("Global Paging Extensions\n");
>        } else {
>  	if(edx & (1<<i)){

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Attachments on bug 179065: 134397