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Lines 57-63
int tsc_perf_stat;
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| 57 |
static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag; |
57 |
static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag; |
| 58 |
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58 |
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| 59 |
SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN, |
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SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN, |
| 60 |
&tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant"); |
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&tsc_is_invariant, 0, |
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"Indicates whether the TSC is ACPI P-, C- and T-state invariant"); |
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TUNABLE_INT("kern.timecounter.invariant_tsc", &tsc_is_invariant); |
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TUNABLE_INT("kern.timecounter.invariant_tsc", &tsc_is_invariant); |
| 62 |
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63 |
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| 63 |
#ifdef SMP |
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#ifdef SMP |
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Lines 272-280
probe_tsc_freq(void)
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| 272 |
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273 |
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| 273 |
switch (cpu_vendor_id) { |
274 |
switch (cpu_vendor_id) { |
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case CPU_VENDOR_AMD: |
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case CPU_VENDOR_AMD: |
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if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || |
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if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0) |
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(vm_guest == VM_GUEST_NO && |
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| 277 |
CPUID_TO_FAMILY(cpu_id) >= 0x10)) |
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tsc_is_invariant = 1; |
277 |
tsc_is_invariant = 1; |
| 279 |
if (cpu_feature & CPUID_SSE2) { |
278 |
if (cpu_feature & CPUID_SSE2) { |
| 280 |
tsc_timecounter.tc_get_timecount = |
279 |
tsc_timecounter.tc_get_timecount = |
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Lines 282-293
probe_tsc_freq(void)
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| 282 |
} |
281 |
} |
| 283 |
break; |
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break; |
| 284 |
case CPU_VENDOR_INTEL: |
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case CPU_VENDOR_INTEL: |
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if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 || |
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if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0) |
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(vm_guest == VM_GUEST_NO && |
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| 287 |
((CPUID_TO_FAMILY(cpu_id) == 0x6 && |
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CPUID_TO_MODEL(cpu_id) >= 0xe) || |
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(CPUID_TO_FAMILY(cpu_id) == 0xf && |
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CPUID_TO_MODEL(cpu_id) >= 0x3)))) |
| 291 |
tsc_is_invariant = 1; |
285 |
tsc_is_invariant = 1; |
| 292 |
if (cpu_feature & CPUID_SSE2) { |
286 |
if (cpu_feature & CPUID_SSE2) { |
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tsc_timecounter.tc_get_timecount = |
287 |
tsc_timecounter.tc_get_timecount = |
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Lines 554-573
init_TSC_tc(void)
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| 554 |
} |
548 |
} |
| 555 |
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| 556 |
/* |
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/* |
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* We cannot use the TSC if it stops incrementing in deep sleep. |
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| 558 |
* Currently only Intel CPUs are known for this problem unless |
| 559 |
* the invariant TSC bit is set. |
| 560 |
*/ |
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if (cpu_can_deep_sleep && cpu_vendor_id == CPU_VENDOR_INTEL && |
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(amd_pminfo & AMDPM_TSC_INVARIANT) == 0) { |
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tsc_timecounter.tc_quality = -1000; |
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tsc_timecounter.tc_flags |= TC_FLAGS_C3STOP; |
| 565 |
if (bootverbose) |
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printf("TSC timecounter disabled: C3 enabled.\n"); |
| 567 |
goto init; |
| 568 |
} |
| 569 |
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| 570 |
/* |
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* We can not use the TSC in SMP mode unless the TSCs on all CPUs |
551 |
* We can not use the TSC in SMP mode unless the TSCs on all CPUs |
| 572 |
* are synchronized. If the user is sure that the system has |
552 |
* are synchronized. If the user is sure that the system has |
| 573 |
* synchronized TSCs, set kern.timecounter.smp_tsc tunable to a |
553 |
* synchronized TSCs, set kern.timecounter.smp_tsc tunable to a |