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(-)b/sys/x86/x86/tsc.c (-24 / +4 lines)
Lines 57-63 int tsc_perf_stat; Link Here
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static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag;
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static eventhandler_tag tsc_levels_tag, tsc_pre_tag, tsc_post_tag;
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SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN,
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SYSCTL_INT(_kern_timecounter, OID_AUTO, invariant_tsc, CTLFLAG_RDTUN,
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    &tsc_is_invariant, 0, "Indicates whether the TSC is P-state invariant");
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    &tsc_is_invariant, 0,
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    "Indicates whether the TSC is ACPI P-, C- and T-state invariant");
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TUNABLE_INT("kern.timecounter.invariant_tsc", &tsc_is_invariant);
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TUNABLE_INT("kern.timecounter.invariant_tsc", &tsc_is_invariant);
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#ifdef SMP
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#ifdef SMP
Lines 272-280 probe_tsc_freq(void) Link Here
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	switch (cpu_vendor_id) {
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	switch (cpu_vendor_id) {
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	case CPU_VENDOR_AMD:
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	case CPU_VENDOR_AMD:
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		if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
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		if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0)
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		    (vm_guest == VM_GUEST_NO &&
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		    CPUID_TO_FAMILY(cpu_id) >= 0x10))
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			tsc_is_invariant = 1;
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			tsc_is_invariant = 1;
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		if (cpu_feature & CPUID_SSE2) {
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		if (cpu_feature & CPUID_SSE2) {
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			tsc_timecounter.tc_get_timecount =
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			tsc_timecounter.tc_get_timecount =
Lines 282-293 probe_tsc_freq(void) Link Here
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		}
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		}
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		break;
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		break;
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	case CPU_VENDOR_INTEL:
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	case CPU_VENDOR_INTEL:
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		if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
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		if ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0)
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		    (vm_guest == VM_GUEST_NO &&
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		    ((CPUID_TO_FAMILY(cpu_id) == 0x6 &&
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		    CPUID_TO_MODEL(cpu_id) >= 0xe) ||
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		    (CPUID_TO_FAMILY(cpu_id) == 0xf &&
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		    CPUID_TO_MODEL(cpu_id) >= 0x3))))
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			tsc_is_invariant = 1;
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			tsc_is_invariant = 1;
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		if (cpu_feature & CPUID_SSE2) {
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		if (cpu_feature & CPUID_SSE2) {
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			tsc_timecounter.tc_get_timecount =
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			tsc_timecounter.tc_get_timecount =
Lines 554-573 init_TSC_tc(void) Link Here
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	}
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	}
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	/*
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	/*
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	 * We cannot use the TSC if it stops incrementing in deep sleep.
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	 * Currently only Intel CPUs are known for this problem unless
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	 * the invariant TSC bit is set.
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	 */
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	if (cpu_can_deep_sleep && cpu_vendor_id == CPU_VENDOR_INTEL &&
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	    (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) {
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		tsc_timecounter.tc_quality = -1000;
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		tsc_timecounter.tc_flags |= TC_FLAGS_C3STOP;
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		if (bootverbose)
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			printf("TSC timecounter disabled: C3 enabled.\n");
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		goto init;
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	}
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	/*
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	 * We can not use the TSC in SMP mode unless the TSCs on all CPUs
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	 * We can not use the TSC in SMP mode unless the TSCs on all CPUs
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	 * are synchronized.  If the user is sure that the system has
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	 * are synchronized.  If the user is sure that the system has
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	 * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a
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	 * synchronized TSCs, set kern.timecounter.smp_tsc tunable to a

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