FreeBSD Bugzilla – Attachment 148617 Details for
Bug 192316
Invariant TSC gets misdetected on Intel Core 2 Duo processors, resulting in sluggish system behavior
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[patch]
always_disable.patch
192316.patch (text/plain), 3.50 KB, created by
John Baldwin
on 2014-10-24 15:06:29 UTC
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Description:
always_disable.patch
Filename:
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Creator:
John Baldwin
Created:
2014-10-24 15:06:29 UTC
Size:
3.50 KB
patch
obsolete
>diff --git a/sys/amd64/amd64/machdep.c b/sys/amd64/amd64/machdep.c >index 95d67c0..bfa9ea3 100644 >--- a/sys/amd64/amd64/machdep.c >+++ b/sys/amd64/amd64/machdep.c >@@ -824,6 +824,13 @@ cpu_idle(int busy) > #ifdef MP_WATCHDOG > ap_watchdog(PCPU_GET(cpuid)); > #endif >+ /* >+ * Don't sleep at all on Intel CPUs without a C-state invariant TSC >+ * if the TSC is being used as a timecounter. >+ */ >+ if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_disable_deep_sleep) >+ goto out; >+ > /* If we are busy - try to use fast methods. */ > if (busy) { > if ((cpu_feature2 & CPUID2_MON) && idle_mwait) { >diff --git a/sys/dev/acpica/acpi_cpu.c b/sys/dev/acpica/acpi_cpu.c >index 9350935..32ca2d3 100644 >--- a/sys/dev/acpica/acpi_cpu.c >+++ b/sys/dev/acpica/acpi_cpu.c >@@ -711,7 +711,6 @@ acpi_cpu_generic_cx_probe(struct acpi_cpu_softc *sc) > cx_ptr->trans_lat = AcpiGbl_FADT.C3Latency; > cx_ptr++; > sc->cpu_cx_count++; >- cpu_can_deep_sleep = 1; > } > } > } >@@ -803,8 +802,7 @@ acpi_cpu_cx_cst(struct acpi_cpu_softc *sc) > "acpi_cpu%d: C3[%d] not available.\n", > device_get_unit(sc->cpu_dev), i)); > continue; >- } else >- cpu_can_deep_sleep = 1; >+ } > break; > } > >diff --git a/sys/kern/kern_clocksource.c b/sys/kern/kern_clocksource.c >index 092c818..490b075 100644 >--- a/sys/kern/kern_clocksource.c >+++ b/sys/kern/kern_clocksource.c >@@ -59,7 +59,6 @@ __FBSDID("$FreeBSD$"); > cyclic_clock_func_t cyclic_clock_func = NULL; > #endif > >-int cpu_can_deep_sleep = 0; /* C3 state is available. */ > int cpu_disable_deep_sleep = 0; /* Timer dies in C3. */ > > static void setuptimer(void); >diff --git a/sys/sys/systm.h b/sys/sys/systm.h >index f4eae57..2b7a966 100644 >--- a/sys/sys/systm.h >+++ b/sys/sys/systm.h >@@ -289,7 +289,6 @@ sbintime_t cpu_idleclock(void); > void cpu_activeclock(void); > void cpu_new_callout(int cpu, sbintime_t bt, sbintime_t bt_opt); > void cpu_et_frequency(struct eventtimer *et, uint64_t newfreq); >-extern int cpu_can_deep_sleep; > extern int cpu_disable_deep_sleep; > > int cr_cansee(struct ucred *u1, struct ucred *u2); >diff --git a/sys/sys/timetc.h b/sys/sys/timetc.h >index 48b962f..3ff24cd 100644 >--- a/sys/sys/timetc.h >+++ b/sys/sys/timetc.h >@@ -58,7 +58,7 @@ struct timecounter { > * means "only use at explicit request". > */ > u_int tc_flags; >-#define TC_FLAGS_C3STOP 1 /* Timer dies in C3. */ >+#define TC_FLAGS_CxSTOP 1 /* Timer dies in C-states. */ > #define TC_FLAGS_SUSPEND_SAFE 2 /* > * Timer functional across > * suspend/resume. >diff --git a/sys/x86/x86/tsc.c b/sys/x86/x86/tsc.c >index b78e3c9..9e43f08 100644 >--- a/sys/x86/x86/tsc.c >+++ b/sys/x86/x86/tsc.c >@@ -581,16 +581,18 @@ init_TSC_tc(void) > } > > /* >- * We cannot use the TSC if it stops incrementing in deep sleep. >- * Currently only Intel CPUs are known for this problem unless >- * the invariant TSC bit is set. >+ * We cannot use the TSC if it stops incrementing while idle. >+ * Intel CPUs without a C-state invariant TSC can stop the TSC >+ * in C1 if C1E is enabled in the BIOS. There is no way to >+ * detect if C1E is enabled on these CPUs, so disable the TSC >+ * to be safe. > */ >- if (cpu_can_deep_sleep && cpu_vendor_id == CPU_VENDOR_INTEL && >+ if (cpu_vendor_id == CPU_VENDOR_INTEL && > (amd_pminfo & AMDPM_TSC_INVARIANT) == 0) { > tsc_timecounter.tc_quality = -1000; >- tsc_timecounter.tc_flags |= TC_FLAGS_C3STOP; >+ tsc_timecounter.tc_flags |= TC_FLAGS_CxSTOP; > if (bootverbose) >- printf("TSC timecounter disabled: C3 enabled.\n"); >+ printf("TSC timecounter disabled: C-states may halt it.\n"); > goto init; > } >
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bug 192316
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147407
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148617
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149826