Attachment 151195 Details for Bug 196423 – assembler files from failed build

assembler files from failed build

tmp-sqr_basecase.s (text/plain), 7.63 KB, created by Sean Bruno on 2015-01-01 19:07:56 UTC

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Creator: Sean Bruno

Created: 2015-01-01 19:07:56 UTC

Size: 7.63 KB

patch

obsolete

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>	.text
>	.align	3
>	.globl	__gmpn_sqr_basecase 
>	.type	__gmpn_sqr_basecase,#function
>__gmpn_sqr_basecase:
>	and	r12, r2, #3
>	cmp	r2, #4
>	addgt	r12, r12, #4
>	add	r15, r15, r12, lsl #2
>	nop
>	b	.L4
>	b	.L1
>	b	.L2
>	b	.L3
>	b	.L0m4
>	b	.L1m4
>	b	.L2m4
>	b	.L3m4
>
>
>.L1m4:	push	{r4-r10,r11,r14}
>	mov	r14, r2
>	sub	r8, r2, #4
>	sub	r2, r2, #2
>	add	r10, r15, #.Lam2_2m4-.-8
>	ldm	r1, {r3,r6,r7}
>	sub	r1, r1, #4
>	mov	r12, #0
>	mov	r5, #0
>	umull	r4, r11, r6, r3
>	str	r4, [r0], #-12
>	mov	r4, #0
>	b	.Lko0
>
>.L3m4:	push	{r4-r10,r11,r14}
>	mov	r14, r2
>	sub	r8, r2, #4
>	sub	r2, r2, #2
>	add	r10, r15, #.Lam2_0m4-.-8
>	ldm	r1, {r3,r6,r7}
>	add	r1, r1, #4
>	mov	r12, #0
>	mov	r5, #0
>	umull	r4, r11, r6, r3
>	str	r4, [r0], #-4
>	mov	r4, #0
>	b	.Lko2
>
>.L2m4:	push	{r4-r10,r11,r14}
>	mov	r14, r2
>	sub	r8, r2, #4
>	sub	r2, r2, #2
>	add	r10, r15, #.Lam2_3m4-.-8
>	ldm	r1, {r3,r6,r9}
>	mov	r12, #0
>	mov	r4, #0
>	umull	r5, r11, r6, r3
>	str	r5, [r0], #-8
>	mov	r5, #0
>	b	.Lko1
>
>.L0m4:	push	{r4-r10,r11,r14}
>	mov	r14, r2
>	sub	r8, r2, #4
>	sub	r2, r2, #2
>	add	r10, r15, #.Lam2_1m4-.-8
>	ldm	r1, {r3,r6,r9}
>	mov	r12, #0
>	mov	r4, #0
>	add	r1, r1, #8
>	umull	r5, r11, r6, r3
>	str	r5, [r0, #0]
>	mov	r5, #0
>
>.Ltop:	ldr	r7, [r1, #4]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #4]
>	mov	r4, #0
>	umaal	r5, r12, r9, r6
>.Lko2:	ldr	r9, [r1, #8]
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #8]
>	mov	r5, #0
>	umaal	r4, r12, r7, r6
>.Lko1:	ldr	r7, [r1, #12]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #12]
>	mov	r4, #0
>	umaal	r5, r12, r9, r6
>.Lko0:	ldr	r9, [r1, #16]!
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #16]!
>	mov	r5, #0
>	umaal	r4, r12, r7, r6
>	subs	r8, r8, #4
>	bhi	.Ltop
>	bx	r10
>
>.Levnloop:
>	subs	r8, r2, #4
>	sub	r2, r2, #2
>	blt	.Ltix
>	ldm	r1, {r3,r6,r7}
>	add	r1, r1, #4
>	mov	r11, #0
>	mov	r12, #0
>	ldm	r0, {r4,r5}
>	sub	r0, r0, #4
>	umaal	r4, r11, r6, r3
>	str	r4, [r0, #4]
>	ldr	r4, [r0, #12]
>	b	.Llo2
>.Lua2:	ldr	r7, [r1, #4]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #4]
>	ldr	r4, [r0, #12]
>	umaal	r5, r12, r9, r6
>.Llo2:	ldr	r9, [r1, #8]
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #8]
>	ldr	r5, [r0, #16]
>	umaal	r4, r12, r7, r6
>	ldr	r7, [r1, #12]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #12]
>	ldr	r4, [r0, #20]
>	umaal	r5, r12, r9, r6
>	ldr	r9, [r1, #16]!
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #16]!
>	ldr	r5, [r0, #8]
>	umaal	r4, r12, r7, r6
>	subs	r8, r8, #4
>	bhi	.Lua2
>.Lam2_0m4:
>	umaal	r4, r11, r9, r3
>	ldr	r7, [r1, #4]
>	umaal	r5, r12, r9, r6
>	str	r4, [r0, #4]
>	umaal	r5, r11, r7, r3
>	umaal	r11, r12, r7, r6
>	str	r5, [r0, #8]
>	str	r11, [r0, #12]
>	str	r12, [r0, #16]
>	sub	r1, r1, r2, lsl #2
>	sub	r0, r0, r2, lsl #2
>	add	r1, r1, #8
>	sub	r8, r2, #4
>	sub	r2, r2, #2
>	ldm	r1, {r3,r6,r7}
>	sub	r1, r1, #4
>	mov	r11, #0
>	mov	r12, #0
>	ldr	r4, [r0, #24]
>	ldr	r5, [r0, #28]
>	add	r0, r0, #12
>	umaal	r4, r11, r6, r3
>	str	r4, [r0, #12]
>	ldr	r4, [r0, #20]
>	b	.Llo0
>.Lua0:	ldr	r7, [r1, #4]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #4]
>	ldr	r4, [r0, #12]
>	umaal	r5, r12, r9, r6
>	ldr	r9, [r1, #8]
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #8]
>	ldr	r5, [r0, #16]
>	umaal	r4, r12, r7, r6
>	ldr	r7, [r1, #12]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #12]
>	ldr	r4, [r0, #20]
>	umaal	r5, r12, r9, r6
>.Llo0:	ldr	r9, [r1, #16]!
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #16]!
>	ldr	r5, [r0, #8]
>	umaal	r4, r12, r7, r6
>	subs	r8, r8, #4
>	bhi	.Lua0
>.Lam2_2m4:
>	umaal	r4, r11, r9, r3
>	ldr	r7, [r1, #4]
>	umaal	r5, r12, r9, r6
>	str	r4, [r0, #4]
>	umaal	r5, r11, r7, r3
>	umaal	r11, r12, r7, r6
>	str	r5, [r0, #8]
>	str	r11, [r0, #12]
>	str	r12, [r0, #16]
>	sub	r1, r1, r2, lsl #2
>	sub	r0, r0, r2, lsl #2
>	add	r1, r1, #8
>	add	r0, r0, #24
>	b	.Levnloop
>
>
>.Loddloop:
>	subs	r8, r2, #4
>	sub	r2, r2, #2
>	blt	.Lxit
>	ldm	r1, {r3,r6,r9}
>	mov	r11, #0
>	mov	r12, #0
>	sub	r0, r0, #8
>	ldr	r5, [r0, #8]
>	ldr	r4, [r0, #12]
>	umaal	r5, r11, r6, r3
>	str	r5, [r0, #8]
>	ldr	r5, [r0, #16]
>	b	.Llo1
>.Lua1:	ldr	r7, [r1, #4]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #4]
>	ldr	r4, [r0, #12]
>	umaal	r5, r12, r9, r6
>	ldr	r9, [r1, #8]
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #8]
>	ldr	r5, [r0, #16]
>	umaal	r4, r12, r7, r6
>.Llo1:	ldr	r7, [r1, #12]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #12]
>	ldr	r4, [r0, #20]
>	umaal	r5, r12, r9, r6
>	ldr	r9, [r1, #16]!
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #16]!
>	ldr	r5, [r0, #8]
>	umaal	r4, r12, r7, r6
>	subs	r8, r8, #4
>	bhi	.Lua1
>.Lam2_3m4:
>	umaal	r4, r11, r9, r3
>	ldr	r7, [r1, #4]
>	umaal	r5, r12, r9, r6
>	str	r4, [r0, #4]
>	umaal	r5, r11, r7, r3
>	umaal	r11, r12, r7, r6
>	str	r5, [r0, #8]
>	str	r11, [r0, #12]
>	str	r12, [r0, #16]
>	sub	r1, r1, r2, lsl #2
>	sub	r0, r0, r2, lsl #2
>	add	r1, r1, #8
>	add	r0, r0, #24
>	subs	r8, r2, #4
>	sub	r2, r2, #2
>	ldm	r1, {r3,r6,r9}
>	mov	r11, #0
>	mov	r12, #0
>	ldr	r5, [r0, #0]
>	ldr	r4, [r0, #4]
>	add	r1, r1, #8
>	umaal	r5, r11, r6, r3
>	str	r5, [r0, #0]
>	ldr	r5, [r0, #8]
>	bls	.Le3
>.Lua3:	ldr	r7, [r1, #4]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #4]
>	ldr	r4, [r0, #12]
>	umaal	r5, r12, r9, r6
>	ldr	r9, [r1, #8]
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #8]
>	ldr	r5, [r0, #16]
>	umaal	r4, r12, r7, r6
>	ldr	r7, [r1, #12]
>	umaal	r4, r11, r9, r3
>	str	r4, [r0, #12]
>	ldr	r4, [r0, #20]
>	umaal	r5, r12, r9, r6
>	ldr	r9, [r1, #16]!
>	umaal	r5, r11, r7, r3
>	str	r5, [r0, #16]!
>	ldr	r5, [r0, #8]
>	umaal	r4, r12, r7, r6
>	subs	r8, r8, #4
>	bhi	.Lua3
>.Le3:
>.Lam2_1m4:
>	umaal	r4, r11, r9, r3
>	ldr	r7, [r1, #4]
>	umaal	r5, r12, r9, r6
>	str	r4, [r0, #4]
>	umaal	r5, r11, r7, r3
>	umaal	r11, r12, r7, r6
>	str	r5, [r0, #8]
>	str	r11, [r0, #12]
>	str	r12, [r0, #16]
>	sub	r1, r1, r2, lsl #2
>	sub	r0, r0, r2, lsl #2
>	add	r1, r1, #8
>	add	r0, r0, #24
>	b	.Loddloop
>
>.Lxit:	ldm	r1!, {r3,r7}
>	ldr	r11, [r0], #12
>	mov	r12, #0
>	umaal	r11, r12, r7, r3
>	b	.Lsqr_diag_addlsh1
>
>.Ltix:	ldm	r1!, {r3,r6,r7}
>	ldm	r0, {r4,r5}
>	mov	r11, #0
>	mov	r12, #0
>	umaal	r4, r11, r6, r3
>	umaal	r5, r11, r7, r3
>	stm	r0, {r4,r5}
>	umaal	r11, r12, r7, r6
>	add	r0, r0, #20
>
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>.Lsqr_diag_addlsh1:
>	str	r11, [r0, #-12]
>	str	r12, [r0, #-8]
>	sub	r2, r14, #1
>	sub	r1, r1, r14, lsl #2
>	sub	r0, r0, r14, lsl #3
>	ldr	r3, [r1], #4
>	umull	r7, r5, r3, r3
>	mov	r8, #0
>
>	b	.Llm
>
>.Ltsd:	adds	r6, r6, r9
>	adcs	r7, r7, r4
>	str	r6, [r0, #0]
>.Llm:	ldr	r6, [r0, #4]
>	str	r7, [r0, #4]
>	ldr	r7, [r0, #8]!
>	add	r9, r5, r8
>	adcs	r6, r6, r6
>	ldr	r3, [r1], #4
>	adcs	r7, r7, r7
>	mov	r8, #0
>	adc	r8, r8, r8
>	umull	r4, r5, r3, r3
>	subs	r2, r2, #1
>	bne	.Ltsd
>
>	adds	r6, r6, r9
>	adcs	r7, r7, r4
>	adc	r8, r5, r8
>	stm	r0, {r6,r7,r8}
>
>	pop	{r4-r10,r11,r15}
>
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>.L1:	ldr	r3, [r1, #0]
>	umull	r1, r2, r3, r3
>	stm	r0, {r1,r2}
>	bx	r14
>
>.L2:	push	{r4-r5}
>	ldm	r1, {r5,r12}
>	umull	r1, r2, r5, r5
>	umull	r3, r4, r12, r12
>	umull	r5, r12, r5, r12
>	adds	r5, r5, r5
>	adcs	r12, r12, r12
>	adc	r4, r4, #0
>	adds	r2, r2, r5
>	adcs	r3, r3, r12
>	adc	r4, r4, #0
>	stm	r0, {r1,r2,r3,r4}
>	pop	{r4-r5}
>	bx	r14
>
>.L3:	push	{r4-r11}
>	ldm	r1, {r7,r8,r9}
>	umull	r1, r2, r7, r7
>	umull	r3, r4, r8, r8
>	umull	r5, r6, r9, r9
>	umull	r10, r11, r7, r8
>	mov	r12, #0
>	umlal	r11, r12, r7, r9
>	mov	r7, #0
>	umlal	r12, r7, r8, r9
>	adds	r10, r10, r10
>	adcs	r11, r11, r11
>	adcs	r12, r12, r12
>	adcs	r7, r7, r7
>	adc	r6, r6, #0
>	adds	r2, r2, r10
>	adcs	r3, r3, r11
>	adcs	r4, r4, r12
>	adcs	r5, r5, r7
>	adc	r6, r6, #0
>	stm	r0, {r1,r2,r3,r4,r5,r6}
>	pop	{r4-r11}
>	bx	r14
>
>.L4:	push	{r4-r11, r14}
>	ldm	r1, {r9,r10,r11,r12}
>	umull	r1, r2, r9, r9
>	umull	r3, r4, r10, r10
>	umull	r5, r6, r11, r11
>	umull	r7, r8, r12, r12
>	stm	r0, {r1,r2,r3,r4,r5,r6,r7}
>	umull	r1, r2, r9, r10
>	mov	r3, #0
>	umlal	r2, r3, r9, r11
>	mov	r4, #0
>	umlal	r3, r4, r9, r12
>	mov	r5, #0
>	umlal	r3, r5, r10, r11
>	umaal	r4, r5, r10, r12
>	mov	r6, #0
>	umlal	r5, r6, r11, r12
>	adds	r1, r1, r1
>	adcs	r2, r2, r2
>	adcs	r3, r3, r3
>	adcs	r4, r4, r4
>	adcs	r5, r5, r5
>	adcs	r6, r6, r6
>	adc	r7, r8, #0
>	add	r0, r0, #4
>	ldm	r0, {r8,r9,r10,r11,r12,r14}
>	adds	r1, r1, r8
>	adcs	r2, r2, r9
>	adcs	r3, r3, r10
>	adcs	r4, r4, r11
>	adcs	r5, r5, r12
>	adcs	r6, r6, r14
>	adc	r7, r7, #0
>	stm	r0, {r1,r2,r3,r4,r5,r6,r7}
>	pop	{r4-r11, r15}
>
>	.size	__gmpn_sqr_basecase,.-__gmpn_sqr_basecase

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Attachments on bug 196423: 151195