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Lines 84-89
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| 84 |
#define WRITE4(_sc, _reg, _val) \ |
84 |
#define WRITE4(_sc, _reg, _val) \ |
| 85 |
bus_write_4((_sc)->res[0], _reg, _val) |
85 |
bus_write_4((_sc)->res[0], _reg, _val) |
| 86 |
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86 |
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87 |
#define MAC_RESET_TIMEOUT 100 |
| 87 |
#define WATCHDOG_TIMEOUT_SECS 5 |
88 |
#define WATCHDOG_TIMEOUT_SECS 5 |
| 88 |
#define STATS_HARVEST_INTERVAL 2 |
89 |
#define STATS_HARVEST_INTERVAL 2 |
| 89 |
#define MII_CLK_VAL 2 |
90 |
#define MII_CLK_VAL 2 |
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Lines 1103-1121
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| 1103 |
sc->bst = rman_get_bustag(sc->res[0]); |
1104 |
sc->bst = rman_get_bustag(sc->res[0]); |
| 1104 |
sc->bsh = rman_get_bushandle(sc->res[0]); |
1105 |
sc->bsh = rman_get_bushandle(sc->res[0]); |
| 1105 |
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1106 |
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| 1106 |
mtx_init(&sc->mtx, device_get_nameunit(sc->dev), |
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| 1107 |
MTX_NETWORK_LOCK, MTX_DEF); |
| 1108 |
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| 1109 |
callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); |
| 1110 |
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| 1111 |
/* Setup interrupt handler. */ |
| 1112 |
error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, |
| 1113 |
NULL, dwc_intr, sc, &sc->intr_cookie); |
| 1114 |
if (error != 0) { |
| 1115 |
device_printf(dev, "could not setup interrupt handler.\n"); |
| 1116 |
return (ENXIO); |
| 1117 |
} |
| 1118 |
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| 1119 |
/* Read MAC before reset */ |
1107 |
/* Read MAC before reset */ |
| 1120 |
if (dwc_get_hwaddr(sc, macaddr)) { |
1108 |
if (dwc_get_hwaddr(sc, macaddr)) { |
| 1121 |
device_printf(sc->dev, "can't get mac\n"); |
1109 |
device_printf(sc->dev, "can't get mac\n"); |
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Lines 1127-1138
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| 1127 |
reg |= (BUS_MODE_SWR); |
1115 |
reg |= (BUS_MODE_SWR); |
| 1128 |
WRITE4(sc, BUS_MODE, reg); |
1116 |
WRITE4(sc, BUS_MODE, reg); |
| 1129 |
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1117 |
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| 1130 |
for (i = 0; i < 100; i++) { |
1118 |
for (i = 0; i < MAC_RESET_TIMEOUT; i++) { |
| 1131 |
if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) |
1119 |
if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) |
| 1132 |
break; |
1120 |
break; |
| 1133 |
DELAY(10); |
1121 |
DELAY(10); |
| 1134 |
} |
1122 |
} |
| 1135 |
if (i == 0) { |
1123 |
if (i >= MAC_RESET_TIMEOUT) { |
| 1136 |
device_printf(sc->dev, "Can't reset DWC.\n"); |
1124 |
device_printf(sc->dev, "Can't reset DWC.\n"); |
| 1137 |
return (ENXIO); |
1125 |
return (ENXIO); |
| 1138 |
} |
1126 |
} |
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Lines 1156-1161
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| 1156 |
WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); |
1144 |
WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); |
| 1157 |
WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); |
1145 |
WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); |
| 1158 |
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1146 |
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1147 |
mtx_init(&sc->mtx, device_get_nameunit(sc->dev), |
| 1148 |
MTX_NETWORK_LOCK, MTX_DEF); |
| 1149 |
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| 1150 |
callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); |
| 1151 |
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| 1152 |
/* Setup interrupt handler. */ |
| 1153 |
error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, |
| 1154 |
NULL, dwc_intr, sc, &sc->intr_cookie); |
| 1155 |
if (error != 0) { |
| 1156 |
device_printf(dev, "could not setup interrupt handler.\n"); |
| 1157 |
return (ENXIO); |
| 1158 |
} |
| 1159 |
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| 1159 |
/* Set up the ethernet interface. */ |
1160 |
/* Set up the ethernet interface. */ |
| 1160 |
sc->ifp = ifp = if_alloc(IFT_ETHER); |
1161 |
sc->ifp = ifp = if_alloc(IFT_ETHER); |
| 1161 |
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1162 |
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